Sequencer

17 July 2023 07:04

9] Sequencer Page 1
1] uvm_sequence_item
15 April 2023 11:57

Class properties

Testbench Component Page 2

2] UVM Sequence ( uvm_sequence)
15 April 2023 12:46

1] verification guide

https://verificationguide.com/uvm/uvm-sequence/

A sequence generates a series of sequence_item’s and sends it to the driver via sequencer, Sequence is
written by extending the uvm_sequence.

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3] Sequencer
16 April 2023 16:32

⚫ UVM Sequencer
https://vlsiverify.com/uvm/uvm-sequencer?utm_content=vc-true

The sequencer is a mediator who establishes a connection between sequence and driver. Ultimately, it passes
transactions or sequence items to the driver so that they can be driven to the DUT.

uvm_sequencer class hierarchy

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uvm_sequencer class declaration:

class uvm_sequencer #( type REQ = uvm_sequence_item, RSP = REQ ) extends uvm_sequencer_param_base

#(REQ, RSP)

A user-defined sequencer is recommended to extend from the parameterized base class “uvm_sequencer” which
is parameterized by request (REQ) and response (RSP) item types. Response item usage is optional. So, mostly
sequencer class is extended from a base class that has only a REQ item.

class my_sequencer extends uvm_sequencer #(data_item, data_rsp); // with rsp

class my_sequencer extends uvm_sequencer #(data_item); // without rsp

TLM interface is used by sequencer and driver to pass transactions. seq_item_export and
seq_item_port TLM connect methods are defined in uvm_sequencer and uvm_driver class.

class my_sequencer extends uvm_sequencer #(data_item);

`uvm_component_utils(my_sequencer)

function new (string name, uvm_component parent);

super.new(name, parent);
endfunction

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 endfunction
endclass

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Agent
20 April 2023 09:43

1]An agent is a container that holds and connects the driver, monitor, and sequencer instances. The agent develops a
structured hierarchy based on the protocol or interface requirement.

How to create a UVM agent?

1]Create a user-defined agent class extended from uvm_agent and register it in the factory.

2] In the build_phase, instantiate driver, monitor, and sequencer if it is an active agent. Instantiate monitor alone if it is a
passive agent.

3] In the connect_phase, connect driver and sequencer components.

Types of Agent

1] Active Agent
An Active agent drives stimulus to the DUT. It instantiates all three components driver, monitor, and sequencer.

2] Passive Agent
A passive agent does not drive stimulus to the DUT. It instantiates only a monitor component. It is used as a sample
interface for coverage and checker purposes.

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Q . How an agent build a structural hierarchy with various protocols?

Based on the protocol interface, the stimulus has to be driven to the DUT. So, the agent provides flexibility to build a
structural hierarchy by having different agents for different protocol interfaces.

For example:

In the below diagram,

1] agent_ahb is specific to the AHB interface and involves driver, sequence, and sequencers to drive the interface.
2] agent_axi is specific to the AXI interface and involves driver, sequence, and sequencers to drive the interface.
3] agent_apb is specific to the APB interface and involves driver, sequence, and sequencers to drive the interface.

Testbench Component Page 8

Testbench Component Page 9
1] get_type_name and get_full_name
16 April 2023 18:24

1] If you use get_type_name() then it will return only the class name irrespective of hierarchy.

class subproducer extends uvm_component;

`uvm_component_utils(subproducer);
int data =12;
uvm_blocking_put_port #(int) subpro;

function new(string path="subpro",uvm_component parent =null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
subpro=new("subpro",this);
endfunction

task main_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info(get_type_name(),$sformatf("inside the main phase of producer value of data send =%
0d",data),UVM_NONE);
subpro.put(data);
phase.drop_objection(this);
endtask

endclass

Output:

UVM_INFO testbench.sv(23) @ 0: uvm_test_top.e.p1.sp [subproducer] inside the main phase of producer value of
data send =12

Ethe class che naav print zala aahe.

2] If you use get_full_name() then it will show the complete hierarchical path starting from tb_top.test.env.... and so
on till your object type in the output LOG file.
class subproducer extends uvm_component;
`uvm_component_utils(subproducer);
int data =12;
uvm_blocking_put_port #(int) subpro;

function new(string path="subpro",uvm_component parent =null);

Others Concept Page 10

 function new(string path="subpro",uvm_component parent =null);
super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
subpro=new("subpro",this);
endfunction

task main_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info(get_full_name(),$sformatf("inside the main phase of producer value of data send =%
0d",data),UVM_NONE);
subpro.put(data);
phase.drop_objection(this);
endtask

endclass

Output:

UVM_INFO testbench.sv(23) @ 0: uvm_test_top.e.p1.sp [uvm_test_top.e.p1.sp] inside the main phase of

producer value of data send =12

Ethe serve hi hierarchical path print hote aahe.

Others Concept Page 11

1] D flip Flop
13 April 2023 10:32

1]

https://learnuvmverification.com/index.php/2015/07/29/uvm-sequences-and-transactions-application/

Transaction class of D flip flop

Uvm_sequecne_item

Sequencer 1 of d flip flop

Uvm_sequence

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In sequence flow of task body

Start_item(trans) -----> randomize() -----> finish_item(trans);

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Seq_item_port.get_next_item(trans) ----> drive data to dut through virtual interface ----->
seq_item_port.next_item();

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Projects Page 15
Projects Page 16
Projects Page 17
2] Verification of adder kumar khandale
06 July 2023 08:55

1]

Design.sv
module add(
input [3:0] a,b,
output [4:0] y
);

assign y = a + b;

endmodule

////////////////////////////////////////////////////////////
interface add_if();
logic [3:0] a;
logic [3:0] b;
logic [4:0] y;
endinterface

Testbench.sv
////////////////////////// Testbench Code

`timescale 1ns / 1ps

/////////////////////////Transaction
`include "uvm_macros.svh"
import uvm_pkg::*;

class transaction extends uvm_sequence_item;

rand bit [3:0] a;
rand bit [3:0] b;
bit [4:0] y;

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 function new(input string path = "transaction");
super.new(path);
endfunction

`uvm_object_utils_begin(transaction)
`uvm_field_int(a, UVM_DEFAULT)
`uvm_field_int(b, UVM_DEFAULT)
`uvm_field_int(y, UVM_DEFAULT)
`uvm_object_utils_end

endclass

//////////////////////////////////////////////////////////////
class generator extends uvm_sequence #(transaction);
`uvm_object_utils(generator)

transaction t;
integer i;

function new(input string path = "generator");

super.new(path);
endfunction

virtual task body();

t = transaction::type_id::create("t");
repeat(10)
begin
start_item(t);
t.randomize();
`uvm_info("GEN",$sformatf("Data send to Driver a :%0d , b :%0d",t.a,t.b), UVM_NONE);
finish_item(t);
end
endtask

endclass

////////////////////////////////////////////////////////////////////

class driver extends uvm_driver #(transaction);

`uvm_component_utils(driver)

function new(input string path = "driver", uvm_component parent = null);

super.new(path, parent);
endfunction

transaction tc;
virtual add_if aif;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
tc = transaction::type_id::create("tc");

if(!uvm_config_db #(virtual add_if)::get(this,"","aif",aif))

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 if(!uvm_config_db #(virtual add_if)::get(this,"","aif",aif))
`uvm_error("DRV","Unable to access uvm_config_db");
endfunction

virtual task run_phase(uvm_phase phase);

forever begin

seq_item_port.get_next_item(tc);
aif.a <= tc.a;
aif.b <= tc.b;
`uvm_info("DRV", $sformatf("Trigger DUT a: %0d ,b : %0d",tc.a, tc.b), UVM_NONE);
seq_item_port.item_done();
#10;

end
endtask
endclass

////////////////////////////////////////////////////////////////////////
class monitor extends uvm_monitor;
`uvm_component_utils(monitor)

uvm_analysis_port #(transaction) send;

function new(input string path = "monitor", uvm_component parent = null);

super.new(path, parent);
send = new("send", this);
endfunction

transaction t;
virtual add_if aif;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
t = transaction::type_id::create("t");

if(!uvm_config_db #(virtual add_if)::get(this,"","aif",aif))

`uvm_error("MON","Unable to access uvm_config_db");
endfunction

virtual task run_phase(uvm_phase phase);

forever begin
#10;
t.a = aif.a;
t.b = aif.b;
t.y = aif.y;
`uvm_info("MON", $sformatf("Data send to Scoreboard a : %0d , b : %0d and y : %0d", t.a,t.b,t.y),
UVM_NONE);
send.write(t);
end
endtask
endclass

///////////////////////////////////////////////////////////////////////
class scoreboard extends uvm_scoreboard;
`uvm_component_utils(scoreboard)

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`uvm_component_utils(scoreboard)

uvm_analysis_imp #(transaction,scoreboard) recv;

transaction tr;

function new(input string path = "scoreboard", uvm_component parent = null);

super.new(path, parent);
recv = new("recv", this);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
tr = transaction::type_id::create("tr");
endfunction

virtual function void write(input transaction t);

tr = t;
`uvm_info("SCO",$sformatf("Data rcvd from Monitor a: %0d , b : %0d and y : %0d",tr.a,tr.b,tr.y), UVM_NONE);

if(tr.y == tr.a + tr.b)

`uvm_info("SCO","Test Passed", UVM_NONE)
else
`uvm_info("SCO","Test Failed", UVM_NONE);
endfunction

endclass
////////////////////////////////////////////////

class agent extends uvm_agent;

`uvm_component_utils(agent)

function new(input string inst = "AGENT", uvm_component c);

super.new(inst, c);
endfunction

monitor m;
driver d;
uvm_sequencer #(transaction) seqr;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
m = monitor::type_id::create("m",this);
d = driver::type_id::create("d",this);
seqr = uvm_sequencer #(transaction)::type_id::create("seqr",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
d.seq_item_port.connect(seqr.seq_item_export);
endfunction

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endfunction
endclass

/////////////////////////////////////////////////////

class env extends uvm_env;

`uvm_component_utils(env)

function new(input string inst = "ENV", uvm_component c);

super.new(inst, c);
endfunction

scoreboard s;
agent a;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
s = scoreboard::type_id::create("s",this);
a = agent::type_id::create("a",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
a.m.send.connect(s.recv);
endfunction

endclass

////////////////////////////////////////////

class test extends uvm_test;

`uvm_component_utils(test)

function new(input string inst = "TEST", uvm_component c);

super.new(inst, c);
endfunction

generator gen;
env e;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
gen = generator::type_id::create("gen");
e = env::type_id::create("e",this);
endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);
gen.start(e.a.seqr);
#50;
phase.drop_objection(this);
endtask
endclass

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endclass
//////////////////////////////////////

module add_tb();

add_if aif();

add dut (.a(aif.a), .b(aif.b), .y(aif.y));

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end

initial begin
uvm_config_db #(virtual add_if)::set(null, "uvm_test_top.e.a*", "aif", aif);
run_test("test");
end

endmodule

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3] Four Bit Multiplier Kumar khandale
06 July 2023 08:40

Design.sv
module mul(
input [3:0] a,b,
output [7:0] y
);

assign y = a * b;

endmodule

///////////////////////////////////////////

interface mul_if;
logic [3:0] a;
logic [3:0] b;
logic [7:0] y;

endinterface

Testbench.sv
`include "uvm_macros.svh"
import uvm_pkg::*;

////////////////////////////////////////////////////////////
class transaction extends uvm_sequence_item;

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class transaction extends uvm_sequence_item;
`uvm_object_utils(transaction)

rand bit [3:0] a;

rand bit [3:0] b;
bit [7:0] y;

function new(input string path = "transaction");

super.new(path);
endfunction

endclass

////////////////////////////////////////////////////////////////////////

class generator extends uvm_sequence#(transaction);

`uvm_object_utils(generator)

transaction tr;

function new(input string path = "generator");

super.new(path);
endfunction

virtual task body();

repeat(15)
begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize());
`uvm_info("SEQ", $sformatf("a : %0d b : %0d y : %0d", tr.a, tr.b, tr.y), UVM_NONE);
finish_item(tr);
end
endtask

endclass
//////////////////////////////////////////////////////////////////////////////

class drv extends uvm_driver#(transaction);

`uvm_component_utils(drv)

transaction tr;
virtual mul_if mif;

function new(input string path = "drv", uvm_component parent = null);

super.new(path,parent);
endfunction

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 endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
if(!uvm_config_db#(virtual mul_if)::get(this,"","mif",mif))//uvm_test_top.env.agent.drv.aif
`uvm_error("drv","Unable to access Interface");
endfunction

virtual task run_phase(uvm_phase phase);

tr = transaction::type_id::create("tr");
forever begin
seq_item_port.get_next_item(tr);
mif.a <= tr.a;
mif.b <= tr.b;
`uvm_info("DRV", $sformatf("a : %0d b : %0d y : %0d", tr.a, tr.b, tr.y), UVM_NONE);
seq_item_port.item_done();
#20;
end
endtask

endclass

//////////////////////////////////////////////////////////////////////////
class mon extends uvm_monitor;
`uvm_component_utils(mon)

uvm_analysis_port#(transaction) send;
transaction tr;
virtual mul_if mif;

function new(input string inst = "mon", uvm_component parent = null);

super.new(inst,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
tr = transaction::type_id::create("tr");
send = new("send", this);
if(!uvm_config_db#(virtual mul_if)::get(this,"","mif",mif))//uvm_test_top.env.agent.drv.aif
`uvm_error("drv","Unable to access Interface");
endfunction

virtual task run_phase(uvm_phase phase);

forever begin
#20;
tr.a = mif.a;
tr.b = mif.b;
tr.y = mif.y;
`uvm_info("MON", $sformatf("a : %0d b : %0d y : %0d", tr.a, tr.b, tr.y), UVM_NONE);
send.write(tr);
end
endtask

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 endtask

endclass

/////////////////////////////////////////////////////////////////////////
class sco extends uvm_scoreboard;
`uvm_component_utils(sco)

uvm_analysis_imp#(transaction,sco) recv;

function new(input string inst = "sco", uvm_component parent = null);

super.new(inst,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
recv = new("recv", this);
endfunction

virtual function void write(transaction tr);

if(tr.y == (tr.a * tr.b))
`uvm_info("SCO", $sformatf("Test Passed -> a : %0d b : %0d y : %0d", tr.a, tr.b, tr.y), UVM_NONE)
else
`uvm_error("SCO", $sformatf("Test Failed -> a : %0d b : %0d y : %0d", tr.a, tr.b, tr.y))

$display("----------------------------------------------------------------");
endfunction

endclass

///////////////////////////////////////////////////////////////////////////

class agent extends uvm_agent;

`uvm_component_utils(agent)

function new(input string inst = "agent", uvm_component parent = null);

super.new(inst,parent);
endfunction

drv d;
uvm_sequencer#(transaction) seqr;
mon m;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
d = drv::type_id::create("d",this);
m = mon::type_id::create("m",this);
seqr = uvm_sequencer#(transaction)::type_id::create("seqr", this);
endfunction

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virtual function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
d.seq_item_port.connect(seqr.seq_item_export);
endfunction

endclass

///////////////////////////////////////////////////////////////////////

class env extends uvm_env;

`uvm_component_utils(env)

function new(input string inst = "env", uvm_component c);

super.new(inst,c);
endfunction

agent a;
sco s;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a = agent::type_id::create("a",this);
s = sco::type_id::create("s", this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
a.m.send.connect(s.recv);
endfunction

endclass

//////////////////////////////////////////////////////////////////
class test extends uvm_test;
`uvm_component_utils(test)

function new(input string inst = "test", uvm_component c);

super.new(inst,c);
endfunction

env e;
generator gen;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e = env::type_id::create("env",this);
gen = generator::type_id::create("gen");
endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);

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phase.raise_objection(this);
gen.start(e.a.seqr);
#20;
phase.drop_objection(this);
endtask
endclass

////////////////////////////////////////////////////////////////////
module tb;

mul_if mif();

mul dut (.a(mif.a), .b(mif.b), .y(mif.y));

initial
begin
uvm_config_db #(virtual mul_if)::set(null, "*", "mif", mif);
run_test("test");
end

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

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4] D flip Flop kumar khandale
06 July 2023 08:43

1]

Design.sv
module dff(
input clk,
input rst,
input din,
output reg dout
);

always@(posedge clk)
begin
if(rst)
dout <= 1'b0;
else
dout <= din;
end

endmodule

//////////////////////////////////////////////////

interface dff_if;
logic clk;
logic rst;
logic din;
logic dout;
endinterface

Testbench.sv
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`include "uvm_macros.svh"
import uvm_pkg::*;

//////////////////////////////////////////////////////////////

class config_dff extends uvm_object;

`uvm_object_utils(config_dff)

uvm_active_passive_enum agent_type = UVM_ACTIVE;

function new(input string path = "config_dff");

super.new(path);
endfunction

endclass

////////////////////////////////////////////////////////////
class transaction extends uvm_sequence_item;
`uvm_object_utils(transaction)

rand bit rst;

rand bit din;
bit dout;

function new(input string path = "transaction");

super.new(path);
endfunction

endclass

////////////////////////////////////////////////////////////////////////

class valid_din extends uvm_sequence#(transaction);

`uvm_object_utils(valid_din)

transaction tr;

function new(input string path = "valid_din");

super.new(path);
endfunction

virtual task body();

repeat(15)
begin

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 begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize());
tr.rst = 1'b0;
`uvm_info("SEQ", $sformatf("rst : %0b din : %0b dout : %0b", tr.rst, tr.din, tr.dout), UVM_NONE);
finish_item(tr);
end
endtask

endclass
//////////////////////////////////////////////////////////////////////////////
class rst_dff extends uvm_sequence#(transaction);
`uvm_object_utils(rst_dff)

transaction tr;

function new(input string path = "rst_dff");

super.new(path);
endfunction

virtual task body();

repeat(15)
begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize());
tr.rst = 1'b1;
`uvm_info("SEQ", $sformatf("rst : %0b din : %0b dout : %0b", tr.rst, tr.din, tr.dout), UVM_NONE);
finish_item(tr);
end
endtask

endclass

//////////////////////////////////////////////////////////////////////////////
class rand_din_rst extends uvm_sequence#(transaction);
`uvm_object_utils(rand_din_rst)

transaction tr;

function new(input string path = "rand_din_rst");

super.new(path);
endfunction

virtual task body();

repeat(15)
begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize());

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 assert(tr.randomize());
`uvm_info("SEQ", $sformatf("rst : %0b din : %0b dout : %0b", tr.rst, tr.din, tr.dout), UVM_NONE);
finish_item(tr);
end
endtask

endclass

//////////////////////////////////////////////////////////////////////////////
class drv extends uvm_driver#(transaction);
`uvm_component_utils(drv)

transaction tr;
virtual dff_if dif;

function new(input string path = "drv", uvm_component parent = null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
if(!uvm_config_db#(virtual dff_if)::get(this,"","dif",dif))//uvm_test_top.env.agent.drv.aif
`uvm_error("drv","Unable to access Interface");
endfunction

virtual task run_phase(uvm_phase phase);

tr = transaction::type_id::create("tr");
forever begin
seq_item_port.get_next_item(tr);
dif.rst <= tr.rst;
dif.din <= tr.din;
`uvm_info("DRV", $sformatf("rst : %0b din : %0b dout : %0b", tr.rst, tr.din, tr.dout), UVM_NONE);
seq_item_port.item_done();
repeat(2) @(posedge dif.clk);
end
endtask

endclass

//////////////////////////////////////////////////////////////////////////
class mon extends uvm_monitor;
`uvm_component_utils(mon)

uvm_analysis_port#(transaction) send;
transaction tr;
virtual dff_if dif;

function new(input string inst = "mon", uvm_component parent = null);

super.new(inst,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

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 virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
tr = transaction::type_id::create("tr");
send = new("send", this);
if(!uvm_config_db#(virtual dff_if)::get(this,"","dif",dif))//uvm_test_top.env.agent.drv.aif
`uvm_error("drv","Unable to access Interface");
endfunction

virtual task run_phase(uvm_phase phase);

forever begin
repeat(2) @(posedge dif.clk);
tr.rst = dif.rst;
tr.din = dif.din;
tr.dout = dif.dout;
`uvm_info("MON", $sformatf("rst : %0b din : %0b dout : %0b", tr.rst, tr.din, tr.dout), UVM_NONE);
send.write(tr);
end
endtask

endclass

/////////////////////////////////////////////////////////////////////////
class sco extends uvm_scoreboard;
`uvm_component_utils(sco)

uvm_analysis_imp#(transaction,sco) recv;

function new(input string inst = "sco", uvm_component parent = null);

super.new(inst,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
recv = new("recv", this);
endfunction

virtual function void write(transaction tr);

`uvm_info("SCO", $sformatf("rst : %0b din : %0b dout : %0b", tr.rst, tr.din, tr.dout), UVM_NONE);
if(tr.rst == 1'b1)
`uvm_info("SCO", "DFF Reset", UVM_NONE)
else if(tr.rst == 1'b0 && (tr.din == tr.dout))
`uvm_info("SCO", "TEST PASSED", UVM_NONE)
else
`uvm_info("SCO", "TEST FAILED", UVM_NONE)

$display("----------------------------------------------------------------");
endfunction

endclass

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endclass

///////////////////////////////////////////////////////////////////////////

class agent extends uvm_agent;

`uvm_component_utils(agent)

function new(input string inst = "agent", uvm_component parent = null);

super.new(inst,parent);
endfunction

drv d;
uvm_sequencer#(transaction) seqr;
mon m;

///////////////////
config_dff cfg;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

m = mon::type_id::create("m",this);
cfg = config_dff::type_id::create("cfg");

////////////////////////////////////////////////////////////
if(!uvm_config_db#(config_dff)::get(this, "", "cfg", cfg))
`uvm_error("AGENT", "FAILED TO ACCESS CONFIG");

if(cfg.agent_type == UVM_ACTIVE)
begin
d = drv::type_id::create("d",this);
seqr = uvm_sequencer#(transaction)::type_id::create("seqr", this);
end

endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
d.seq_item_port.connect(seqr.seq_item_export);
endfunction

endclass

///////////////////////////////////////////////////////////////////////

class env extends uvm_env;

`uvm_component_utils(env)

function new(input string inst = "env", uvm_component c);

super.new(inst,c);
endfunction

Projects Page 35
agent a;
sco s;
config_dff cfg;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a = agent::type_id::create("a",this);
s = sco::type_id::create("s", this);
cfg = config_dff::type_id::create("cfg");
//////////////////////////////////////////
uvm_config_db#(config_dff)::set(this, "a", "cfg", cfg);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
a.m.send.connect(s.recv);
endfunction

endclass

//////////////////////////////////////////////////////////////////
class test extends uvm_test;
`uvm_component_utils(test)

function new(input string inst = "test", uvm_component c);

super.new(inst,c);
endfunction

env e;
valid_din vdin;
rst_dff rff;
rand_din_rst rdin;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e = env::type_id::create("env",this);
vdin = valid_din::type_id::create("vdin");
rff = rst_dff::type_id::create("rff");
rdin = rand_din_rst::type_id::create("rdin");
endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);
rff.start(e.a.seqr);
#40;
vdin.start(e.a.seqr);
#40;
rdin.start(e.a.seqr);
#40;
phase.drop_objection(this);

Projects Page 36
phase.drop_objection(this);
endtask
endclass

////////////////////////////////////////////////////////////////////
module tb;

dff_if dif();

dff dut (.clk(dif.clk), .rst(dif.rst), .din(dif.din), .dout(dif.dout));

initial
begin
uvm_config_db #(virtual dff_if)::set(null, "*", "dif", dif);
run_test("test");
end

initial begin
dif.clk = 0;
end

always #10 dif.clk = ~dif.clk;

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

Projects Page 37
5] Verification of UART kumar Khandale
06 July 2023 08:47

Design.sv
`timescale 1ns / 1ps

/////////////////////////////////////////////////
///////////////clock generator

module clk_gen(
input clk, rst,
input [16:0] baud,
output reg tx_clk, rx_clk
);

int rx_max =0, tx_max = 0;

int rx_count = 0 , tx_count = 0;
//////////////////////////////////////////////

always@(posedge clk) begin

if(rst)begin
rx_max <= 0;
tx_max <= 0;
end
else begin
case(baud)
4800 : begin
rx_max <=11'd651;
tx_max <=14'd10416;
end
9600 : begin
rx_max <=11'd325;
tx_max <=14'd5208;
end
14400 : begin
rx_max <=11'd217;
tx_max <=14'd3472;
end
19200 : begin
rx_max <=11'd163;
tx_max <=14'd2604;
end
38400: begin
rx_max <=11'd81;
tx_max <=14'd1302;

Projects Page 38
 tx_max <=14'd1302;
end
57600 : begin
rx_max <=11'd54;
tx_max <=14'd868;
end
115200: begin
rx_max <=11'd27;
tx_max <=14'd434;
end
128000: begin
rx_max <=11'd24;
tx_max <=14'd392;
end
default: begin
rx_max <=11'd325;
tx_max <=14'd5208;
end
endcase
end
end

///////////////////////////////////////////
always@(posedge clk)
begin
if(rst)
begin
rx_max <= 0;
rx_count <= 0;
rx_clk <= 0;
end
else
begin
if(rx_count <= rx_max)
begin
rx_count <= rx_count + 1;
end
else
begin
rx_clk <= ~rx_clk;
rx_count <= 0;
end
end
end
////////////////////////////////////////////////////////////

always@(posedge clk)
begin
if(rst)
begin
tx_max <= 0;
tx_count <= 0;
tx_clk <= 0;
end
else
begin
if(tx_count <= tx_max)

Projects Page 39
 if(tx_count <= tx_max)
begin
tx_count <= tx_count + 1;
end
else
begin
tx_clk <= ~tx_clk;
tx_count <= 0;
end
end
end

/////////////////////////////////////////////////////

endmodule
//////////////////////////////////////////////////
module uart_tx(
input tx_clk,tx_start,
input rst,
input [7:0] tx_data,
input [3:0] length,
input parity_type,parity_en,
input stop2,
output reg tx, tx_done, tx_err
);

logic [7:0] tx_reg;

logic start_b = 0;
logic stop_b = 1;
logic parity_bit = 0;
integer count = 0;

typedef enum bit [2:0] {idle = 0, start_bit = 1, send_data = 2, send_parity = 3, send_first_stop = 4,

send_sec_stop = 5, done = 6} state_type;
state_type state = idle, next_state = idle;

////////////////////parity generator
always@(posedge tx_clk)
begin
if(parity_type == 1'b1) ///odd
begin
case(length)
4'd5 : parity_bit = ^(tx_data[4:0]); //xor
4'd6 : parity_bit = ^(tx_data[5:0]);
4'd7 : parity_bit = ^(tx_data[6:0]);
4'd8 : parity_bit = ^(tx_data[7:0]);
default : parity_bit = 1'b0;
endcase
end
else
begin
case(length)

Projects Page 40
 case(length)
4'd5 : parity_bit = ~^(tx_data[4:0]);//xnor
4'd6 : parity_bit = ~^(tx_data[5:0]);
4'd7 : parity_bit = ~^(tx_data[6:0]);
4'd8 : parity_bit = ~^(tx_data[7:0]);
default : parity_bit = 1'b0;
endcase
end
end

///////////////////// reset detector

always@(posedge tx_clk)
begin
if(rst)
state <= idle;
else
state <= next_state;
end

///////////////////next state decoder + output decoder

always@(*)
begin
case(state)
idle :
begin
tx_done = 1'b0;
tx = 1'b1;
tx_reg = {(8){1'b0}};
tx_err = 0;
if(tx_start)
next_state = start_bit;
else
next_state = idle;
end
////////////////////////
start_bit :
begin
tx_reg = tx_data;
tx = start_b;
next_state = send_data;
end
///////////////////////////

send_data:
begin
if(count < (length - 1))
begin
next_state = send_data;
tx = tx_reg[count];
end
else if (parity_en)
begin
tx = tx_reg[count];
next_state = send_parity;

Projects Page 41
 next_state = send_parity;
end
else
begin
tx = tx_reg[count];
next_state = send_first_stop;
end
end
////////////////////////////////////////////////

send_parity:
begin
tx = parity_bit;
next_state = send_first_stop;
end
///////////////////////////////////////////////////

send_first_stop :
begin
tx = stop_b;
if(stop2)
next_state = send_sec_stop;
else
next_state = done;
end
////////////////////////////////////
send_sec_stop :
begin
tx = stop_b;
next_state = done;
end

////////////////////////////////

done :
begin
tx_done = 1'b1;
next_state = idle;
end
//////////////////////////////////////////////////
default : next_state = idle;

endcase
end
///////////////////////////////////////////////////////////////////////////////////////////////////////////

always@(posedge tx_clk)
begin
case(state)
idle : begin
count <= 0;
end

start_bit : begin
count <= 0;

Projects Page 42
 count <= 0;
end

send_data: begin
count <= count + 1;
end

send_parity: begin
count <= 0;
end

send_first_stop : begin
count <= 0;
end

send_sec_stop : begin
count <= 0;
end

done : begin
count <= 0;
end

default : count <= 0;

endcase
end

////////////////////////////////////////////////////////////////////

endmodule

///////////////////////////////////////////////////UART RX

module uart_rx(
input rx_clk,rx_start,
input rst, rx,
input [3:0] length,
input parity_type,parity_en,
input stop2,
output reg [7:0] rx_out,
output logic rx_done, rx_error
);

logic parity = 0;
logic [7:0] datard = 0;
int count = 0;
int bit_count = 0;

typedef enum bit [2:0] {idle = 0, start_bit = 1, recv_data = 2, check_parity = 3, check_first_stop = 4,

check_sec_stop= 5, done = 6} state_type;
state_type state = idle, next_state = idle;
///////////////////// reset detector
always@(posedge rx_clk)
begin
if(rst)

Projects Page 43
 if(rst)
state <= idle;
else
state <= next_state;
end

/////////////////////////////////////////////////////////
///////////////////next_State decoder + output

///////////////////// reset detector

always@(*)
begin
case(state)
idle:
begin
rx_done = 0;
rx_error = 0;
if(rx_start && !rx)
next_state = start_bit;
else
next_state = idle;

end

////////////////////////////////////////////////

start_bit:
begin
if(count == 7 && rx)
begin
next_state = idle;
end
else if (count == 15)
begin
next_state = recv_data;
end
else
begin
next_state = start_bit;
end
end

//////////////////////////////////////////////////////////////////
recv_data: begin

if(count == 7)
begin
datard[7:0] = {rx,datard[7:1]};
end
else if(count == 15 && bit_count == (length - 1))
begin

case(length)

Projects Page 44
 case(length)
5: rx_out = datard[7:3];
6: rx_out = datard[7:2];
7: rx_out = datard[7:1];
8: rx_out = datard[7:0];
default : rx_out = 8'h00;
endcase
//////////////////////////////////

if(parity_type)
parity = ^datard;
else
parity = ~^datard;
////////////////////////////////////////////

if(parity_en)
next_state = check_parity;
else
next_state = check_first_stop;
/////////////////////////////////////////
end
else
next_state = recv_data;

end
//////////////////////////////////////////////////

check_parity: begin

if(count == 7)
begin
if(rx == parity)
rx_error = 1'b0;
else
rx_error = 1'b1;
end
else if (count == 15)
begin
next_state = check_first_stop;
end
else
begin
next_state = check_parity;
end

end
////////////////////////////////////////////////////////////////////////////
check_first_stop :
begin
if(count == 7)
begin
if(rx != 1'b1)
rx_error = 1'b1;
else
rx_error = 1'b0;

Projects Page 45
 rx_error = 1'b0;
end
else if (count == 15)
begin
if(stop2)
next_state = check_sec_stop;
else
next_state = done;
end
end

////////////////////////////////////////////////////////////////////////////////
check_sec_stop: begin
if(count == 7)
begin
if(rx != 1'b1)
rx_error = 1'b1;
else
rx_error = 1'b0;
end
else if (count == 15)
begin
next_state = done;
end

end

/////////////////////////////////////////////////////////////////////////
done : begin
rx_done = 1'b1;
next_state = idle;
rx_error = 1'b0;
end
endcase
end

///////////////////////////////////////////////////////////////////////////////////////////////////

///////////////////// reset detector

always@(posedge rx_clk)
begin
case(state)
idle:
begin
count <= 0;
bit_count <= 0;
end

////////////////////////////////////////////////

start_bit:
begin
if(count < 15)
count <= count + 1;
else
count <= 0;
end

Projects Page 46
 end

//////////////////////////////////////////////////////////////////
recv_data: begin
if(count < 15)
count <= count + 1;
else begin
count <= 0;
bit_count <= bit_count + 1;
end

end
//////////////////////////////////////////////////

check_parity: begin
if(count < 15)
count <= count + 1;
else
count <= 0;

end
////////////////////////////////////////////////////////////////////////////
check_first_stop :
begin
if(count < 15)
count <= count + 1;
else
count <= 0;
end

////////////////////////////////////////////////////////////////////////////////
check_sec_stop: begin
if(count < 15)
count <= count + 1;
else
count <= 0;

end

/////////////////////////////////////////////////////////////////////////
done : begin
count <= 0;
bit_count <= 0;
end
endcase
end

endmodule

///////////////////////////////////////////////////////////////////

Projects Page 47
 /////////////////////////////////

module uart_top
(
input clk, rst,
input tx_start, rx_start,
input [7:0] tx_data,
input [16:0] baud,
input [3:0] length,
input parity_type, parity_en,
input stop2,
output tx_done,rx_done, tx_err,rx_err,
output [7:0] rx_out
);

wire tx_clk, rx_clk;

wire tx_rx;

clk_gen clk_dut (clk, rst, baud,tx_clk, rx_clk);

uart_tx tx_dut (tx_clk,tx_start, rst, tx_data, length, parity_type, parity_en, stop2, tx_rx, tx_done, tx_err);
uart_rx rx_dut (rx_clk, rx_start, rst, tx_rx, length,parity_type, parity_en, stop2,rx_out,rx_done, rx_err);

endmodule

/////////////////////////////////////////////////////////////////////
interface uart_if;
logic clk, rst;
logic tx_start, rx_start;
logic [7:0] tx_data;
logic [16:0] baud;
logic [3:0] length;
logic parity_type, parity_en;
logic stop2;
logic tx_done,rx_done, tx_err,rx_err;
logic [7:0] rx_out;

endinterface

Testbench.sv
`include "uvm_macros.svh"
import uvm_pkg::*;

Projects Page 48
/////////////build the seq for random length with and without priority

////////////////////////////////////////////////////////////////////////////////////
class uart_config extends uvm_object; /////configuration of env
`uvm_object_utils(uart_config)

function new(string name = "uart_config");

super.new(name);
endfunction

uvm_active_passive_enum is_active = UVM_ACTIVE;

endclass

//////////////////////////////////////////////////////////

typedef enum bit [3:0] {rand_baud_1_stop = 0, rand_length_1_stop = 1, length5wp = 2, length6wp = 3,

length7wp = 4, length8wp = 5, length5wop = 6, length6wop = 7, length7wop = 8, length8wop = 9,rand_baud_2
_stop = 11, rand_length_2_stop = 12} oper_mode;

class transaction extends uvm_sequence_item;

`uvm_object_utils(transaction)

rand oper_mode op;

logic tx_start, rx_start;
logic rst;
rand logic [7:0] tx_data;
rand logic [16:0] baud;
rand logic [3:0] length;
rand logic parity_type, parity_en;
logic stop2;
logic tx_done, rx_done, tx_err, rx_err;
logic [7:0] rx_out;

constraint baud_c { baud inside {4800,9600,14400,19200,38400,57600}; }

constraint length_c { length inside {5,6,7,8}; }

function new(string name = "transaction");

super.new(name);
endfunction

endclass : transaction

///////////////////////////////////////////////////////////////////////

///////////////////random baud - fixed length = 8 - parity enable - parity type : random - single stop
class rand_baud extends uvm_sequence#(transaction);
`uvm_object_utils(rand_baud)

transaction tr;

Projects Page 49
 function new(string name = "rand_baud");
super.new(name);
endfunction

virtual task body();

repeat(5)
begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize);
tr.op = rand_baud_1_stop;
tr.length = 8;
tr.baud = 9600;
tr.rst = 1'b0;
tr.tx_start = 1'b1;
tr.rx_start = 1'b1;
tr.parity_en = 1'b1;
tr.stop2 = 1'b0;
finish_item(tr);
end
endtask

endclass
////////////////////random baud - fixed length = 8 - parity enable - parity type : random - two stop
//////////////////////////////////////////////////////////
class rand_baud_with_stop extends uvm_sequence#(transaction);
`uvm_object_utils(rand_baud_with_stop)

transaction tr;

function new(string name = "rand_baud_with_stop");

super.new(name);
endfunction

virtual task body();

repeat(5)
begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize);
tr.op = rand_baud_2_stop;
tr.rst = 1'b0;
tr.length = 8;
tr.tx_start = 1'b1;
tr.rx_start = 1'b1;
tr.parity_en = 1'b1;
tr.stop2 = 1'b1;
finish_item(tr);
end
endtask

endclass

//////////////////////////////////////////////////////////

Projects Page 50
//////////////////////////////////////////////////////////
////////////////////fixed length = 5 - variable baud - with parity
class rand_baud_len5p extends uvm_sequence#(transaction);
`uvm_object_utils(rand_baud_len5p)

transaction tr;

function new(string name = "rand_baud_len5p");

super.new(name);
endfunction

virtual task body();

repeat(5)
begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize);
tr.op = length5wp;
tr.rst = 1'b0;
tr.tx_data = {3'b000, tr.tx_data[7:3]};
tr.length = 5;
tr.tx_start = 1'b1;
tr.rx_start = 1'b1;
tr.parity_en = 1'b1;
tr.stop2 = 1'b0;
finish_item(tr);
end
endtask

endclass

//////////////////////////////////////////////////////////
////////////////////fixed length = 6 - variable baud - with parity
class rand_baud_len6p extends uvm_sequence#(transaction);
`uvm_object_utils(rand_baud_len6p)

transaction tr;

function new(string name = "rand_baud_len6p");

super.new(name);
endfunction

virtual task body();

repeat(5)
begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize);
tr.op = length6wp;
tr.rst = 1'b0;
tr.length = 6;
tr.tx_data = {2'b00, tr.tx_data[7:2]};
tr.tx_start = 1'b1;
tr.rx_start = 1'b1;

Projects Page 51
 tr.rx_start = 1'b1;
tr.parity_en = 1'b1;
tr.stop2 = 1'b0;
finish_item(tr);
end
endtask

endclass

//////////////////////////////////////////////////////////
////////////////////fixed length = 7 - variable baud - with parity
class rand_baud_len7p extends uvm_sequence#(transaction);
`uvm_object_utils(rand_baud_len7p)

transaction tr;

function new(string name = "rand_baud_len7p");

super.new(name);
endfunction

virtual task body();

repeat(5)
begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize);
tr.op = length7wp;
tr.rst = 1'b0;
tr.length = 7;
tr.tx_data = {1'b0, tr.tx_data[7:1]};
tr.tx_start = 1'b1;
tr.rx_start = 1'b1;
tr.parity_en = 1'b1;
tr.stop2 = 1'b0;
finish_item(tr);
end
endtask

endclass

//////////////////////////////////////////////////////////
////////////////////fixed length = 8 - variable baud - with parity
class rand_baud_len8p extends uvm_sequence#(transaction);
`uvm_object_utils(rand_baud_len8p)

transaction tr;

function new(string name = "rand_baud_len8p");

super.new(name);
endfunction

virtual task body();

repeat(5)
begin
tr = transaction::type_id::create("tr");

Projects Page 52
 tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize);
tr.op = length8wp;
tr.rst = 1'b0;
tr.length = 8;
tr.tx_data = tr.tx_data[7:0];
tr.tx_start = 1'b1;
tr.rx_start = 1'b1;
tr.parity_en = 1'b1;
tr.stop2 = 1'b0;
finish_item(tr);
end
endtask

endclass

//////////////////////////////////////////////////////////
////////////////////fixed length = 5 - variable baud - without parity
class rand_baud_len5 extends uvm_sequence#(transaction);
`uvm_object_utils(rand_baud_len5)

transaction tr;

function new(string name = "rand_baud_len5");

super.new(name);
endfunction

virtual task body();

repeat(5)
begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize);
tr.op = length5wop;
tr.rst = 1'b0;
tr.length = 5;
tr.tx_data = {3'b000, tr.tx_data[7:3]};
tr.tx_start = 1'b1;
tr.rx_start = 1'b1;
tr.parity_en = 1'b0;
tr.stop2 = 1'b0;
finish_item(tr);
end
endtask

endclass

//////////////////////////////////////////////////////////
////////////////////fixed length = 6- variable baud - without parity
class rand_baud_len6 extends uvm_sequence#(transaction);
`uvm_object_utils(rand_baud_len6)

transaction tr;

Projects Page 53
 transaction tr;

function new(string name = "rand_baud_len6");

super.new(name);
endfunction

virtual task body();

repeat(5)
begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize);
tr.op = length6wop;
tr.rst = 1'b0;
tr.length = 6;
tr.tx_data = {2'b00, tr.tx_data[7:2]};
tr.tx_start = 1'b1;
tr.rx_start = 1'b1;
tr.parity_en = 1'b0;
tr.stop2 = 1'b0;
finish_item(tr);
end
endtask

endclass

//////////////////////////////////////////////////////////
////////////////////fixed length = 7- variable baud - without parity
class rand_baud_len7 extends uvm_sequence#(transaction);
`uvm_object_utils(rand_baud_len7)

transaction tr;

function new(string name = "rand_baud_len7");

super.new(name);
endfunction

virtual task body();

repeat(5)
begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize);
tr.op = length7wop;
tr.rst = 1'b0;
tr.length = 7;
tr.tx_data = {1'b0, tr.tx_data[7:1]};
tr.tx_start = 1'b1;
tr.rx_start = 1'b1;
tr.parity_en = 1'b0;
tr.stop2 = 1'b0;
finish_item(tr);
end
endtask

Projects Page 54
endclass

//////////////////////////////////////////////////////////
////////////////////fixed length = 8 - variable baud - without parity
class rand_baud_len8 extends uvm_sequence#(transaction);
`uvm_object_utils(rand_baud_len8)

transaction tr;

function new(string name = "rand_baud_len8");

super.new(name);
endfunction

virtual task body();

repeat(5)
begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize);
tr.op = length8wop;
tr.rst = 1'b0;
tr.length = 8;
tr.tx_data = tr.tx_data[7:0];
tr.tx_start = 1'b1;
tr.rx_start = 1'b1;
tr.parity_en = 1'b0;
tr.stop2 = 1'b0;
finish_item(tr);
end
endtask

endclass

///////////////////////////////////////////////////////////////////////////////////////

class driver extends uvm_driver #(transaction);

`uvm_component_utils(driver)

virtual uart_if vif;

transaction tr;

function new(input string path = "drv", uvm_component parent = null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
tr = transaction::type_id::create("tr");

if(!uvm_config_db#(virtual uart_if)::get(this,"","vif",vif))

Projects Page 55
if(!uvm_config_db#(virtual uart_if)::get(this,"","vif",vif))
`uvm_error("drv","Unable to access Interface");
endfunction

task reset_dut();

repeat(5)
begin
vif.rst <= 1'b1; ///active high reset
vif.tx_start <= 1'b0;
vif.rx_start <= 1'b0;
vif.tx_data <= 8'h00;
vif.baud <= 16'h0;
vif.length <= 4'h0;
vif.parity_type <= 1'b0;
vif.parity_en <= 1'b0;
vif.stop2 <= 1'b0;
`uvm_info("DRV", "System Reset : Start of Simulation", UVM_MEDIUM);
@(posedge vif.clk);
end
endtask

task drive();
reset_dut();
forever begin

seq_item_port.get_next_item(tr);

vif.rst <= 1'b0;

vif.tx_start <= tr.tx_start;
vif.rx_start <= tr.rx_start;
vif.tx_data <= tr.tx_data;
vif.baud <= tr.baud;
vif.length <= tr.length;
vif.parity_type <= tr.parity_type;
vif.parity_en <= tr.parity_en;
vif.stop2 <= tr.stop2;
`uvm_info("DRV", $sformatf("BAUD:%0d LEN:%0d PAR_T:%0d PAR_EN:%0d STOP:%0d TX_DATA:%0d", tr.baud,
tr.length, tr.parity_type, tr.parity_en, tr.stop2, tr.tx_data), UVM_NONE);
@(posedge vif.clk);
@(posedge vif.tx_done);
@(negedge vif.rx_done);

seq_item_port.item_done();

end
endtask

virtual task run_phase(uvm_phase phase);

drive();
endtask

Projects Page 56
endclass

//////////////////////////////////////////////////////////////////////////////////////////////

class mon extends uvm_monitor;

`uvm_component_utils(mon)

uvm_analysis_port#(transaction) send;
transaction tr;
virtual uart_if vif;

function new(input string inst = "mon", uvm_component parent = null);

super.new(inst,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
tr = transaction::type_id::create("tr");
send = new("send", this);
if(!uvm_config_db#(virtual uart_if)::get(this,"","vif",vif))//uvm_test_top.env.agent.drv.aif
`uvm_error("MON","Unable to access Interface");
endfunction

virtual task run_phase(uvm_phase phase);

forever begin
@(posedge vif.clk);
if(vif.rst)
begin
tr.rst = 1'b1;
`uvm_info("MON", "SYSTEM RESET DETECTED", UVM_NONE);
send.write(tr);
end
else
begin
@(posedge vif.tx_done);
tr.rst = 1'b0;
tr.tx_start = vif.tx_start;
tr.rx_start = vif.rx_start;
tr.tx_data = vif.tx_data;
tr.baud = vif.baud;
tr.length = vif.length;
tr.parity_type = vif.parity_type;
tr.parity_en = vif.parity_en;
tr.stop2 = vif.stop2;
@(negedge vif.rx_done);

tr.rx_out = vif.rx_out;
`uvm_info("MON", $sformatf("BAUD:%0d LEN:%0d PAR_T:%0d PAR_EN:%0d STOP:%0d TX_DATA:%0d
RX_DATA:%0d", tr.baud, tr.length, tr.parity_type, tr.parity_en, tr.stop2, tr.tx_data, tr.rx_out), UVM_NONE);
send.write(tr);
end

end

Projects Page 57
 end
endtask

endclass
//////////////////////////////////////////////////////////////////////////////////////////////////

class sco extends uvm_scoreboard;

`uvm_component_utils(sco)

uvm_analysis_imp#(transaction,sco) recv;
bit [31:0] arr[32] = '{default:0};
bit [31:0] addr = 0;
bit [31:0] data_rd = 0;

function new(input string inst = "sco", uvm_component parent = null);

super.new(inst,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
recv = new("recv", this);
endfunction

virtual function void write(transaction tr);

`uvm_info("SCO", $sformatf("BAUD:%0d LEN:%0d PAR_T:%0d PAR_EN:%0d STOP:%0d TX_DATA:%0d
RX_DATA:%0d", tr.baud, tr.length, tr.parity_type, tr.parity_en, tr.stop2, tr.tx_data, tr.rx_out), UVM_NONE);
if(tr.rst == 1'b1)
`uvm_info("SCO", "System Reset", UVM_NONE)
else if(tr.tx_data == tr.rx_out)
`uvm_info("SCO", "Test Passed", UVM_NONE)
else
`uvm_info("SCO", "Test Failed", UVM_NONE)
$display("----------------------------------------------------------------");
endfunction

endclass

//////////////////////////////////////////////////////////////////////////////////////////////

class agent extends uvm_agent;

`uvm_component_utils(agent)

uart_config cfg;

function new(input string inst = "agent", uvm_component parent = null);

super.new(inst,parent);
endfunction

driver d;
uvm_sequencer#(transaction) seqr;
mon m;

Projects Page 58
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
cfg = uart_config::type_id::create("cfg");
m = mon::type_id::create("m",this);

if(cfg.is_active == UVM_ACTIVE)
begin
d = driver::type_id::create("d",this);
seqr = uvm_sequencer#(transaction)::type_id::create("seqr", this);
end

endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
if(cfg.is_active == UVM_ACTIVE) begin
d.seq_item_port.connect(seqr.seq_item_export);
end
endfunction

endclass

//////////////////////////////////////////////////////////////////////////////////

class env extends uvm_env;

`uvm_component_utils(env)

function new(input string inst = "env", uvm_component c);

super.new(inst,c);
endfunction

agent a;
sco s;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a = agent::type_id::create("a",this);
s = sco::type_id::create("s", this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
a.m.send.connect(s.recv);
endfunction

endclass

//////////////////////////////////////////////////////////////////////////

class test extends uvm_test;

`uvm_component_utils(test)

function new(input string inst = "test", uvm_component c);

super.new(inst,c);

Projects Page 59
super.new(inst,c);
endfunction

env e;
rand_baud rb;
rand_baud_with_stop rbs;
rand_baud_len5p rb5l;
rand_baud_len6p rb6l;
rand_baud_len7p rb7l;
rand_baud_len8p rb8l;
///////////////////////

rand_baud_len5 rb5lwop;
rand_baud_len6 rb6lwop;
rand_baud_len7 rb7lwop;
rand_baud_len8 rb8lwop;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e = env::type_id::create("env",this);
rb = rand_baud::type_id::create("rb");
rbs = rand_baud_with_stop::type_id::create("rbs");
/////////////fixed length var baud with parity
rb5l = rand_baud_len5p::type_id::create("rb5l");
rb6l = rand_baud_len6p::type_id::create("rb6l");
rb7l = rand_baud_len7p::type_id::create("rb7l");
rb8l = rand_baud_len8p::type_id::create("rb8l");

///////////////fixed len var baud without parity

rb5lwop = rand_baud_len5::type_id::create("rb5lwop");
rb6lwop = rand_baud_len6::type_id::create("rb6lwop");
rb7lwop = rand_baud_len7::type_id::create("rb7lwop");
rb8lwop = rand_baud_len8::type_id::create("rb8lwop");

endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);
rb8lwop.start(e.a.seqr);
#20;
phase.drop_objection(this);
endtask
endclass

//////////////////////////////////////////////////////////////////////
module tb;

uart_if vif();

uart_top dut

Projects Page 60
 uart_top dut
(.clk(vif.clk), .rst(vif.rst), .tx_start(vif.tx_start), .rx_start(vif.rx_start), .tx_data(vif.tx_data), .baud(vif.baud), .length(
vif.length), .parity_type(vif.parity_type), .parity_en(vif.parity_en),.stop2(vif.stop2),.tx_done(vif.tx_done), .rx_done
(vif.rx_done), .tx_err(vif.tx_err), .rx_err(vif.rx_err), .rx_out(vif.rx_out));

initial begin
vif.clk <= 0;
end

always #10 vif.clk <= ~vif.clk;

initial begin
uvm_config_db#(virtual uart_if)::set(null, "*", "vif", vif);
run_test("test");
end

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end

endmodule

Projects Page 61
6] Verification of SPI kumar Khandale
06 July 2023 09:02

Design.sv
module spi_mem(
input clk, rst, cs, miso,
output reg ready, mosi, op_done
);

reg [7:0] mem [31:0] = '{default:0};

integer count = 0;
reg [15:0] datain;
reg [7:0] dataout;

typedef enum bit [2:0] {idle = 0, detect = 1, store = 2, send_addr = 3, send_data = 4, temp_del = 5} state_type;
state_type state = idle;

always@(posedge clk)
begin
if(rst)
begin
state <= idle;
count <= 0;
mosi <= 0;
ready <= 0;
op_done <= 0;

end
else
begin
case(state)
idle: begin
count <= 0;
mosi <= 0;
ready <= 0;
op_done <= 0;
datain <= 0;

if(!cs)
state <= detect;
else
state <= idle;
end

detect: begin
if(miso)
Projects Page 62
 if(miso)
state <= store; ///write
else
state <= send_addr; ///read
end

store: begin
if(count <= 15) begin
datain[count] <= miso;
count <= count + 1;
state <= store;
end
else
begin
mem[datain[7:0]] <= datain[15:8];
state <= idle;
count <= 0;
op_done <= 1'b1;
end
end

send_addr: begin
if(count <= 7) begin
count <= count + 1;
datain[count] <= miso;
state <= send_addr;
end
else begin
count <= 0;
state <= temp_del;
ready <= 1'b0;
dataout <= mem[datain];
end
end

temp_del : begin
state <= send_data;
ready <= 1'b1;
count <= 1;
mosi <= dataout[0];
end

send_data: begin

if(count <= 7)
begin
count <= count + 1;
mosi <= dataout[count];
state <= send_data;
end
else
begin
count <= 0;
state <= idle;
op_done <= 1'b1;

Projects Page 63
 op_done <= 1'b1;
end
end

default : state <= idle;

endcase
end
end
endmodule

////////////////////////////////////////////////////////////

interface spi_i;

logic clk, rst, cs, miso;

logic ready, mosi, op_done;

endinterface

Testbench.sv
`include "uvm_macros.svh"
import uvm_pkg::*;

////////////////////////////////////////////////////////////////////////////////////
class spi_config extends uvm_object; /////configuration of env
`uvm_object_utils(spi_config)

function new(string name = "spi_config");

super.new(name);
endfunction

uvm_active_passive_enum is_active = UVM_ACTIVE;

endclass

//////////////////////////////////////////////////////////

Projects Page 64
typedef enum bit [1:0] {readd = 0, writed = 1, rstdut = 2} oper_mode;

class transaction extends uvm_sequence_item;

randc logic [7:0] addr;
rand logic [7:0] din;
logic [7:0] dout;
rand oper_mode op;
logic rst;
rand logic miso;
logic cs;
logic done;
logic err;
logic ready;
logic mosi;

constraint addr_c { addr <= 10;}

`uvm_object_utils_begin(transaction)
`uvm_field_int (addr,UVM_ALL_ON)
`uvm_field_int (din,UVM_ALL_ON)
`uvm_field_int (dout,UVM_ALL_ON)
`uvm_field_int (ready,UVM_ALL_ON)
`uvm_field_int (rst,UVM_ALL_ON)
`uvm_field_int (done,UVM_ALL_ON)
`uvm_field_int (miso,UVM_ALL_ON)
`uvm_field_int (mosi,UVM_ALL_ON)
`uvm_field_int (cs,UVM_ALL_ON)
`uvm_field_int (err,UVM_ALL_ON)
`uvm_field_enum(oper_mode, op, UVM_DEFAULT)
`uvm_object_utils_end

function new(string name = "transaction");

super.new(name);
endfunction

endclass : transaction

///////////////////////////////////////////////////////////////////////

///////////////////write seq
class write_data extends uvm_sequence#(transaction);
`uvm_object_utils(write_data)

transaction tr;

function new(string name = "write_data");

super.new(name);
endfunction

virtual task body();

repeat(15)
begin
tr = transaction::type_id::create("tr");
tr.addr_c.constraint_mode(1);
start_item(tr);
assert(tr.randomize);

Projects Page 65
 assert(tr.randomize);
tr.op = writed;
finish_item(tr);
end
endtask

endclass
//////////////////////////////////////////////////////////

class read_data extends uvm_sequence#(transaction);

`uvm_object_utils(read_data)

transaction tr;

function new(string name = "read_data");

super.new(name);
endfunction

virtual task body();

repeat(15)
begin
tr = transaction::type_id::create("tr");
tr.addr_c.constraint_mode(1);
start_item(tr);
assert(tr.randomize);
tr.op = readd;
finish_item(tr);
end
endtask

endclass
/////////////////////////////////////////////////////////////////////

class reset_dut extends uvm_sequence#(transaction);

`uvm_object_utils(reset_dut)

transaction tr;

function new(string name = "reset_dut");

super.new(name);
endfunction

virtual task body();

repeat(15)
begin
tr = transaction::type_id::create("tr");
tr.addr_c.constraint_mode(1);
start_item(tr);
assert(tr.randomize);
tr.op = rstdut;
finish_item(tr);
end
endtask

endclass
////////////////////////////////////////////////////////////

Projects Page 66
class writeb_readb extends uvm_sequence#(transaction);
`uvm_object_utils(writeb_readb)

transaction tr;

function new(string name = "writeb_readb");

super.new(name);
endfunction

virtual task body();

repeat(10)
begin
tr = transaction::type_id::create("tr");
tr.addr_c.constraint_mode(1);
start_item(tr);
assert(tr.randomize);
tr.op = writed;
finish_item(tr);
end

repeat(10)
begin
tr = transaction::type_id::create("tr");
tr.addr_c.constraint_mode(1);
start_item(tr);
assert(tr.randomize);
tr.op = readd;
finish_item(tr);
end

endtask

endclass

////////////////////////////////////////////////////////////
class driver extends uvm_driver #(transaction);
`uvm_component_utils(driver)

virtual spi_i vif;

transaction tr;
logic [15:0] data; ////<- din , addr ->
logic [7:0] datard;

function new(input string path = "drv", uvm_component parent = null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
tr = transaction::type_id::create("tr");

if(!uvm_config_db#(virtual spi_i)::get(this,"","vif",vif))//uvm_test_top.env.agent.drv.aif
`uvm_error("drv","Unable to access Interface");

Projects Page 67
 `uvm_error("drv","Unable to access Interface");
endfunction

////////////////////reset task
task reset_dut();
begin
vif.rst <= 1'b1; ///active high reset
vif.miso <= 1'b0;
vif.cs <= 1'b1;
`uvm_info("DRV", "System Reset", UVM_MEDIUM);
@(posedge vif.clk);
end
endtask

///////////////////////write
task write_d();
////start of transaction
vif.rst <= 1'b0;
vif.cs <= 1'b0;
vif.miso <= 1'b0;
data = {tr.din, tr.addr};
`uvm_info("DRV", $sformatf("DATA WRITE addr : %0d din : %0d",tr.addr, tr.din), UVM_MEDIUM);
@(posedge vif.clk);
vif.miso <= 1'b1; ///write operation
@(posedge vif.clk);

for(int i = 0; i < 16 ; i++)

begin
vif.miso <= data[i];
@(posedge vif.clk);
end

@(posedge vif.op_done);

endtask

//////////////////read operation
task read_d();
////start of transaction
vif.rst <= 1'b0;
vif.cs <= 1'b0;
vif.miso <= 1'b0;
data = {8'h00, tr.addr};
@(posedge vif.clk);
vif.miso <= 1'b0; ///read operation
@(posedge vif.clk);

////send addr
for(int i = 0; i < 8 ; i++)
begin
vif.miso <= data[i];
@(posedge vif.clk);
end

///wait for data ready

@(posedge vif.ready);

///sample output data

for(int i = 0; i < 8 ; i++)

Projects Page 68
 for(int i = 0; i < 8 ; i++)
begin
@(posedge vif.clk);
datard[i] = vif.mosi;
end
`uvm_info("DRV", $sformatf("DATA READ addr : %0d dout : %0d",tr.addr,datard), UVM_MEDIUM);
@(posedge vif.op_done);

endtask

//////////////////////////

virtual task run_phase(uvm_phase phase);

forever begin

seq_item_port.get_next_item(tr);

if(tr.op == rstdut)
begin
reset_dut();
end

else if(tr.op == writed)

begin
write_d();
end
else if(tr.op == readd)
begin
read_d();
end

seq_item_port.item_done();

end
endtask

endclass

//////////////////////////////////////////////////////////////////////////////////////////////

class mon extends uvm_monitor;

`uvm_component_utils(mon)

uvm_analysis_port#(transaction) send;
transaction tr;
virtual spi_i vif;
logic [15:0] din;
logic [7:0] dout;

function new(input string inst = "mon", uvm_component parent = null);

super.new(inst,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
tr = transaction::type_id::create("tr");
send = new("send", this);

Projects Page 69
send = new("send", this);
if(!uvm_config_db#(virtual spi_i)::get(this,"","vif",vif))//uvm_test_top.env.agent.drv.aif
`uvm_error("MON","Unable to access Interface");
endfunction

virtual task run_phase(uvm_phase phase);

forever begin
@(posedge vif.clk);

if(vif.rst)
begin
tr.op = rstdut;
`uvm_info("MON", "SYSTEM RESET DETECTED", UVM_NONE);
send.write(tr);
end

else begin
@(posedge vif.clk);
if(vif.miso && !vif.cs)
begin
tr.op = writed;
@(posedge vif.clk);

for(int i = 0; i < 16 ; i++)

begin
din[i] <= vif.miso;
@(posedge vif.clk);
end

tr.addr = din[7:0];
tr.din = din[15:8];

@(posedge vif.op_done);
`uvm_info("MON", $sformatf("DATA WRITE addr:%0d data:%0d",din[7:0],din[15:8]), UVM_NONE);
send.write(tr);
end
else if (!vif.miso && !vif.cs)
begin
tr.op = readd;
@(posedge vif.clk);

for(int i = 0; i < 8 ; i++)

begin
din[i] <= vif.miso;
@(posedge vif.clk);
end
tr.addr = din[7:0];

@(posedge vif.ready);

for(int i = 0; i < 8 ; i++)

begin
@(posedge vif.clk);
dout[i] = vif.mosi;
end
@(posedge vif.op_done);
tr.dout = dout;
`uvm_info("MON", $sformatf("DATA READ addr:%0d data:%0d ",tr.addr,tr.dout), UVM_NONE);
send.write(tr);

Projects Page 70
 send.write(tr);
end
end
end
endtask

endclass
//////////////////////////////////////////////////////////////////////////////////////////////////

class sco extends uvm_scoreboard;

`uvm_component_utils(sco)

uvm_analysis_imp#(transaction,sco) recv;
bit [31:0] arr[32] = '{default:0};
bit [31:0] addr = 0;
bit [31:0] data_rd = 0;

function new(input string inst = "sco", uvm_component parent = null);

super.new(inst,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
recv = new("recv", this);
endfunction

virtual function void write(transaction tr);

if(tr.op == rstdut)
begin
`uvm_info("SCO", "SYSTEM RESET DETECTED", UVM_NONE);
end
else if (tr.op == writed)
begin
arr[tr.addr] = tr.din;
`uvm_info("SCO", $sformatf("DATA WRITE OP addr:%0d, wdata:%0d arr_wr:%0d",tr.addr,tr.din, arr[tr.addr]),
UVM_NONE);
end

else if (tr.op == readd)

begin
data_rd = arr[tr.addr];
if (data_rd == tr.dout)
`uvm_info("SCO", $sformatf("DATA MATCHED : addr:%0d, rdata:%0d",tr.addr,tr.dout), UVM_NONE)
else
`uvm_info("SCO",$sformatf("TEST FAILED : addr:%0d, rdata:%0d data_rd_arr:%0d",tr.addr,tr.dout,data_rd),
UVM_NONE)
end

$display("----------------------------------------------------------------");
endfunction

endclass

//////////////////////////////////////////////////////////////////////////////////////////////

Projects Page 71
class agent extends uvm_agent;
`uvm_component_utils(agent)

spi_config cfg;

function new(input string inst = "agent", uvm_component parent = null);

super.new(inst,parent);
endfunction

driver d;
uvm_sequencer#(transaction) seqr;
mon m;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
cfg = spi_config::type_id::create("cfg");
m = mon::type_id::create("m",this);

if(cfg.is_active == UVM_ACTIVE)
begin
d = driver::type_id::create("d",this);
seqr = uvm_sequencer#(transaction)::type_id::create("seqr", this);
end

endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
if(cfg.is_active == UVM_ACTIVE) begin
d.seq_item_port.connect(seqr.seq_item_export);
end
endfunction

endclass

//////////////////////////////////////////////////////////////////////////////////

class env extends uvm_env;

`uvm_component_utils(env)

function new(input string inst = "env", uvm_component c);

super.new(inst,c);
endfunction

agent a;
sco s;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a = agent::type_id::create("a",this);
s = sco::type_id::create("s", this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
a.m.send.connect(s.recv);
endfunction

Projects Page 72
endclass

//////////////////////////////////////////////////////////////////////////

class test extends uvm_test;

`uvm_component_utils(test)

function new(input string inst = "test", uvm_component c);

super.new(inst,c);
endfunction

env e;
write_data wdata;
read_data rdata;
writeb_readb wrrdb;
reset_dut rstdut;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e = env::type_id::create("env",this);
wdata = write_data::type_id::create("wdata");
rdata = read_data::type_id::create("rdata");
wrrdb = writeb_readb::type_id::create("wrrdb");
rstdut = reset_dut::type_id::create("rstdut");
endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);
wrrdb.start(e.a.seqr);

phase.drop_objection(this);
endtask
endclass

//////////////////////////////////////////////////////////////////////
module tb;

spi_i vif();

spi_mem dut (.clk(vif.clk), .rst(vif.rst), .cs(vif.cs), .miso(vif.miso), .ready(vif.ready), .mosi(vif.mosi), .op_done(vif.op_done));

initial begin
vif.clk <= 0;
end

always #10 vif.clk <= ~vif.clk;

initial begin
uvm_config_db#(virtual spi_i)::set(null, "*", "vif", vif);
run_test("test");
end

initial begin
$dumpfile("dump.vcd");

Projects Page 73
 $dumpfile("dump.vcd");
$dumpvars;
end

endmodule

Projects Page 74
7] Verification of I2C kumar Khandale
06 July 2023 09:05

Design.sv
module i2c_mem
(
input clk, rst, wr,
input [6:0] addr,
input [7:0] din,
output [7:0] datard,
output reg done
);

////////////////////////////
wire sda;
reg scl;
reg [7:0] addrt;
reg [7:0] temprd;
reg en;
reg sdat;
integer count = 0;

///////////////////////////////////////
typedef enum bit [3:0] {idle = 0, start = 1, send_addr = 2, get_ack1 = 3, send_data = 4, get_ack2= 5, read_data = 6,
complete = 7, get_addr = 8, send_ack1 = 9, get_data = 10, send_ack2 = 11 } state_type;
state_type state, nstate;

/////////////////////////////////////

always@(posedge clk)
begin
if(rst)
begin
addrt <= 0;
temprd <= 0;
en <= 0;
sdat <= 0;
count <= 0;
end
else begin
case(state)
idle: begin
en <= 1'b1;
scl <= 1'b1;
sdat <= 1'b1;
state <= start;
count <= 0;
done <= 1'b0;

Projects Page 75
done <= 1'b0;
temprd <= 0;
end

start: begin
sdat <= 1'b0;
addrt <= {addr,wr};
state <= send_addr;
end

send_addr: begin
if(count <= 7) begin
sdat <= addrt[count];
count <= count + 1;
end
else
begin
state <= get_ack1;
count <= 0;
en <= 1'b0;
end
end

get_ack1: begin
if(sda == 1'b0)
begin
if(wr == 1'b1)
begin
state <= send_data;
en <= 1'b1;
end
else if (wr == 1'b0 )
begin
state <= read_data;
en <= 1'b0;
end
end
else
state <= get_ack1;
end

send_data: begin
if(count <= 7) begin
sdat <= din[count];
count <= count + 1;
end
else
begin
state <= get_ack2;
count <= 0;
en <= 1'b0;
end
end

get_ack2: begin
if(sda == 1'b0)
state <= complete;
else

Projects Page 76
else
state <= get_ack2;
end

read_data: begin
if(count <= 9) begin
//temprd[count] <= sda;
temprd[7:0] <= {sda,temprd[7:1]};
count <= count + 1;
end
else
begin
state <= complete;
count <= 0;
end
end

complete: begin
if(update) begin
done <= 1'b1;
state <= idle;
end
else
state <= complete;
end

default : state <= idle;

endcase
end

end

/////////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [7:0] mem [128];

integer countn = 0;
reg [7:0] addrn, data_rd, datan;
reg sdan;
reg update;

always@(posedge clk)
begin
if(rst)
begin
for(int i = 0; i< 128; i++)
begin
mem[i] <= 0;
end

addrn <= 0;
datan <= 0;
update <= 0;
end
else
begin
case(nstate)
idle: begin
addrn <= 0;

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 addrn <= 0;
datan <= 0;
update <= 0;
data_rd <= 0;

if(scl && sdat)

nstate <= start;
else
nstate <= idle;
end

start: begin
if(scl && !sdat)
nstate <= get_addr;
else
nstate <= start;
end

get_addr: begin
if(countn <= 7) begin
addrn[countn] <= sdat;
countn <= countn + 1;
end
else
begin
nstate <= send_ack1;
countn <= 0;

if(addrn[0] == 1'b0)
begin
data_rd <= mem[addrn[7:1]];
end

end
end

send_ack1:begin
sdan <= 1'b0;
if(addrn[0] == 1'b1 && state == send_data)
begin
nstate <= get_data;
end
else if(addrn[0] == 1'b0 && state == read_data)
nstate <= send_data;
else
nstate <= send_ack1;
end

get_data: begin
if(countn <= 7) begin
datan[countn] <= sdat;
countn <= countn + 1;
end
else
begin
nstate <= send_ack2;
countn <= 0;
mem[addrn[7:1]] <= datan;

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 mem[addrn[7:1]] <= datan;
end
end

send_ack2:begin
sdan <= 1'b0;
nstate <= complete;
end

send_data: begin
if(countn <= 7) begin
sdan <= data_rd[countn];
countn <= countn + 1;
end
else
begin
nstate <= complete;
countn <= 0;
end
end

complete : begin
update <= 1'b1;
nstate <= idle;
end

default: nstate <= idle;

endcase
end
end
////////////////////////////////////////////////////////////////////////

assign sda = (en == 1'b1) ? sdat : sdan;

assign datard = temprd;
endmodule

////////////////////////////////////////////////////////////////////////////////

interface i2c_i;

logic clk, rst, wr;

logic [6:0] addr;
logic [7:0] din;
logic [7:0] datard;
logic done;

endinterface

Projects Page 79
Testbench.sv
`include "uvm_macros.svh"
import uvm_pkg::*;

//////////////////////////////////////////////////////////

typedef enum bit [1:0] {readd = 0, writed = 1, rstdut = 2} oper_mode;

class transaction extends uvm_sequence_item;

`uvm_object_utils(transaction)

oper_mode op;
logic wr;
randc logic [6:0] addr;
rand logic [7:0] din;
logic [7:0] datard;
logic done;

constraint addr_c { addr <= 10;}

function new(string name = "transaction");

super.new(name);
endfunction

endclass : transaction

///////////////////////////////////////////////////////////////////////

///////////////////write seq
class write_data extends uvm_sequence#(transaction);
`uvm_object_utils(write_data)

transaction tr;

function new(string name = "write_data");

super.new(name);
endfunction

virtual task body();

repeat(15)
begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize);

Projects Page 80
 assert(tr.randomize);
tr.op = writed;
`uvm_info("SEQ", $sformatf("MODE : WRITE DIN : %0d ADDR : %0d ", tr.din, tr.addr), UVM_NONE);
finish_item(tr);
end
endtask

endclass
//////////////////////////////////////////////////////////

class read_data extends uvm_sequence#(transaction);

`uvm_object_utils(read_data)

transaction tr;

function new(string name = "read_data");

super.new(name);
endfunction

virtual task body();

repeat(15)
begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize);
tr.op = readd;
`uvm_info("SEQ", $sformatf("MODE : READ ADDR : %0d ", tr.addr), UVM_NONE);
finish_item(tr);
end
endtask

endclass
/////////////////////////////////////////////////////////////////////

class reset_dut extends uvm_sequence#(transaction);

`uvm_object_utils(reset_dut)

transaction tr;

function new(string name = "reset_dut");

super.new(name);
endfunction

virtual task body();

repeat(15)
begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize);
tr.op = rstdut;
`uvm_info("SEQ", "MODE : RESET", UVM_NONE);
finish_item(tr);
end
endtask

Projects Page 81
endclass
////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////
class driver extends uvm_driver #(transaction);
`uvm_component_utils(driver)

virtual i2c_i vif;

transaction tr;

function new(input string path = "drv", uvm_component parent = null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
tr = transaction::type_id::create("tr");

if(!uvm_config_db#(virtual i2c_i)::get(this,"","vif",vif))//uvm_test_top.env.agent.drv.aif
`uvm_error("drv","Unable to access Interface");
endfunction

////////////////////reset task
task reset_dut();
begin
`uvm_info("DRV", "System Reset", UVM_MEDIUM);
vif.rst <= 1'b1; ///active high reset
vif.addr <= 0;
vif.din <= 0;
vif.wr <= 0;
@(posedge vif.clk);
end
endtask

///////////////////////write
task write_d();
`uvm_info("DRV", $sformatf("mode : WRITE addr : %0d din : %0d", tr.addr, tr.din), UVM_NONE);
vif.rst <= 1'b0;
vif.wr <= 1'b1;
vif.addr <= tr.addr;
vif.din <= tr.din;
@(posedge vif.done);

endtask

task read_d();
`uvm_info("DRV", $sformatf("mode : READ addr : %0d din : %0d", tr.addr, tr.din), UVM_NONE);
vif.rst <= 1'b0;
vif.wr <= 1'b0;
vif.addr <= tr.addr;
vif.din <= 0;

Projects Page 82
 vif.din <= 0;
@(posedge vif.done);
endtask

virtual task run_phase(uvm_phase phase);

forever begin

seq_item_port.get_next_item(tr);

if(tr.op == rstdut)
begin
reset_dut();
end

else if(tr.op == writed)

begin
write_d();
end

else if(tr.op == readd)

begin
read_d();
end

seq_item_port.item_done();

end
endtask

endclass

//////////////////////////////////////////////////////////////////////////////////////////////

class mon extends uvm_monitor;

`uvm_component_utils(mon)

uvm_analysis_port#(transaction) send;
transaction tr;
virtual i2c_i vif;
logic [15:0] din;
logic [7:0] dout;

function new(input string inst = "mon", uvm_component parent = null);

super.new(inst,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
tr = transaction::type_id::create("tr");
send = new("send", this);
if(!uvm_config_db#(virtual i2c_i)::get(this,"","vif",vif))//uvm_test_top.env.agent.drv.aif
`uvm_error("MON","Unable to access Interface");
endfunction

Projects Page 83
 endfunction

virtual task run_phase(uvm_phase phase);

forever begin
@(posedge vif.clk);

if(vif.rst)
begin
tr.op = rstdut;
`uvm_info("MON", "SYSTEM RESET DETECTED", UVM_NONE);
send.write(tr);
end

else begin

if(vif.wr)
begin
tr.op = writed;
tr.addr = vif.addr;
tr.wr = 1;
tr.din = vif.din;
@(posedge vif.done);
`uvm_info("MON", $sformatf("DATA WRITE addr:%0d data:%0d",tr.addr,tr.din), UVM_NONE);
send.write(tr);
end
else if (!vif.wr)
begin
tr.op = readd;
tr.addr = vif.addr;
tr.wr = 0;
tr.din = vif.din;
@(posedge vif.done);
tr.datard = vif.datard;
`uvm_info("MON", $sformatf("DATA READ addr:%0d data:%0d ",tr.addr,tr.datard), UVM_NONE);
send.write(tr);
end
end
end
endtask

endclass
//////////////////////////////////////////////////////////////////////////////////////////////////

class sco extends uvm_scoreboard;

`uvm_component_utils(sco)

uvm_analysis_imp#(transaction,sco) recv;
bit [7:0] arr[128] = '{default:0};
bit [7:0] data_rd = 0;

function new(input string inst = "sco", uvm_component parent = null);

super.new(inst,parent);
endfunction

Projects Page 84
 virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
recv = new("recv", this);
endfunction

virtual function void write(transaction tr);

if(tr.op == rstdut)
begin
`uvm_info("SCO", "SYSTEM RESET DETECTED", UVM_NONE);
end
else if (tr.op == writed)
begin
arr[tr.addr] = tr.din;
`uvm_info("SCO", $sformatf("DATA WRITE OP addr:%0d, wdata:%0d arr_wr:%0d",tr.addr,tr.din, arr[tr.addr]),
UVM_NONE);
end

else if (tr.op == readd)

begin
data_rd = arr[tr.addr];
if (data_rd == tr.datard)
`uvm_info("SCO", $sformatf("DATA MATCHED : addr:%0d, rdata:%0d",tr.addr,tr.datard), UVM_NONE)
else
`uvm_info("SCO",$sformatf("TEST FAILED : addr:%0d, rdata:%0d data_rd_arr:%
0d",tr.addr,tr.datard,data_rd), UVM_NONE)
end

$display("----------------------------------------------------------------");
endfunction

endclass

//////////////////////////////////////////////////////////////////////////////////////////////

class agent extends uvm_agent;

`uvm_component_utils(agent)

function new(input string inst = "agent", uvm_component parent = null);

super.new(inst,parent);
endfunction

driver d;
uvm_sequencer#(transaction) seqr;
mon m;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

Projects Page 85
 m = mon::type_id::create("m",this);
d = driver::type_id::create("d",this);
seqr = uvm_sequencer#(transaction)::type_id::create("seqr", this);

endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
d.seq_item_port.connect(seqr.seq_item_export);
endfunction

endclass

//////////////////////////////////////////////////////////////////////////////////

class env extends uvm_env;

`uvm_component_utils(env)

function new(input string inst = "env", uvm_component c);

super.new(inst,c);
endfunction

agent a;
sco s;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a = agent::type_id::create("a",this);
s = sco::type_id::create("s", this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
a.m.send.connect(s.recv);
endfunction

endclass

//////////////////////////////////////////////////////////////////////////

class test extends uvm_test;

`uvm_component_utils(test)

function new(input string inst = "test", uvm_component c);

super.new(inst,c);
endfunction

env e;
write_data wdata;
read_data rdata;
reset_dut rstdut;

virtual function void build_phase(uvm_phase phase);

Projects Page 86
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
e = env::type_id::create("env",this);
wdata = write_data::type_id::create("wdata");
rdata = read_data::type_id::create("rdata");
rstdut = reset_dut::type_id::create("rstdut");
endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);
rstdut.start(e.a.seqr);

wdata.start(e.a.seqr);

rdata.start(e.a.seqr);

phase.drop_objection(this);
endtask
endclass

//////////////////////////////////////////////////////////////////////
module tb;

i2c_i vif();

i2c_mem dut (.clk(vif.clk), .rst(vif.rst), .wr(vif.wr), .addr(vif.addr), .din(vif.din), .datard(vif.datard), .done(vif.done));

initial begin
vif.clk <= 0;
end

always #10 vif.clk <= ~vif.clk;

initial begin
uvm_config_db#(virtual i2c_i)::set(null, "*", "vif", vif);
run_test("test");
end

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end

endmodule

Projects Page 87
8] Verification of APB_RAM kumar Khandale
06 July 2023 09:08

Design.sv
// Code your design here
module apb_ram (
input presetn,
input pclk,
input psel,
input penable,
input pwrite,
input [31:0] paddr, pwdata,
output reg [31:0] prdata,
output reg pready, pslverr
);

reg [31:0] mem [32];

typedef enum {idle = 0, setup = 1, access = 2, transfer = 3} state_type;

state_type state = idle;

always@(posedge pclk)
begin
if(presetn == 1'b0) //active low
begin
state <= idle;
prdata <= 32'h00000000;
pready <= 1'b0;
pslverr <= 1'b0;

for(int i = 0; i < 32; i++)

begin
mem[i] <= 0;
end

end
else
begin

case(state)
idle :
begin
prdata <= 32'h00000000;
pready <= 1'b0;
pslverr <= 1'b0;
state <= setup;
end

Projects Page 88
end

setup: ///start of transaction

begin
if(psel == 1'b1)
state <= access;
else
state <= setup;

end

access:
begin
if(pwrite && penable)
begin
if(paddr < 32)
begin
mem[paddr] <= pwdata;
state <= transfer;
pslverr <= 1'b0;
pready <= 1'b1;
end
else
begin
state <= transfer;
pready <= 1'b1;
pslverr <= 1'b1;
end
end
else if (!pwrite && penable)
begin
if(paddr < 32)
begin
prdata <= mem[paddr];
state <= transfer;
pready <= 1'b1;
pslverr <= 1'b0;
end
else
begin
state <= transfer;
pready <= 1'b1;
pslverr <= 1'b1;
prdata <= 32'hxxxxxxxx;
end
end
else
state <= setup;
end

transfer: begin
state <= setup;
pready <= 1'b0;
pslverr <= 1'b0;
end

Projects Page 89
 default : state <= idle;

endcase

end
end

endmodule

//////////////////////////////////////////////////
interface apb_if ();
// Signals
logic pclk;
logic presetn;
logic [31:0] paddr;
logic pwrite;
logic [31:0] pwdata;
logic penable;
logic psel;
logic [31:0] prdata;
logic pslverr;
logic pready;

endinterface : apb_if

Projects Page 90
Testbench.sv
`timescale 1ns / 1ps

/*
module tb();

reg presetn = 0;
reg pclk = 0;
reg psel = 0;
reg penable = 0 ;
reg pwrite = 0;
reg [31:0] paddr = 0, pwdata = 0;
wire [31:0] prdata;
wire pready, pslverr;

apb_ram dut (presetn, pclk, psel, penable, pwrite, paddr, pwdata, prdata, pready, pslverr);

always #10 pclk = ~pclk;

initial begin
presetn = 0;
repeat(5) @(posedge pclk);
presetn = 1;
psel = 1;
pwrite = 1;
paddr = 12;
pwdata = 35;
@(posedge pclk);
penable = 1;
@(posedge pready);
psel = 0;
penable = 0;
@(posedge pclk);
psel = 1;
pwrite = 1'b0;
paddr = 12;
pwdata = 35;
@(posedge pclk);
penable = 1'b1;
@(posedge pready);
psel = 0;
penable = 0;
@(posedge pclk);
psel = 1;
pwrite = 1;
paddr = 45;
pwdata = 35;
@(posedge pclk);
penable = 1;
@(posedge pready);

Projects Page 91
 @(posedge pready);
psel = 0;
penable = 0;
@(posedge pclk);
psel = 1;
pwrite = 0;
paddr = 45;
pwdata = 35;
@(posedge pclk);
penable = 1;
@(posedge pready);
@(posedge pclk);
$stop();
end

endmodule

*/

`include "uvm_macros.svh"
import uvm_pkg::*;

////////////////////////////////////////////////////////////////////////////////////
class abp_config extends uvm_object; /////configuration of env
`uvm_object_utils(abp_config)

function new(string name = "abp_config");

super.new(name);
endfunction

uvm_active_passive_enum is_active = UVM_ACTIVE;

endclass

///////////////////////////////////////////////////////

typedef enum bit [1:0] {readd = 0, writed = 1, rst = 2} oper_mode;

//////////////////////////////////////////////////////////////////////////////////

class transaction extends uvm_sequence_item;

rand oper_mode op;

rand logic PWRITE;
rand logic [31 : 0] PWDATA;
rand logic [31 : 0] PADDR;

// Output Signals of DUT for APB UART's transaction

logic PREADY;
logic PSLVERR;

Projects Page 92
 logic PSLVERR;
logic [31: 0] PRDATA;

`uvm_object_utils_begin(transaction)
`uvm_field_int (PWRITE,UVM_ALL_ON)
`uvm_field_int (PWDATA,UVM_ALL_ON)
`uvm_field_int (PADDR,UVM_ALL_ON)
`uvm_field_int (PREADY,UVM_ALL_ON)
`uvm_field_int (PSLVERR,UVM_ALL_ON)
`uvm_field_int (PRDATA,UVM_ALL_ON)
`uvm_field_enum(oper_mode, op, UVM_DEFAULT)
`uvm_object_utils_end

constraint addr_c { PADDR <= 31; }

constraint addr_c_err { PADDR > 31; }

function new(string name = "transaction");

super.new(name);
endfunction

endclass : transaction

///////////////////////////////////////////////////////////////
/*
module tb;

transaction tr;

initial begin
tr = transaction::type_id::create("tr");
tr.randomize();
tr.print();
end

endmodule
*/
//////////////////////////////////////////////////////////////////
///////////////////write seq
class write_data extends uvm_sequence#(transaction);
`uvm_object_utils(write_data)

transaction tr;

function new(string name = "write_data");

super.new(name);
endfunction

virtual task body();

repeat(15)
begin
tr = transaction::type_id::create("tr");
tr.addr_c.constraint_mode(1);//enable
tr.addr_c_err.constraint_mode(0);//disable
start_item(tr);
assert(tr.randomize);
tr.op = writed;
finish_item(tr);

Projects Page 93
 finish_item(tr);
end
endtask

endclass
//////////////////////////////////////////////////////////
////////////////////////read seq
class read_data extends uvm_sequence#(transaction);
`uvm_object_utils(read_data)

transaction tr;

function new(string name = "read_data");

super.new(name);
endfunction

virtual task body();

repeat(15)
begin
tr = transaction::type_id::create("tr");
tr.addr_c.constraint_mode(1);
tr.addr_c_err.constraint_mode(0);//disable
start_item(tr);
assert(tr.randomize);
tr.op = readd;
finish_item(tr);
end
endtask

endclass

/////////////////////////////////////////////

class write_read extends uvm_sequence#(transaction); //////read after write

`uvm_object_utils(write_read)

transaction tr;

function new(string name = "write_read");

super.new(name);
endfunction

virtual task body();

repeat(15)
begin
tr = transaction::type_id::create("tr");
tr.addr_c.constraint_mode(1);
tr.addr_c_err.constraint_mode(0);

start_item(tr);
assert(tr.randomize);
tr.op = writed;
finish_item(tr);

Projects Page 94
 start_item(tr);
assert(tr.randomize);
tr.op = readd;
finish_item(tr);

end
endtask

endclass
///////////////////////////////////////////////////////
///////////////write bulk read bulk
class writeb_readb extends uvm_sequence#(transaction);
`uvm_object_utils(writeb_readb)

transaction tr;

function new(string name = "writeb_readb");

super.new(name);
endfunction

virtual task body();

repeat(15) begin
tr = transaction::type_id::create("tr");
tr.addr_c.constraint_mode(1);
tr.addr_c_err.constraint_mode(0);

start_item(tr);
assert(tr.randomize);
tr.op = writed;
finish_item(tr);

end

repeat(15) begin
tr = transaction::type_id::create("tr");
tr.addr_c.constraint_mode(1);
tr.addr_c_err.constraint_mode(0);

start_item(tr);
assert(tr.randomize);
tr.op = readd;
finish_item(tr);

end
endtask

endclass

/////////////////////////////////////////////////////////////////
//////////////////////slv_error_write
class write_err extends uvm_sequence#(transaction);
`uvm_object_utils(write_err)

Projects Page 95
 `uvm_object_utils(write_err)

transaction tr;

function new(string name = "write_err");

super.new(name);
endfunction

virtual task body();

repeat(15)
begin
tr = transaction::type_id::create("tr");
tr.addr_c.constraint_mode(0);
tr.addr_c_err.constraint_mode(1);

start_item(tr);
assert(tr.randomize);
tr.op = writed;
finish_item(tr);
end
endtask

endclass
///////////////////////////////////////////////////////////////
/////////////////////////read err

class read_err extends uvm_sequence#(transaction);

`uvm_object_utils(read_err)

transaction tr;

function new(string name = "read_err");

super.new(name);
endfunction

virtual task body();

repeat(15)
begin
tr = transaction::type_id::create("tr");
tr.addr_c.constraint_mode(0);
tr.addr_c_err.constraint_mode(1);

start_item(tr);
assert(tr.randomize);
tr.op = readd;
finish_item(tr);
end
endtask

endclass

///////////////////////////////////////////////////////////////

class reset_dut extends uvm_sequence#(transaction);

`uvm_object_utils(reset_dut)

Projects Page 96
 `uvm_object_utils(reset_dut)

transaction tr;

function new(string name = "reset_dut");

super.new(name);
endfunction

virtual task body();

repeat(15)
begin
tr = transaction::type_id::create("tr");
tr.addr_c.constraint_mode(1);
tr.addr_c_err.constraint_mode(0);

start_item(tr);
assert(tr.randomize);
tr.op = rst;
finish_item(tr);
end
endtask

endclass

////////////////////////////////////////////////////////////
class driver extends uvm_driver #(transaction);
`uvm_component_utils(driver)

virtual apb_if vif;

transaction tr;

function new(input string path = "drv", uvm_component parent = null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
tr = transaction::type_id::create("tr");

if(!uvm_config_db#(virtual apb_if)::get(this,"","vif",vif))//uvm_test_top.env.agent.drv.aif
`uvm_error("drv","Unable to access Interface");
endfunction

task reset_dut();

repeat(5)
begin
vif.presetn <= 1'b0;
vif.paddr <= 'h0;
vif.pwdata <= 'h0;
vif.pwrite <= 'b0;
vif.psel <= 'b0;

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 vif.psel <= 'b0;
vif.penable <= 'b0;
`uvm_info("DRV", "System Reset : Start of Simulation", UVM_MEDIUM);
@(posedge vif.pclk);
end
endtask

task drive();
reset_dut();
forever begin

seq_item_port.get_next_item(tr);

if(tr.op == rst)
begin
vif.presetn <= 1'b0;
vif.paddr <= 'h0;
vif.pwdata <= 'h0;
vif.pwrite <= 'b0;
vif.psel <= 'b0;
vif.penable <= 'b0;
@(posedge vif.pclk);
end

else if(tr.op == writed)

begin
vif.psel <= 1'b1;
vif.paddr <= tr.PADDR;
vif.pwdata <= tr.PWDATA;
vif.presetn <= 1'b1;
vif.pwrite <= 1'b1;
@(posedge vif.pclk);
vif.penable <= 1'b1;
`uvm_info("DRV", $sformatf("mode:%0s, addr:%0d, wdata:%0d, rdata:%0d, slverr:%
0d",tr.op.name(),tr.PADDR,tr.PWDATA,tr.PRDATA,tr.PSLVERR), UVM_NONE);
@(negedge vif.pready);
vif.penable <= 1'b0;
tr.PSLVERR = vif.pslverr;

end
else if(tr.op == readd)
begin
vif.psel <= 1'b1;
vif.paddr <= tr.PADDR;
vif.presetn <= 1'b1;
vif.pwrite <= 1'b0;
@(posedge vif.pclk);
vif.penable <= 1'b1;
`uvm_info("DRV", $sformatf("mode:%0s, addr:%0d, wdata:%0d, rdata:%0d, slverr:%
0d",tr.op.name(),tr.PADDR,tr.PWDATA,tr.PRDATA,tr.PSLVERR), UVM_NONE);
@(negedge vif.pready);
vif.penable <= 1'b0;
tr.PRDATA = vif.prdata;
tr.PSLVERR = vif.pslverr;
end
seq_item_port.item_done();

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 end
endtask

virtual task run_phase(uvm_phase phase);

drive();
endtask

endclass

//////////////////////////////////////////////////////////////////

class mon extends uvm_monitor;

`uvm_component_utils(mon)

uvm_analysis_port#(transaction) send;
transaction tr;
virtual apb_if vif;

function new(input string inst = "mon", uvm_component parent = null);

super.new(inst,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
tr = transaction::type_id::create("tr");
send = new("send", this);
if(!uvm_config_db#(virtual apb_if)::get(this,"","vif",vif))//uvm_test_top.env.agent.drv.aif
`uvm_error("MON","Unable to access Interface");
endfunction

virtual task run_phase(uvm_phase phase);

forever begin
@(posedge vif.pclk);
if(!vif.presetn)
begin
tr.op = rst;
`uvm_info("MON", "SYSTEM RESET DETECTED", UVM_NONE);
send.write(tr);
end
else if (vif.presetn && vif.pwrite)
begin
@(negedge vif.pready);
tr.op = writed;
tr.PWDATA = vif.pwdata;
tr.PADDR = vif.paddr;
tr.PSLVERR = vif.pslverr;
`uvm_info("MON", $sformatf("DATA WRITE addr:%0d data:%0d slverr:%
0d",tr.PADDR,tr.PWDATA,tr.PSLVERR), UVM_NONE);
send.write(tr);
end
else if (vif.presetn && !vif.pwrite)
begin
@(negedge vif.pready);
tr.op = readd;
tr.PADDR = vif.paddr;

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 tr.PADDR = vif.paddr;
tr.PRDATA = vif.prdata;
tr.PSLVERR = vif.pslverr;
`uvm_info("MON", $sformatf("DATA READ addr:%0d data:%0d slverr:%0d",tr.PADDR,
tr.PRDATA,tr.PSLVERR), UVM_NONE);
send.write(tr);
end

end
endtask

endclass

/////////////////////////////////////////////////////////////////////

class sco extends uvm_scoreboard;

`uvm_component_utils(sco)

uvm_analysis_imp#(transaction,sco) recv;
bit [31:0] arr[32] = '{default:0};
bit [31:0] addr = 0;
bit [31:0] data_rd = 0;

function new(input string inst = "sco", uvm_component parent = null);

super.new(inst,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
recv = new("recv", this);
endfunction

virtual function void write(transaction tr);

if(tr.op == rst)
begin
`uvm_info("SCO", "SYSTEM RESET DETECTED", UVM_NONE);
end
else if (tr.op == writed)
begin
if(tr.PSLVERR == 1'b1)
begin
`uvm_info("SCO", "SLV ERROR during WRITE OP", UVM_NONE);
end
else
begin
arr[tr.PADDR] = tr.PWDATA;
`uvm_info("SCO", $sformatf("DATA WRITE OP addr:%0d, wdata:%0d arr_wr:%
0d",tr.PADDR,tr.PWDATA, arr[tr.PADDR]), UVM_NONE);
end
end
else if (tr.op == readd)
begin
if(tr.PSLVERR == 1'b1)
begin

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 begin
`uvm_info("SCO", "SLV ERROR during READ OP", UVM_NONE);
end
else
begin
data_rd = arr[tr.PADDR];
if (data_rd == tr.PRDATA)
`uvm_info("SCO", $sformatf("DATA MATCHED : addr:%0d, rdata:%
0d",tr.PADDR,tr.PRDATA), UVM_NONE)
else
`uvm_info("SCO",$sformatf("TEST FAILED : addr:%0d, rdata:%0d data_rd_arr:%
0d",tr.PADDR,tr.PRDATA,data_rd), UVM_NONE)
end

end

$display("----------------------------------------------------------------");
endfunction

endclass

/////////////////////////////////////////////////////////////////////

class agent extends uvm_agent;

`uvm_component_utils(agent)

abp_config cfg;

function new(input string inst = "agent", uvm_component parent = null);

super.new(inst,parent);
endfunction

driver d;
uvm_sequencer#(transaction) seqr;
mon m;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
cfg = abp_config::type_id::create("cfg");
m = mon::type_id::create("m",this);

if(cfg.is_active == UVM_ACTIVE)
begin
d = driver::type_id::create("d",this);
seqr = uvm_sequencer#(transaction)::type_id::create("seqr", this);
end

endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
if(cfg.is_active == UVM_ACTIVE) begin
d.seq_item_port.connect(seqr.seq_item_export);
end
endfunction

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endfunction

endclass

//////////////////////////////////////////////////////////////////////////////////

class env extends uvm_env;

`uvm_component_utils(env)

function new(input string inst = "env", uvm_component c);

super.new(inst,c);
endfunction

agent a;
sco s;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a = agent::type_id::create("a",this);
s = sco::type_id::create("s", this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
a.m.send.connect(s.recv);
endfunction

endclass

//////////////////////////////////////////////////////////////////////////

class test extends uvm_test;

`uvm_component_utils(test)

function new(input string inst = "test", uvm_component c);

super.new(inst,c);
endfunction

env e;
write_read wrrd;
writeb_readb wrrdb;
write_data wdata;
read_data rdata;
write_err werr;
read_err rerr;
reset_dut rstdut;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e = env::type_id::create("env",this);
wrrd = write_read::type_id::create("wrrd");
wdata = write_data::type_id::create("wdata");
rdata = read_data::type_id::create("rdata");
wrrdb = writeb_readb::type_id::create("wrrdb");
werr = write_err::type_id::create("werr");
rerr = read_err::type_id::create("rerr");
rstdut = reset_dut::type_id::create("rstdut");
endfunction

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endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);
wrrdb.start(e.a.seqr);
#20;
phase.drop_objection(this);
endtask
endclass

//////////////////////////////////////////////////////////////////////
module tb;

apb_if vif();

apb_ram dut
(.presetn(vif.presetn), .pclk(vif.pclk), .psel(vif.psel), .penable(vif.penable), .pwrite(vif.pwrite), .paddr(vif.paddr),
.pwdata(vif.pwdata), .prdata(vif.prdata), .pready(vif.pready), .pslverr(vif.pslverr));

initial begin
vif.pclk <= 0;
end

always #10 vif.pclk <= ~vif.pclk;

initial begin
uvm_config_db#(virtual apb_if)::set(null, "*", "vif", vif);
run_test("test");
end

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end

endmodule

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9] Verification of AXI_RAM kumar Khandale
06 July 2023 09:15

Design.sv
///////////////////////////////////////////////
module axi_slave(
////////////////global control signals
input clk,
input resetn,

///////////////////write address channel

input awvalid, /// master is sending new address

output reg awready, /// slave is ready to accept request
input [3:0] awid, ////// unique ID for each transaction
input [3:0] awlen, ////// burst length AXI3 : 1 to 16, AXI4 : 1 to 256
input [2:0] awsize, ////unique transaction size : 1,2,4,8,16 ...128 bytes
input [31:0] awaddr, ////write adress of transaction
input [1:0] awburst, ////burst type : fixed , INCR , WRAP

/////////////////////write data channel

input wvalid, //// master is sending new data

output reg wready, //// slave is ready to accept new data
input [3:0] wid, /// unique id for transaction
input [31:0] wdata, //// data
input [3:0] wstrb, //// lane having valid data
input wlast, //// last transfer in write burst

///////////////write response channel

input bready, ///master is ready to accept response

output reg bvalid, //// slave has valid response
output reg [3:0] bid, ////unique id for transaction
output reg [1:0] bresp, /// status of write transaction

////////////// read address channel

output reg arready, //read address ready signal from slave

input [3:0] arid, //read address id
input [31:0] araddr, //read address signal
input [3:0] arlen, //length of the burst
input [2:0] arsize, //number of bytes in a transfer
input [1:0] arburst,//burst type - fixed, incremental, wrapping
input arvalid, //address read valid signal

///////////////////read data channel

output reg [3:0] rid, //read data id
output reg [31:0]rdata, //read data from slave
output reg [1:0] rresp, //read response signal
output reg rlast, //read data last signal
output reg rvalid, //read data valid signal

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 output reg rvalid, //read data valid signal
input rready

);

//axi_if vif();
typedef enum bit [1:0] {awidle = 2'b00, awstart = 2'b01, awreadys = 2'b10} awstate_type;
awstate_type awstate, awnext_state;

reg [31:0] awaddrt;

//////reset decoder
always_ff@(posedge clk , negedge resetn)
begin
if(!resetn) begin
awstate <= awidle; ///idle state for write address FSM
wstate <= widle; ///idle state for write data fsm
bstate <= bidle; ///// idle state for write response fsm
end
else
begin
awstate <= awnext_state;
wstate <= wnext_state;
bstate <= bnext_state;
end
end

/////////////fsm for write address channel

always_comb
begin
case(awstate)
awidle:
begin
awready = 1'b0;
awnext_state = awstart;
end

awstart:
begin
if(awvalid)
begin
awnext_state = awreadys;
awaddrt = awaddr; ////storing address
end
else
awnext_state = awstart;
end

awreadys:
begin

awready = 1'b1;

if(wstate == wreadys)
awnext_state = awidle;
else
awnext_state = awreadys;
end
endcase
end

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 end

////////////////////fsm for write data channel

reg [31:0] wdatat;

reg [7:0] mem[128] = '{default:12};
reg [31:0] retaddr;
reg [31:0] nextaddr;
reg first; /// check operation executed first time

///////////////////////////function to compute next address during FIXED burst type

function bit[31:0] data_wr_fixed (input [3:0] wstrb, input [31:0] awaddrt);
unique case (wstrb)
4'b0001: begin
mem[awaddrt] = wdatat[7:0];
end

4'b0010: begin
mem[awaddrt] = wdatat[15:8];
end

4'b0011: begin
mem[awaddrt] = wdatat[7:0];
mem[awaddrt + 1] = wdatat[15:8];
end

4'b0100: begin
mem[awaddrt] = wdatat[23:16];
end

4'b0101: begin
mem[awaddrt] = wdatat[7:0];
mem[awaddrt + 1] = wdatat[23:16];
end

4'b0110: begin
mem[awaddrt] = wdatat[15:8];
mem[awaddrt + 1] = wdatat[23:16];
end

4'b0111: begin
mem[awaddrt] = wdatat[7:0];
mem[awaddrt + 1] = wdatat[15:8];
mem[awaddrt + 2] = wdatat[23:16];
end

4'b1000: begin
mem[awaddrt] = wdatat[31:24];
end

4'b1001: begin
mem[awaddrt] = wdatat[7:0];
mem[awaddrt + 1] = wdatat[31:24];
end

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 4'b1010: begin
mem[awaddrt] = wdatat[15:8];
mem[awaddrt + 1] = wdatat[31:24];
end

4'b1011: begin
mem[awaddrt] = wdatat[7:0];
mem[awaddrt + 1] = wdatat[15:8];
mem[awaddrt + 2] = wdatat[31:24];
end

4'b1100: begin
mem[awaddrt] = wdatat[23:16];
mem[awaddrt + 1] = wdatat[31:24];
end

4'b1101: begin
mem[awaddrt] = wdatat[7:0];
mem[awaddrt + 1] = wdatat[23:16];
mem[awaddrt + 2] = wdatat[31:24];
end

4'b1110: begin
mem[awaddrt] = wdatat[15:8];
mem[awaddrt + 1] = wdatat[23:16];
mem[awaddrt + 2] = wdatat[31:24];
end

4'b1111: begin
mem[awaddrt] = wdatat[7:0];
mem[awaddrt + 1] = wdatat[15:8];
mem[awaddrt + 2] = wdatat[23:16];
mem[awaddrt + 3] = wdatat[31:24];
end
endcase
return awaddrt;
endfunction

///////////////////////////function to compute next address during INCR burst type

function bit[31:0] data_wr_incr (input [3:0] wstrb, input [31:0] awaddrt);

bit [31:0] addr;

unique case (wstrb)

4'b0001: begin
mem[awaddrt] = wdatat[7:0];
addr = awaddrt + 1;
end

4'b0010: begin
mem[awaddrt] = wdatat[15:8];
addr = awaddrt + 1;
end

4'b0011: begin
mem[awaddrt] = wdatat[7:0];
mem[awaddrt + 1] = wdatat[15:8];
addr = awaddrt + 2;

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 addr = awaddrt + 2;
end

4'b0100: begin
mem[awaddrt] = wdatat[23:16];
addr = awaddrt + 1;
end

4'b0101: begin
mem[awaddrt] = wdatat[7:0];
mem[awaddrt + 1] = wdatat[23:16];
addr = awaddrt + 2;
end

4'b0110: begin
mem[awaddrt] = wdatat[15:8];
mem[awaddrt + 1] = wdatat[23:16];
addr = awaddrt + 2;
end

4'b0111: begin
mem[awaddrt] = wdatat[7:0];
mem[awaddrt + 1] = wdatat[15:8];
mem[awaddrt + 2] = wdatat[23:16];
addr = awaddrt + 3;
end

4'b1000: begin
mem[awaddrt] = wdatat[31:24];
addr = awaddrt + 1;
end

4'b1001: begin
mem[awaddrt] = wdatat[7:0];
mem[awaddrt + 1] = wdatat[31:24];
addr = awaddrt + 2;
end

4'b1010: begin
mem[awaddrt] = wdatat[15:8];
mem[awaddrt + 1] = wdatat[31:24];
addr = awaddrt + 2;
end

4'b1011: begin
mem[awaddrt] = wdatat[7:0];
mem[awaddrt + 1] = wdatat[15:8];
mem[awaddrt + 2] = wdatat[31:24];
addr = awaddrt + 3;
end

4'b1100: begin
mem[awaddrt] = wdatat[23:16];
mem[awaddrt + 1] = wdatat[31:24];
addr = awaddrt + 2;
end

4'b1101: begin
mem[awaddrt] = wdatat[7:0];

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 mem[awaddrt] = wdatat[7:0];
mem[awaddrt + 1] = wdatat[23:16];
mem[awaddrt + 2] = wdatat[31:24];
addr = awaddrt + 3;
end

4'b1110: begin
mem[awaddrt] = wdatat[15:8];
mem[awaddrt + 1] = wdatat[23:16];
mem[awaddrt + 2] = wdatat[31:24];
addr = awaddrt + 3;
end

4'b1111: begin
mem[awaddrt] = wdatat[7:0];
mem[awaddrt + 1] = wdatat[15:8];
mem[awaddrt + 2] = wdatat[23:16];
mem[awaddrt + 3] = wdatat[31:24];
addr = awaddrt + 4;
end
endcase
return addr;
endfunction

///////////////////////Function to compute Wrapping boundary

function bit [7:0] wrap_boundary (input bit [3:0] awlen,input bit[2:0] awsize);
bit [7:0] boundary;

unique case(awlen)
4'b0001:
begin
unique case(awsize)
3'b000: begin
boundary = 2 * 1;
end
3'b001: begin
boundary = 2 * 2;

end
3'b010: begin
boundary = 2 * 4;

end
endcase
end
4'b0011:
begin
unique case(awsize)
3'b000: begin
boundary = 4 * 1;
end
3'b001: begin
boundary = 4 * 2;

end
3'b010: begin
boundary = 4 * 4;

end
endcase

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 endcase
end

4'b0111:
begin
unique case(awsize)
3'b000: begin
boundary = 8 * 1;
end
3'b001: begin
boundary = 8 * 2;

end
3'b010: begin
boundary = 8 * 4;

end
endcase
end

4'b1111:
begin
unique case(awsize)
3'b000: begin
boundary = 16 * 1;
end
3'b001: begin
boundary = 16 * 2;

end
3'b010: begin
boundary = 16 * 4;

end
endcase
end

endcase

return boundary;
endfunction
//////////////////////////////////////////////////////////////

function bit[31:0] data_wr_wrap (input [3:0] wstrb, input [31:0] awaddrt, input [7:0] wboundary);

bit [31:0] addr1, addr2, addr3, addr4;

bit [31:0] nextaddr, nextaddr2;

unique case (wstrb)

/////////////////////////////////////////////////
4'b0001: begin
mem[awaddrt] = wdatat[7:0];

if((awaddrt + 1) % wboundary == 0)
addr1 = (awaddrt + 1) - wboundary;
else
addr1 = awaddrt + 1;

return addr1;

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return addr1;
end

/////////////////////////////////////////////////

4'b0010: begin
mem[awaddrt] = wdatat[15:8];

if((awaddrt + 1) % wboundary == 0)
addr1 = (awaddrt + 1) - wboundary;
else
addr1 = awaddrt + 1;

return addr1;
end

///////////////////////////////////////////////////

4'b0011: begin
mem[awaddrt] = wdatat[7:0];

if((awaddrt + 1) % wboundary == 0)
addr1 = (awaddrt + 1) - wboundary;
else
addr1 = awaddrt + 1;

mem[addr1] = wdatat[15:8];

if((addr1 + 1) % wboundary == 0)
addr2 = (addr1 + 1) - wboundary;
else
addr2 = addr1 + 1;

return addr2;

end

///////////////////////////////////////////////

4'b0100: begin
mem[awaddrt] = wdatat[23:16];

if((awaddrt + 1) % wboundary == 0)
addr1 = (awaddrt + 1) - wboundary;
else
addr1 = awaddrt + 1;

return addr1;
end

//////////////////////////////////////////////

4'b0101: begin
mem[awaddrt] = wdatat[7:0];

if((awaddrt + 1) % wboundary == 0)
addr1 = (awaddrt + 1) - wboundary;
else
addr1 = awaddrt + 1;

mem[addr1] = wdatat[23:16];

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 mem[addr1] = wdatat[23:16];

if((addr1 + 1) % wboundary == 0)
addr2 = (addr1 + 1) - wboundary;
else
addr2 = addr1 + 1;

return addr2;

end

///////////////////////////////////////////////////

4'b0110: begin
mem[awaddrt] = wdatat[15:8];

if((awaddrt + 1) % wboundary == 0)
addr1 = (awaddrt + 1) - wboundary;
else
addr1 = awaddrt + 1;

mem[addr1] = wdatat[23:16];

if((addr1 + 1) % wboundary == 0)
addr2 = (addr1 + 1) - wboundary;
else
addr2 = addr1 + 1;

return addr2;

end
//////////////////////////////////////////////////////////////

4'b0111: begin
mem[awaddrt] = wdatat[7:0];
if((awaddrt + 1) % wboundary == 0)
addr1 = (awaddrt + 1) - wboundary;
else
addr1 = awaddrt + 1;

mem[addr1] = wdatat[15:8];

if((addr1 + 1) % wboundary == 0)
addr2 = (addr1 + 1) - wboundary;
else
addr2 = addr1 + 1;

mem[addr2] = wdatat[23:16];

if((addr2 + 1) % wboundary == 0)
addr3 = (addr2 + 1) - wboundary;
else
addr3 = addr2 + 1;

return addr3;
end

4'b1000: begin
mem[awaddrt] = wdatat[31:24];

if((awaddrt + 1) % wboundary == 0)

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 if((awaddrt + 1) % wboundary == 0)
addr1 = (awaddrt + 1) - wboundary;
else
addr1 = awaddrt + 1;

return addr1;
end

4'b1001: begin
mem[awaddrt] = wdatat[7:0];

if((awaddrt + 1) % wboundary == 0)
addr1 = (awaddrt + 1) - wboundary;
else
addr1 = awaddrt + 1;

mem[addr1] = wdatat[31:24];

if((addr1 + 1) % wboundary == 0)
addr2 = (addr1 + 1) - wboundary;
else
addr2 = addr1 + 1;

return addr2;
end

4'b1010: begin
mem[awaddrt] = wdatat[15:8];

if((awaddrt + 1) % wboundary == 0)
addr1 = (awaddrt + 1) - wboundary;
else
addr1 = awaddrt + 1;

mem[addr1] = wdatat[31:24];

if((addr1 + 1) % wboundary == 0)
addr2 = (addr1 + 1) - wboundary;
else
addr2 = addr1 + 1;

return addr2;
end

4'b1011: begin
mem[awaddrt] = wdatat[7:0];

if((awaddrt + 1) % wboundary == 0)
addr1 = (awaddrt + 1) - wboundary;
else
addr1 = awaddrt + 1;

mem[addr1] = wdatat[15:8];

if((addr1 + 1) % wboundary == 0)
addr2 = (addr1 + 1) - wboundary;
else
addr2 = addr1 + 1;

Projects Page 113

 addr2 = addr1 + 1;

mem[addr2] = wdatat[31:24];

if((addr2 + 1) % wboundary == 0)
addr3 = (addr2 + 1) - wboundary;
else
addr3 = addr2 + 1;

return addr3;

end

4'b1100: begin
mem[awaddrt] = wdatat[23:16];

if((awaddrt + 1) % wboundary == 0)
addr1 = (awaddrt + 1) - wboundary;
else
addr1 = awaddrt + 1;

mem[addr1] = wdatat[31:24];

if((addr1 + 1) % wboundary == 0)
addr2 = (addr1 + 1) - wboundary;
else
addr2 = addr1 + 1;

return addr2;
end

4'b1101: begin
mem[awaddrt] = wdatat[7:0];

if((awaddrt + 1) % wboundary == 0)
addr1 = (awaddrt + 1) - wboundary;
else
addr1 = awaddrt + 1;

mem[addr1] = wdatat[23:16];

if((addr1 + 1) % wboundary == 0)
addr2 = (addr1 + 1) - wboundary;
else
addr2 = addr1 + 1;

mem[addr2] = wdatat[31:24];

if((addr2 + 1) % wboundary == 0)
addr3 = (addr2 + 1) - wboundary;
else
addr3 = addr2 + 1;

return addr3;

end

4'b1110: begin
mem[awaddrt] = wdatat[15:8];

if((awaddrt + 1) % wboundary == 0)
addr1 = (awaddrt + 1) - wboundary;

Projects Page 114

 addr1 = (awaddrt + 1) - wboundary;
else
addr1 = awaddrt + 1;

mem[addr1] = wdatat[23:16];

if((addr1 + 1) % wboundary == 0)
addr2 = (addr1 + 1) - wboundary;
else
addr2 = addr1 + 1;

mem[addr2] = wdatat[31:24];

if((addr2 + 1) % wboundary == 0)
addr3 = (addr2 + 1) - wboundary;
else
addr3 = addr2 + 1;

return addr3;
end

4'b1111: begin
mem[awaddrt] = wdatat[7:0];

if((awaddrt + 1) % wboundary == 0)
addr1 = (awaddrt + 1) - wboundary;
else
addr1 = awaddrt + 1;

mem[addr1] = wdatat[15:8];

if((addr1 + 1) % wboundary == 0)
addr2 = (addr1 + 1) - wboundary;
else
addr2 = addr1 + 1;

mem[addr2] = wdatat[23:16];

if((addr2 + 1) % wboundary == 0)
addr3 = (addr2 + 1) - wboundary;
else
addr3 = addr2 + 1;

mem[addr3] = wdatat[31:24];

if((addr3 + 1) % wboundary == 0)
addr4 = (addr3 + 1) - wboundary;
else
addr4 = addr3 + 1;

return addr4;
end
endcase

endfunction

Projects Page 115

reg [7:0] boundary; ////storing boundary
reg [3:0] wlen_count;

typedef enum bit [2:0] {widle = 0, wstart = 1, wreadys = 2, wvalids = 3, waddr_dec = 4} wstate_type;
wstate_type wstate, wnext_state;

always_comb
begin
case(wstate)

widle: begin
wready = 1'b0;
wnext_state = wstart;
first = 1'b0;
wlen_count = 0;
end

wstart: begin
if(wvalid)
begin
wnext_state = waddr_dec;
wdatat = wdata;
end
else
begin
wnext_state = wstart;
end
end

waddr_dec: begin
wnext_state = wreadys;

if(first == 0) begin
nextaddr = awaddr;
first = 1'b1;
wlen_count = 0;
end
else if (wlen_count < (awlen + 1 ))
begin
nextaddr = retaddr;
end
else
begin
nextaddr = awaddr;
end
end

wreadys: begin

if(wlast == 1'b1) begin

wnext_state = widle;
wready = 1'b0;
wlen_count = 0;
first = 0;
end

Projects Page 116

 end
else if(wlen_count < (awlen + 1))
begin
wnext_state = wvalids;
wready = 1'b1;
end
else
wnext_state = wreadys;

case(awburst)
2'b00: ////Fixed Mode
begin
retaddr = data_wr_fixed(wstrb, awaddr); ///fixed
end

2'b01: ////Incr mode

begin
retaddr = data_wr_incr(wstrb,nextaddr);
end

2'b10: //// wrapping

begin
boundary = wrap_boundary(awlen, awsize); /////calculate wrapping boundary
retaddr = data_wr_wrap(wstrb, nextaddr, boundary); ///////generate next addr
end
endcase
end

wvalids: begin
wready = 1'b0;
wnext_state = wstart;

if(wlen_count < (awlen + 1))

wlen_count = wlen_count + 1;
else
wlen_count = wlen_count;

end
endcase
end

////////////////////////fsm for write response

typedef enum bit [1:0] {bidle = 0, bdetect_last = 1, bstart = 2, bwait = 3} bstate_type;

bstate_type bstate,bnext_state;

always_comb
begin
case(bstate)
bidle: begin
bid = 1'b0;
bresp = 1'b0;
bvalid = 1'b0;
bnext_state = bdetect_last;
end

bdetect_last: begin

Projects Page 117

 bdetect_last: begin
if(wlast)
bnext_state = bstart;
else
bnext_state = bdetect_last;
end

bstart: begin
bid = awid;
bvalid = 1'b1;
bnext_state = bwait;
if( (awaddr < 128 ) && (awsize <= 3'b010) )
bresp = 2'b00; ///okay
else if (awsize > 3'b010)
bresp = 2'b10; /////slverr
else
bresp = 2'b11; ///no slave address
end

bwait: begin
if(bready == 1'b1)
bnext_state = bidle;
else
bnext_state = bwait;
end

endcase
end

////////////////////////fsm for read address

always_ff @(posedge clk, negedge resetn)

begin
if(!resetn)
begin
arstate <= aridle;
rstate <= ridle;
end
else
begin
arstate <= arnext_state;
rstate <= rnext_state;
end
end

typedef enum bit [1:0] {aridle = 0, arstart = 1, arreadys = 2} arstate_type;

arstate_type arstate, arnext_state;

reg [31:0] araddrt; ///register address

always_comb
begin
case(arstate)
aridle: begin
arready = 1'b0;
arnext_state = arstart;
end

arstart: begin
if(arvalid == 1'b1) begin
arnext_state = arreadys;

Projects Page 118

 arnext_state = arreadys;
araddrt = araddr;
end
else
arnext_state = arstart;
end

arreadys: begin
arnext_state = aridle;
arready = 1'b1;
end
endcase
end

///////////////////////////read data in FIxed Mode

function void read_data_fixed (input [31:0] addr, input [2:0] arsize);

unique case(arsize)
3'b000: begin
rdata[7:0] = mem[addr];
end

3'b001: begin
rdata[7:0] = mem[addr];
rdata[15:8] = mem[addr + 1];
end

3'b010: begin
rdata[7:0] = mem[addr];
rdata[15:8] = mem[addr + 1];
rdata[23:16] = mem[addr + 2];
rdata[31:24] = mem[addr + 3];
end
endcase
endfunction
//////////////////////////end of function
//////////////////////////// read data in INCR Mode

function bit [31:0] read_data_incr (input [31:0] addr, input [2:0] arsize);
bit [31:0] nextaddr;

unique case(arsize)
3'b000: begin
rdata[7:0] = mem[addr];
nextaddr = addr + 1;
end

3'b001: begin
rdata[7:0] = mem[addr];
rdata[15:8] = mem[addr + 1];
nextaddr = addr + 2;
end

3'b010: begin
rdata[7:0] = mem[addr];
rdata[15:8] = mem[addr + 1];
rdata[23:16] = mem[addr + 2];
rdata[31:24] = mem[addr + 3];
nextaddr = addr + 4;
end

endcase

Projects Page 119

 endcase

return nextaddr;

endfunction

///////////////////////////////////////////end of function
function bit [31:0] read_data_wrap (input bit [31:0] addr, input bit [2:0] rsize, input [7:0] rboundary);
bit [31:0] addr1,addr2,addr3,addr4;

unique case (rsize)

3'b000: begin
rdata[7:0] = mem[addr];

if(((addr + 1) % rboundary ) == 0)
addr1 = (addr + 1) - rboundary;
else
addr1 = (addr + 1);

return addr1;
end

3'b001: begin
rdata[7:0] = mem[addr];

if(((addr + 1) % rboundary ) == 0)
addr1 = (addr + 1) - rboundary;
else
addr1 = (addr + 1);

rdata[15:8] = mem[addr1];

if(((addr1 + 1) % rboundary ) == 0)
addr2 = (addr1 + 1) - rboundary;
else
addr2 = (addr1 + 1);

return addr2;
end

3'b010: begin

rdata[7:0] = mem[addr];

if(((addr + 1) % rboundary ) == 0)
addr1 = (addr + 1) - rboundary;
else
addr1 = (addr + 1);

rdata[15:8] = mem[addr1];

if(((addr1 + 1) % rboundary ) == 0)
addr2 = (addr1 + 1) - rboundary;
else
addr2 = (addr1 + 1);

rdata[23:16] = mem[addr2];

if(((addr2 + 1) % rboundary ) == 0)
addr3 = (addr2 + 1) - rboundary;
else
addr3 = (addr2 + 1);

Projects Page 120

 addr3 = (addr2 + 1);

rdata[31:24] = mem[addr3];

if(((addr3 + 1) % rboundary ) == 0)
addr4 = (addr3 + 1) - rboundary;
else
addr4 = (addr3 + 1);

return addr4;
end

endcase

endfunction

///////////////////////////////////////
reg rdfirst;
bit [31:0] rdnextaddr, rdretaddr;
reg [3:0] len_count;
reg [7:0] rdboundary;

typedef enum bit [2:0] {ridle = 0, rstart = 1, rwait = 2, rvalids = 3, rerror = 4} rstate_type;
rstate_type rstate, rnext_state;

/////////////////////////////////
always_comb
begin
case(rstate)
ridle: begin

rid = 0;
rdfirst = 0;
rdata = 0;
rresp = 0;
rlast = 0;
rvalid = 0;
len_count = 0;

if(arvalid)
rnext_state = rstart;
else
rnext_state = ridle;
end

rstart: begin
if ((araddrt < 128) && (arsize <= 3'b010) ) begin
rid = arid;
rvalid = 1'b1;
rnext_state = rwait;
rresp = 2'b00;
unique case(arburst)

////////////////////fixed
2'b00: begin
if(rdfirst == 0) begin
rdnextaddr = araddr;
rdfirst = 1'b1;
len_count = 0;
end
else if (len_count != (arlen + 1))
begin

Projects Page 121

 begin
rdnextaddr = araddr;
end

read_data_fixed(araddrt, arsize);
end
//////////////////////end of fixed

////////////////////start of incr
2'b01: begin
if(rdfirst == 0) begin
rdnextaddr = araddr;
rdfirst = 1'b1;
len_count = 0;
end
else if (len_count != (arlen + 1))
begin
rdnextaddr = rdretaddr;
end

rdretaddr = read_data_incr(rdnextaddr, arsize);

end
///////////////////////end of incr
2'b10: begin
if(rdfirst == 0)
begin
rdnextaddr = araddr;
rdfirst = 1'b1;
len_count = 0;
end
else if (len_count != (arlen + 1))
begin
rdnextaddr = rdretaddr;
end
rdboundary = wrap_boundary(arlen, arsize);
rdretaddr = read_data_wrap(rdnextaddr, arsize, rdboundary);
end
endcase
end
else if ( (araddr >= 128) && ( arsize <= 3'b010) ) begin
rresp = 2'b11;
rvalid = 1'b1;
rnext_state = rerror;
end
else if (arsize > 3'b010) begin
rresp = 2'b10;
rvalid = 1'b1;
rnext_state = rerror;
end

end

rwait: begin
rvalid = 1'b0;
if(rready == 1'b1)
rnext_state = rvalids;
else
rnext_state = rwait;
end

rvalids: begin
len_count = len_count + 1;

Projects Page 122

 len_count = len_count + 1;
if(len_count == (arlen + 1))
begin
rnext_state = ridle;
rlast = 1'b1;
end
else
begin
rnext_state = rstart;
rlast = 1'b0;
end
end

rerror : begin
rvalid = 1'b0;

if(len_count < (arlen))

begin
if(arready)
begin
rnext_state = rstart;
len_count = len_count + 1;
end
end
else
begin
rlast = 1'b1;
rnext_state = ridle;
len_count = 0;
end
end

default : rnext_state = ridle;

endcase
end
endmodule

//////////////////////////////////////////////

interface axi_if();

////////write address channel (aw)

logic awvalid; /// master is sending new address

logic awready; /// slave is ready to accept request
logic [3:0] awid; ////// unique ID for each transaction
logic [3:0] awlen; ////// burst length AXI3 : 1 to 16, AXI4 : 1 to 256
logic [2:0] awsize; ////unique transaction size : 1,2,4,8,16 ...128 bytes
logic [31:0] awaddr; ////write adress of transaction
logic [1:0] awburst; ////burst type : fixed , INCR , WRAP

//////////write data channel (w)

logic wvalid; //// master is sending new data
logic wready; //// slave is ready to accept new data
logic [3:0] wid; /// unique id for transaction
logic [31:0] wdata; //// data
logic [3:0] wstrb; //// lane having valid data
logic wlast; //// last transfer in write burst

Projects Page 123

 //////////write response channel (b)
logic bready; ///master is ready to accept response
logic bvalid; //// slave has valid response
logic [3:0] bid; ////unique id for transaction
logic [1:0] bresp; /// status of write transaction

///////////////read address channel (ar)

logic arvalid; /// master is sending new address

logic arready; /// slave is ready to accept request
logic [3:0] arid; ////// unique ID for each transaction
logic [3:0] arlen; ////// burst length AXI3 : 1 to 16, AXI4 : 1 to 256
logic [2:0] arsize; ////unique transaction size : 1,2,4,8,16 ...128 bytes
logic [31:0] araddr; ////write adress of transaction
logic [1:0] arburst; ////burst type : fixed , INCR , WRAP

/////////// read data channel (r)

logic rvalid; //// master is sending new data

logic rready; //// slave is ready to accept new data
logic [3:0] rid; /// unique id for transaction
logic [31:0] rdata; //// data
logic [3:0] rstrb; //// lane having valid data
logic rlast; //// last transfer in write burst
logic [1:0] rresp; ///status of read transfer

////////////////

logic clk;
logic resetn;

//////////////////
logic [31:0] next_addrwr;
logic [31:0] next_addrrd;

endinterface

Testbench.sv
`include "uvm_macros.svh"
import uvm_pkg::*;

typedef enum bit [2:0] {wrrdfixed = 0, wrrdincr = 1, wrrdwrap = 2, wrrderrfix = 3, rstdut = 4 } oper_mode;

class transaction extends uvm_sequence_item;

`uvm_object_utils(transaction)

Projects Page 124

 function new(string name = "transaction");
super.new(name);
endfunction

int len = 0;
rand bit [3:0] id;
oper_mode op;
rand bit awvalid;
bit awready;
bit [3:0] awid;
rand bit [3:0] awlen;
rand bit [2:0] awsize; //4byte =010
rand bit [31:0] awaddr;
rand bit [1:0] awburst;

bit wvalid;
bit wready;
bit [3:0] wid;
rand bit [31:0] wdata;
rand bit [3:0] wstrb;
bit wlast;

bit bready;
bit bvalid;
bit [3:0] bid;
bit [1:0] bresp;

rand bit arvalid; /// master is sending new address

bit arready; /// slave is ready to accept request
bit [3:0] arid; ////// unique ID for each transaction
rand bit [3:0] arlen; ////// burst length AXI3 : 1 to 16, AXI4 : 1 to 256
bit [2:0] arsize; ////unique transaction size : 1,2,4,8,16 ...128 bytes
rand bit [31:0] araddr; ////write adress of transaction
rand bit [1:0] arburst; ////burst type : fixed , INCR , WRAP

/////////// read data channel (r)

bit rvalid; //// master is sending new data

bit rready; //// slave is ready to accept new data
bit [3:0] rid; /// unique id for transaction
bit [31:0] rdata; //// data
bit [3:0] rstrb; //// lane having valid data
bit rlast; //// last transfer in write burst
bit [1:0] rresp; ///status of read transfer

//constraint size { awsize == 3'b010; arsize == 3'b010;}

constraint txid { awid == id; wid == id; bid == id; arid == id; rid == id; }
constraint burst {awburst inside {0,1,2}; arburst inside {0,1,2};}
constraint valid {awvalid != arvalid;}
constraint length {awlen == arlen;}

endclass : transaction

////////////////////////////////////////////////////////////////////////////////

class rst_dut extends uvm_sequence#(transaction);

Projects Page 125

class rst_dut extends uvm_sequence#(transaction);
`uvm_object_utils(rst_dut)

transaction tr;

function new(string name = "rst_dut");

super.new(name);
endfunction

virtual task body();

repeat(5)
begin
tr = transaction::type_id::create("tr");
$display("------------------------------");
`uvm_info("SEQ", "Sending RST Transaction to DRV", UVM_NONE);
start_item(tr);
assert(tr.randomize);
tr.op = rstdut;
finish_item(tr);
end
endtask

endclass

///////////////////////////////////////////////////////////////////////

class valid_wrrd_fixed extends uvm_sequence#(transaction);

`uvm_object_utils(valid_wrrd_fixed)

transaction tr;

function new(string name = "valid_wrrd_fixed");

super.new(name);
endfunction

virtual task body();

tr = transaction::type_id::create("tr");
$display("------------------------------");
`uvm_info("SEQ", "Sending Fixed mode Transaction to DRV", UVM_NONE);
start_item(tr);
assert(tr.randomize);
tr.op = wrrdfixed;
tr.awlen = 7;
tr.awburst = 0;
tr.awsize = 2;

finish_item(tr);
endtask

endclass
////////////////////////////////////////////////////////////

class valid_wrrd_incr extends uvm_sequence#(transaction);

`uvm_object_utils(valid_wrrd_incr)

Projects Page 126

 `uvm_object_utils(valid_wrrd_incr)

transaction tr;

function new(string name = "valid_wrrd_incr");

super.new(name);
endfunction

virtual task body();

tr = transaction::type_id::create("tr");
$display("------------------------------");
`uvm_info("SEQ", "Sending INCR mode Transaction to DRV", UVM_NONE);
start_item(tr);
assert(tr.randomize);
tr.op = wrrdincr;
tr.awlen = 7;
tr.awburst = 1;
tr.awsize = 2;

finish_item(tr);
endtask

endclass

///////////////////////////////////////////////////////////

class valid_wrrd_wrap extends uvm_sequence#(transaction);

`uvm_object_utils(valid_wrrd_wrap)

transaction tr;

function new(string name = "valid_wrrd_wrap");

super.new(name);
endfunction

virtual task body();

tr = transaction::type_id::create("tr");
$display("------------------------------");
`uvm_info("SEQ", "Sending WRAP mode Transaction to DRV", UVM_NONE);
start_item(tr);
assert(tr.randomize);
tr.op = wrrdwrap;
tr.awlen = 7;
tr.awburst = 2;
tr.awsize = 2;

finish_item(tr);
endtask

endclass

/////////////////////////////////////////////////////////////////////////////////

class err_wrrd_fix extends uvm_sequence#(transaction);

`uvm_object_utils(err_wrrd_fix)

transaction tr;

Projects Page 127

 function new(string name = "err_wrrd_fix");
super.new(name);
endfunction

virtual task body();

tr = transaction::type_id::create("tr");
$display("------------------------------");
`uvm_info("SEQ", "Sending Error Transaction to DRV", UVM_NONE);
start_item(tr);
assert(tr.randomize);
tr.op = wrrderrfix;
tr.awlen = 7;
tr.awburst = 0;
tr.awsize = 2;
finish_item(tr);
endtask

endclass

/////////////////////////////////////////////////////////////
class driver extends uvm_driver #(transaction);
`uvm_component_utils(driver)

virtual axi_if vif;

transaction tr;

function new(input string path = "drv", uvm_component parent = null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
tr = transaction::type_id::create("tr");

if(!uvm_config_db#(virtual axi_if)::get(this,"","vif",vif))
`uvm_error("drv","Unable to access Interface");
endfunction

task reset_dut();
begin
`uvm_info("DRV", "System Reset : Start of Simulation", UVM_MEDIUM);
vif.resetn <= 1'b0; ///active high reset
vif.awvalid <= 1'b0;
vif.awid <= 1'b0;
vif.awlen <= 0;
vif.awsize <= 0;
vif.awaddr <= 0;
vif.awburst <= 0;

Projects Page 128

 vif.wvalid <= 0;
vif.wid <= 0;
vif.wdata <= 0;
vif.wstrb <= 0;
vif.wlast <= 0;

vif.bready <= 0;

vif.arvalid <= 1'b0;

vif.arid <= 1'b0;
vif.arlen <= 0;
vif.arsize <= 0;
vif.araddr <= 0;
vif.arburst <= 0;

vif.rready <= 0;
@(posedge vif.clk);
end
endtask

/////////////////////////write read in fixed mode

task wrrd_fixed_wr();
`uvm_info("DRV", "Fixed Mode Write Transaction Started", UVM_NONE);
/////////////////////////write logic
vif.resetn <= 1'b1;
vif.awvalid <= 1'b1;
vif.awid <= tr.id;
vif.awlen <= 7;
vif.awsize <= 2;
vif.awaddr <= 5;
vif.awburst <= 0;

vif.wvalid <= 1'b1;

vif.wid <= tr.id;
vif.wdata <= $urandom_range(0,10);
vif.wstrb <= 4'b1111;
vif.wlast <= 0;

vif.arvalid <= 1'b0; ///turn off read

vif.rready <= 1'b0;
vif.bready <= 1'b0;
@(posedge vif.clk);

@(posedge vif.wready);
@(posedge vif.clk);

for(int i = 0; i < (vif.awlen); i++)//0 - 6 -> 7

begin
vif.wdata <= $urandom_range(0,10);
vif.wstrb <= 4'b1111;
@(posedge vif.wready);
@(posedge vif.clk);
end
vif.awvalid <= 1'b0;
vif.wvalid <= 1'b0;
vif.wlast <= 1'b1;
vif.bready <= 1'b1;
@(negedge vif.bvalid);

Projects Page 129

 @(negedge vif.bvalid);
vif.wlast <= 1'b0;
vif.bready <= 1'b0;
/////////////////////////////////////// read logic
endtask

///////////////////////////////////////////////////////// read transaction in fixed mode

task wrrd_fixed_rd();
`uvm_info("DRV", "Fixed Mode Read Transaction Started", UVM_NONE);
@(posedge vif.clk);

vif.arid <= tr.id;

vif.arlen <= 7;
vif.arsize <= 2;
vif.araddr <= 5;
vif.arburst <= 0;
vif.arvalid <= 1'b1;
vif.rready <= 1'b1;

for(int i = 0; i < (vif.arlen + 1); i++) begin // 0 1 2 3 4 5 6 7

@(posedge vif.arready);
@(posedge vif.clk);
end

@(negedge vif.rlast);
vif.arvalid <= 1'b0;
vif.rready <= 1'b0;

endtask

//////////////////////////////////////////////////////////////////////

task wrrd_incr_wr();
/////////////////////////write logic
`uvm_info("DRV", "INCR Mode Write Transaction Started", UVM_NONE);
vif.resetn <= 1'b1;
vif.awvalid <= 1'b1;
vif.awid <= tr.id;
vif.awlen <= 7;
vif.awsize <= 2;
vif.awaddr <= 5;
vif.awburst <= 1;

vif.wvalid <= 1'b1;

vif.wid <= tr.id;
vif.wdata <= $urandom_range(0,10);
vif.wstrb <= 4'b1111;
vif.wlast <= 0;

vif.arvalid <= 1'b0; ///turn off read

vif.rready <= 1'b0;
vif.bready <= 1'b0;

@(posedge vif.wready);
@(posedge vif.clk);

for(int i = 0; i < (vif.awlen); i++)

Projects Page 130

 for(int i = 0; i < (vif.awlen); i++)
begin
vif.wdata <= $urandom_range(0,10);
vif.wstrb <= 4'b1111;
@(posedge vif.wready);
@(posedge vif.clk);
end

vif.wlast <= 1'b1;

vif.bready <= 1'b1;
vif.awvalid <= 1'b0;
vif.wvalid <= 1'b0;
@(negedge vif.bvalid);
vif.bready <= 1'b0;
vif.wlast <= 1'b0;

endtask

/////////////////////////////////////// read logic

task wrrd_incr_rd();
`uvm_info("DRV", "INCR Mode Read Transaction Started", UVM_NONE);
@(posedge vif.clk);

vif.arid <= tr.id;

vif.arlen <= 7;
vif.arsize <= 2;
vif.araddr <= 5;
vif.arburst <= 1;
vif.arvalid <= 1'b1;
vif.rready <= 1'b1;

for(int i = 0; i < (vif.arlen + 1); i++) begin // 0 1 2 3 4 5 6 7

@(posedge vif.arready);
@(posedge vif.clk);
end

@(negedge vif.rlast);
vif.arvalid <= 1'b0;
vif.rready <= 1'b0;
endtask

//////////////////////////////////////////////////////////////////////////////

task wrrd_wrap_wr();
`uvm_info("DRV", "WRAP Mode Write Transaction Started", UVM_NONE);
/////////////////////////write logic
vif.resetn <= 1'b1;
vif.awvalid <= 1'b1;
vif.awid <= tr.id;
vif.awlen <= 7;
vif.awsize <= 2;
vif.awaddr <= 5;
vif.awburst <= 2;

vif.wvalid <= 1'b1;

vif.wid <= tr.id;
vif.wdata <= $urandom_range(0,10);
vif.wstrb <= 4'b1111;
vif.wlast <= 0;

Projects Page 131

 vif.wlast <= 0;

vif.arvalid <= 1'b0; ///turn off read

vif.rready <= 1'b0;
vif.bready <= 1'b0;

@(posedge vif.wready);
@(posedge vif.clk);

for(int i = 0; i < (vif.awlen); i++)

begin
vif.wdata <= $urandom_range(0,10);
vif.wstrb <= 4'b1111;
@(posedge vif.wready);
@(posedge vif.clk);
end

vif.wlast <= 1'b1;

vif.bready <= 1'b1;
vif.awvalid <= 1'b0;
vif.wvalid <= 1'b0;

@(negedge vif.bvalid);
vif.bready <= 1'b0;
vif.wlast <= 1'b0;

endtask

/////////////////////////////////////// read logic

task wrrd_wrap_rd();
`uvm_info("DRV", "WRAP Mode Read Transaction Started", UVM_NONE);
@(posedge vif.clk);
vif.arvalid <= 1'b1;
vif.rready <= 1'b1;

vif.arid <= tr.id;

vif.arlen <= 7;
vif.arsize <= 2;
vif.araddr <= 5;
vif.arburst <= 2;

for(int i = 0; i < (vif.arlen + 1); i++) begin // 0 1 2 3 4 5 6 7

@(posedge vif.arready);
@(posedge vif.clk);
end

@(negedge vif.rlast);
vif.arvalid <= 1'b0;
vif.rready <= 1'b0;
endtask

//////////////////////////////////////////////////////////////////////////

task err_wr();
`uvm_info("DRV", "Error Write Transaction Started", UVM_NONE);

/////////////////////////write logic

Projects Page 132

/////////////////////////write logic
vif.resetn <= 1'b1;
vif.awvalid <= 1'b1;
vif.awid <= tr.id;
vif.awlen <= 7;
vif.awsize <= 2;
vif.awaddr <= 128;
vif.awburst <= 0;

vif.wvalid <= 1'b1;

vif.wid <= tr.id;
vif.wdata <= $urandom_range(0,10);
vif.wstrb <= 4'b1111;
vif.wlast <= 0;

vif.arvalid <= 1'b0; ///turn off read

vif.rready <= 1'b0;
vif.bready <= 1'b0;

@(posedge vif.wready);
@(posedge vif.clk);

for(int i = 0; i < (vif.awlen); i++)

begin
vif.wdata <= $urandom_range(0,10);
vif.wstrb <= 4'b1111;
@(posedge vif.wready);
@(posedge vif.clk);
end

vif.wlast <= 1'b1;

vif.bready <= 1'b1;
vif.awvalid <= 1'b0;
vif.wvalid <= 1'b0;

@(negedge vif.bvalid);
vif.bready <= 1'b0;
vif.wlast <= 1'b0;
endtask

/////////////////////////////////////// read logic

task err_rd();
`uvm_info("DRV", "Error Read Transaction Started", UVM_NONE);
@(posedge vif.clk);
vif.arvalid <= 1'b1;
vif.rready <= 1'b1;
//vif.bready <= 1'b1;

vif.arid <= tr.id;

vif.arlen <= 7;
vif.arsize <= 2;
vif.araddr <= 128;
vif.arburst <= 0;

for(int i = 0; i < (vif.arlen + 1); i++) begin // 0 1 2 3 4 5 6 7

@(posedge vif.arready);
@(posedge vif.clk);
end

Projects Page 133

 @(negedge vif.rlast);
vif.arvalid <= 1'b0;
vif.rready <= 1'b0;

endtask
////////////////////////////////////////////////////////////////////////

virtual task run_phase(uvm_phase phase);

forever begin

seq_item_port.get_next_item(tr);
if(tr.op == rstdut)
reset_dut();
else if (tr.op == wrrdfixed)
begin
`uvm_info("DRV", $sformatf("Fixed Mode Write -> Read WLEN:%0d WSIZE:%0d",tr.awlen+1,tr.awsize),
UVM_MEDIUM);
wrrd_fixed_wr();
wrrd_fixed_rd();
end
else if (tr.op == wrrdincr)
begin
`uvm_info("DRV", $sformatf("INCR Mode Write -> Read WLEN:%0d WSIZE:%0d",tr.awlen+1,tr.awsize),
UVM_MEDIUM);
wrrd_incr_wr();
wrrd_incr_rd();
end
else if (tr.op == wrrdwrap)
begin
`uvm_info("DRV", $sformatf("WRAP Mode Write -> Read WLEN:%0d WSIZE:%0d",tr.awlen+1,tr.awsize),
UVM_MEDIUM);
wrrd_wrap_wr();
wrrd_wrap_rd();
end
else if (tr.op == wrrderrfix)
begin
`uvm_info("DRV", $sformatf("Error Transaction Mode WLEN:%0d WSIZE:%0d",tr.awlen+1,tr.awsize), UVM_MEDIUM);
err_wr();
err_rd();
end

seq_item_port.item_done();
end
endtask

endclass
///////////////////////////////////////////////////////////////////////

class mon extends uvm_monitor;

`uvm_component_utils(mon)

transaction tr;
virtual axi_if vif;

logic [31:0] arr[128];

logic [1:0] rdresp;

Projects Page 134

logic [1:0] rdresp;
logic [1:0] wrresp;

logic resp;

int err = 0;

function new(input string inst = "mon", uvm_component parent = null);

super.new(inst,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
tr = transaction::type_id::create("tr");
if(!uvm_config_db#(virtual axi_if)::get(this,"","vif",vif))//uvm_test_top.env.agent.drv.aif
`uvm_error("MON","Unable to access Interface");
endfunction

/////////////////////////////////////////////////////////////////////////

task compare();
if(err == 0 && rdresp == 0 && wrresp == 0 )
begin
`uvm_info("MON", $sformatf("Test Passed err :%0d wrresp :%0d rdresp :%0d ", err, rdresp, wrresp), UVM_MEDIUM);
err = 0;
end
else
begin
`uvm_info("MON", $sformatf("Test Failed err :%0d wrresp :%0d rdresp :%0d ", err, rdresp, wrresp), UVM_MEDIUM);
err = 0;
end
endtask

///////////////////////////////////////////////////////////////////////
virtual task run_phase(uvm_phase phase);
forever begin

@(posedge vif.clk);
if(!vif.resetn)
begin
`uvm_info("MON", "System Reset Detected", UVM_MEDIUM);
end

else if(vif.resetn && vif.awaddr < 128)

begin

wait(vif.awvalid == 1'b1);

for(int i =0; i < (vif.awlen + 1); i++) begin

@(posedge vif.wready);
arr[vif.next_addrwr] = vif.wdata;
end

// @(negedge vif.wlast);
@(posedge vif.bvalid);
wrresp = vif.bresp;///0
//////////////////////////////////////////////////////
wait(vif.arvalid == 1'b1);

for(int i =0; i < (vif.arlen + 1); i++) begin

Projects Page 135

 for(int i =0; i < (vif.arlen + 1); i++) begin
@(posedge vif.rvalid);
if(vif.rdata != arr[vif.next_addrrd])
begin
err++;
end
end

@(posedge vif.rlast);
rdresp = vif.rresp;

compare();
$display("------------------------------");
end

else if (vif.resetn && vif.awaddr >= 128)

begin
wait(vif.awvalid == 1'b1);

for(int i =0; i < (vif.awlen + 1); i++) begin

@(negedge vif.wready);
end

@(posedge vif.bvalid);
wrresp = vif.bresp;

wait(vif.arvalid == 1'b1);

for(int i =0; i < (vif.arlen + 1); i++) begin

@(posedge vif.arready);
if(vif.rresp != 2'b00)
begin
err++;
end
end

@(posedge vif.rlast);
rdresp = vif.rresp;

compare();
$display("------------------------------");
end

end
endtask

endclass

///////////////////////////////////////////////////////////
class agent extends uvm_agent;
`uvm_component_utils(agent)

Projects Page 136

function new(input string inst = "agent", uvm_component parent = null);
super.new(inst,parent);
endfunction

driver d;
uvm_sequencer#(transaction) seqr;
mon m;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
m = mon::type_id::create("m",this);
d = driver::type_id::create("d",this);
seqr = uvm_sequencer#(transaction)::type_id::create("seqr", this);

endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
d.seq_item_port.connect(seqr.seq_item_export);
endfunction

endclass

////////////////////////////////////////////////////////////////////////////////

class env extends uvm_env;

`uvm_component_utils(env)

function new(input string inst = "env", uvm_component c);

super.new(inst,c);
endfunction

agent a;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a = agent::type_id::create("a",this);

endfunction

endclass

//////////////////////////////////////////////////
class test extends uvm_test;
`uvm_component_utils(test)

function new(input string inst = "test", uvm_component c);

super.new(inst,c);
endfunction

env e;
valid_wrrd_fixed vwrrdfx;
valid_wrrd_incr vwrrdincr;
valid_wrrd_wrap vwrrdwrap;
err_wrrd_fix errwrrdfix;

Projects Page 137

err_wrrd_fix errwrrdfix;
rst_dut rdut;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e = env::type_id::create("env",this);
vwrrdfx = valid_wrrd_fixed::type_id::create("vwrrdfx");
vwrrdincr = valid_wrrd_incr::type_id::create("vwrrdincr");
vwrrdwrap = valid_wrrd_wrap::type_id::create("vwrrdwrap");
errwrrdfix = err_wrrd_fix::type_id::create("errwrrdfix");
rdut = rst_dut::type_id::create("rdut");
endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);
//rdut.start(e.a.seqr);
//#20;
//vwrrdfx.start(e.a.seqr);
//#20;
//vwrrdincr.start(e.a.seqr);
//#20;
//vwrrdwrap.start(e.a.seqr);
//#20;
errwrrdfix.start(e.a.seqr);
#20;

phase.drop_objection(this);
endtask
endclass

/////////////////////////////////////////////////////////////////////

module tb;

axi_if vif();
axi_slave dut (vif.clk, vif.resetn, vif.awvalid, vif.awready, vif.awid, vif.awlen, vif.awsize, vif.awaddr, vif.awburst, vif.wvalid,
vif.wready, vif.wid, vif.wdata, vif.wstrb, vif.wlast, vif.bready, vif.bvalid, vif.bid, vif.bresp , vif.arready, vif.arid, vif.araddr,
vif.arlen, vif.arsize, vif.arburst, vif.arvalid, vif.rid, vif.rdata, vif.rresp,vif.rlast, vif.rvalid, vif.rready);

initial begin
vif.clk <= 0;
end

always #5 vif.clk <= ~vif.clk;

initial begin
uvm_config_db#(virtual axi_if)::set(null, "*", "vif", vif);
run_test("test");
end

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end

assign vif.next_addrwr = dut.nextaddr;

assign vif.next_addrrd = dut.rdnextaddr;

endmodule

Projects Page 138

endmodule

Projects Page 139

0] Links of Project
10 July 2023 10:22

1] Adder verification in UVM

https://verificationguide.com/systemverilog-examples/systemverilog-testbench-example-with-scb/

https://www.edaplayground.com/x/bZG

Projects Page 140

1]
01 June 2023 09:53

D Flip Flip Verification Page 141

Video 1 : Introduction
20 June 2023 08:18

1]

MV Video Screenshot Page 142

MV Video Screenshot Page 143
MV Video Screenshot Page 144
Video 2 : introduction and factory
20 June 2023 09:24

1]

Video 2 Part1 :
UVM Environment

UVM Agent

MV Video Screenshot Page 145

1] UVM Component Have Hierarchy need to follow
2] UVM Object don't have any hierarchy . Because it is data which we give simulation

UVM Hierarchy

Video 2 Part2 :
MV Video Screenshot Page 146
Object is used for stimulus generation purpose

Factory generate the unique type_id for each class.

1] Factory Registration

MV Video Screenshot Page 147

2] Registering Component

3] Registering object

MV Video Screenshot Page 148

Samja driver la aapan regsister karat aahot factory madhe tenva tycha parent ha agent aasto.Hierarchy madhe
pahave lagte.

4] Default Constructor

MV Video Screenshot Page 149

MV Video Screenshot Page 150
Function new (string name ="driver", uvm_component parent = null )

Null ha constructor madhe asel tar.

UVM_TOP Ha UVM_ROOT cha pointer aahe manje. UVM_TOP ha UVM_ROOT la point out karto.

MV Video Screenshot Page 151

Class test madhe jenva aapna constrctor define karto tenva aapan null karto.
Nanter konte pan class define nahi karat.

function new(string path="test",uvm_component parent =null);

Super.new(path,parent);
endfunction

Jenva aapan run_test() call karto tenva to test class ha null la point karto manje
UVM_TOP la jaate
uvm_top chya khali UVM_TEST_TOP create hoto. Nanter env create karat karat to khali jaato.

MV Video Screenshot Page 152

Null manje TOP madhe object create hoto.

MV Video Screenshot Page 153

MV Video Screenshot Page 154
Video 3:
20 June 2023 13:11

1] Why we use the create method

Create method ha type_id chya class madhe jaato and tithe jo construct aahe tyla call karto.
Jar aapan new method cha use kela tar te fkt class handle chya construct madhe jaato. Overridding saathi factory cha
use kela jaato.

2] Factory override method madhe type id nusar hote. Factroy override kartana nehami tychya hierchay madhe je
kahi component aahe tycha varti class madhe define karave overide method.

3]
Factory Overideing

MV Video Screenshot Page 155

MV Video Screenshot Page 156
1] Sequence
16 July 2023 23:36

Virtual sequence

https://verificationacademy.com/cookbook/sequences/virtual

Sequence Page 157

21 October 2023 00:44

Interview Question Page 158

1] Introduction
01 June 2023 10:25

Q .Why is factory registration required?

In UVM based testbench, it is valid to use a new() function to create class objects, but factory registration has its benefits. The
UVM factory allows an object of one type to be overridden with an object of its derived type without changing the testbench
structure. This is known as the UVM factory override mechanism. This is applicable for uvm objects and components.

The UVM factory is used to create UVM objects and components. This is commonly known as factory registration. The factory
registration for UVM objects and components are lightweight proxies to the actual objects and components.

1] UVM Factory =Modified 1 june Page 159

1] Factory registration
All uvm_component and uvm_object must be registered with the factory using a pre-defined factory registration macro.

A] Factory registration for uvm_object

class reg_seq extends uvm_sequence #(seq_item);

// factory registration for sequence
`uvm_object_utils(reg_seq)
...
...
endclass

// For parameterized class

class param_obj #(int WIDTH = 16, ID = 0) extends uvm_object;
typedef param_obj #(int WIDTH, ID) obj_p;
`uvm_object_param_utils(obj_p)
...
...
endclass

1] UVM Factory =Modified 1 june Page 160

2] Factory registration for uvm_component

class reg_driver extends uvm_driver;

// factory registration for driver component
`uvm_component_utils(reg_driver)
...
...
endclass

// For parameterized class

class param_env #(int WIDTH = 32, ID = 0) extends uvm_env;
typedef param_env #(int WIDTH, ID) env_p;
`uvm_component_param_utils(env_p)
...
...
endclass

2] Default constructor new()

The uvm_component and uvm_object constructors are virtual methods i.e. they have fixed prototype template defined that has
to be followed.

1] Constructor for uvm_object

The default constructor has a single argument as the name denotes an instance name for an object.

class reg_seq extends uvm_sequence #(seq_item);

`uvm_object_utils(reg_seq)

// default constructor for sequence

function new(string name = "reg_seq")
super.new(name);
endclass
...
...
endclass

2] Constructor for uvm_component

1] The default constructor has two arguments: name and parentThe name denotes an instance name for an object.
The parent denotes the handle to its parent. In the constructor, the parent argument is null and the actual parent can be
provided while creating an object.
2] The parent is null if it is a top-level component and all other derived components provide the actual parent.
All derived classes must call super.new() methods.

1] UVM Factory =Modified 1 june Page 161

All derived classes must call super.new() methods.
Default arguments provide an initial assignment. Later, it is reassigned with other values on calling the create() method of
the uvm_component_registry wrapper class.

class env extends uvm_env;

`uvm_component_utils(reg_driver)

// default constructor for sequence

function new(string name = "env", uvm_component parent = null)
super.new(name, parent);
endclass
...
...
endclass

3] Component and object creation

The create() method of the wrapper class is used to create objects for the uvm_object and uvm_component class.
The build_phase is used to create component instances and build component hierarchy.
Since uvm_object is created in the run time, uvm objects are created in the run_phase.
Syntax for Component creation:

<instance_name> = <type>::<type_id>::create("<name>", <parent>)

Syntax for Object creation:

<instance_name> = <type>::<type_id>::create("<name>")

Example :
class env extends uvm_env;
`uvm_component_utils(env)
mycomponent compA;
param_component #(.WIDTH(8), .ID(1)) compB;

// default constructor for sequence

function new(string name = "env", uvm_component parent = null)
super.new(name, parent);
endclass

function void build_phase(uvm_phase phase);

super.build_phase(phase);
// component creation
compA = mycomponent::type_id::create("compA", this);
compB = param_component #(8, 1)::type_id::create("compB", this);
endfunction

task run_phase(uvm_phase phase);

mysequence seqA;
param_sequence #(.WIDTH(8), .ID(1)) seqB;

// object creation
seqA = mysequence::type_id::create("seqA");
seqB = param_sequence #(8,1)::type_id::create("seqB");
...
...
endtask
endclass

1] UVM Factory =Modified 1 june Page 162

endclass

1] UVM Factory =Modified 1 june Page 163

2] Factory Overriding (polymorphism)
01 June 2023 10:59

https://www.linkedin.com/pulse/uvm-factory-overrides-sanjana-pisal/

Based on the requirement, the behavior of the testbench can be changed by substituting one class with another when it
is constructed. This facility of the uvm factory allows users to override the class without editing or recompiling the code.

How factory overriding happens?

A factory can be thought of as a look-up table and a factory component wrapper class can be accessed using type_id
which is used in create method and returns a resultant handle.

2] Using the polymorphism concept, the factory override mechanism returns a derived type handle using a base type
handle. This means when the create method is being called for the base class type, uvm_factory will return a pointer to
an object of a derived class type.

Factory overriding ways

1] Type Override
2] Instance Override

Note: The factory override ways are applicable for both uvm components and
uvm objects.

Type override in UVM factory

In a type override, a substitute component class type is created instead of an original component class in the testbench
hierarchy. This applies to all instances of that component type.

1] UVM Factory =Modified 1 june Page 164

1] set_type_override_by_type (entire Testbench)

Syntax :

set_type_override_by_type (orginal_type ::get_type,

Substitute_type::get_type)

Code 1 :

1] UVM Factory =Modified 1 june Page 165

`include "uvm_macros.svh";
import uvm_pkg::*;

`define RAM_WIDTH 8
`define ADDR_SIZE 4

class parent extends uvm_sequence_item;

rand bit [`RAM_WIDTH -1 :0] din;
rand bit [`ADDR_SIZE -1:0] addr;
rand bit er_enb;

`uvm_object_utils_begin(parent)
`uvm_field_int(din,UVM_ALL_ON +UVM_DEC)
`uvm_field_int(addr,UVM_ALL_ON +UVM_DEC)
`uvm_field_int(er_enb,UVM_ALL_ON +UVM_DEC)
`uvm_object_utils_end

function new(input string name ="parent");

super.new(name);
endfunction
constraint cons { din inside {[10:40]};
soft addr==5;

}
endclass

class child extends parent;

`uvm_object_utils(child)
constraint cons2 { addr==10;}
function new(input string name ="child");
super.new(name);
endfunction
endclass

module tb();
parent p;
function void build();

p=parent::type_id::create("p");
p.randomize();
p.print();
endfunction
uvm_factory factory=uvm_factory::get(); // from uvm 1.2 version we need to use it

initial
begin

// repeat(5)
build();

factory.set_type_override_by_type (parent::get_type(),child::get_type());

//repeat(5)
build();
end
endmodule

Output:

-------------------------------
Name Type Size Value
-------------------------------
p parent - @336
din integral 8 'd16
addr integral 4 'd5
er_enb integral 1 1
-------------------------------
-------------------------------
Name Type Size Value
-------------------------------
p child - @340
din integral 8 'd12
addr integral 4 10

1] UVM Factory =Modified 1 june Page 166

addr integral 4 10
er_enb integral 1 1
-------------------------------
VCSSimulationReport
Time: 0 ns
CPU Time: 0.860 seconds; Data structure size: 0.1Mb
Thu Nov 30 07:24:52 2023

Some changes:

Code:
`include "uvm_macros.svh";
import uvm_pkg::*;
`define RAM_WIDTH 8
`define ADDR_SIZE 4

class parent extends uvm_sequence_item;

rand bit [`RAM_WIDTH -1 :0] din;
rand bit [`ADDR_SIZE -1:0] addr;
rand bit er_enb;
`uvm_object_utils_begin(parent)
`uvm_field_int(din,UVM_ALL_ON +UVM_DEC)
`uvm_field_int(addr,UVM_ALL_ON +UVM_DEC)
`uvm_field_int(er_enb,UVM_ALL_ON +UVM_DEC)
`uvm_object_utils_end

function new(input string name ="parent");

super.new(name);
endfunction
constraint cons { din inside {[10:40]};
soft addr==5;
}
endclass

class child extends parent;

`uvm_object_utils(child)
constraint cons2 { addr==10;}
function new(input string name ="child");
super.new(name);
endfunction
endclass

module tb();
child p;
function void build();
p=child::type_id::create("p");
p.randomize();
p.print();
endfunction
uvm_factory factory=uvm_factory::get(); // from uvm 1.2 version we need to use it
initial
begin
build();
factory.set_type_override_by_type (child::get_type(),parent::get_type());
build();
end
endmodule

1] UVM Factory =Modified 1 june Page 167

Output:
-------------------------------
Name Type Size Value
-------------------------------
p child - @336
din integral 8 'd16
addr integral 4 10
er_enb integral 1 1
-------------------------------
UVM_FATAL @ 0: reporter [FCTTYP] Factory did not return an object of type 'child'. A component of type 'parent' was
returned instead. Name=p Parent=null contxt=
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 1
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 1
** Report counts by id
[FCTTYP] 1
[UVM/RELNOTES] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 135.

$finish at simulation time 0
VCSSimulationReport
Time: 0 ns
CPU Time: 0.700 seconds; Data structure size: 0.1Mb
Thu Nov 30 07:32:49 2023

Code 2 :

`include "uvm_macros.svh"
import uvm_pkg::*;

class component_A extends uvm_component;

`uvm_component_utils(component_A)

function new(string name = "component_A", uvm_component parent = null);

super.new(name, parent);
endfunction

virtual function display();

`uvm_info(get_type_name(), $sformatf("inside component_A"), UVM_LOW);
endfunction
endclass

class component_B extends component_A;

`uvm_component_utils(component_B)

function new(string name = "component_B", uvm_component parent = null);

super.new(name, parent);
endfunction

function display();
`uvm_info(get_type_name(), "inside component_B", UVM_LOW);
endfunction
endclass

class my_test extends uvm_test;

`uvm_component_utils(my_test)
component_A comp_A;

function new(string name = "my_test", uvm_component parent = null);

super.new(name, parent);
endfunction

function void build_phase(uvm_phase phase);

uvm_factory factory = uvm_factory::get();
super.build_phase(phase);

1] UVM Factory =Modified 1 june Page 168

 super.build_phase(phase);

set_type_override_by_type(component_A::get_type(), component_B::get_type());
comp_A = component_A::type_id::create("comp_A", this);
factory.print();
endfunction

function void end_of_elaboration_phase(uvm_phase phase);

super.end_of_elaboration_phase(phase);
uvm_top.print_topology();
endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);
comp_A.display();
endtask
endclass

module tb_top;
initial begin
run_test("my_test");
end
endmodule

Output:
UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# --------------------------------------
# Name Type Size Value
# --------------------------------------
# uvm_test_top my_test - @466
# comp_A component_B - @473
# --------------------------------------
#
# UVM_INFO first.sv(24) @ 0: uvm_test_top.comp_A [component_B] inside component_B
#
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 5
# UVM_WARNING : 0
# UVM_ERROR : 0
# UVM_FATAL : 0
# ** Report counts by id
# [Questa UVM] 2
# [RNTST] 1
# [UVMTOP] 1
# [component_B] 1
# ** Note: $finish : C:/questasim64_10.7c/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430)
# Time: 0 ns Iteration: 215 Instance: /tb_top
#1
# Break in Task uvm_pkg/uvm_root::run_test at C:/questasim64_
10.7c/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh line 430
# quit -sim
# End time: 12:54:44 on Jun 01,2023, Elapsed time: 0:00:52

Without set_overide output is

# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:

# --------------------------------------
# Name Type Size Value
# --------------------------------------
# uvm_test_top my_test - @466
# comp_A component_A - @473
# --------------------------------------
#
# UVM_INFO first.sv(12) @ 0: uvm_test_top.comp_A [component_A] inside component_A
#

1] UVM Factory =Modified 1 june Page 169

#
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 5
# UVM_WARNING : 0
# UVM_ERROR : 0
# UVM_FATAL : 0
# ** Report counts by id
# [Questa UVM] 2
# [RNTST] 1
# [UVMTOP] 1
# [component_A] 1
# ** Note: $finish : C:/questasim64_10.7c/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430)
# Time: 0 ns Iteration: 215 Instance: /tb_top
#1
# Break in Task uvm_pkg/uvm_root::run_test at C:/questasim64_
10.7c/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh line 430
# quit -sim
# End time: 13:03:01 on Jun 01,2023, Elapsed time: 0:00:54
# Errors: 0, Warnings: 3

2] set_inst_override_by_type (Particular instance)

Syntax :

set_inst_override_by_type ("instance _Path",orginal_type ::get_type,

Substitute_type::get_type)

Ha fkt specific path la overirde karto

Code :

`include "uvm_macros.svh"

1] UVM Factory =Modified 1 june Page 170

`include "uvm_macros.svh"
import uvm_pkg::*;

class component_A extends uvm_component;

`uvm_component_utils(component_A)

function new(string name = "component_A", uvm_component parent = null);

super.new(name, parent);
endfunction

virtual function display();

`uvm_info(get_type_name(), $sformatf("inside component_A"), UVM_LOW);
endfunction
endclass

class component_B extends component_A;

`uvm_component_utils(component_B)

function new(string name = "component_B", uvm_component parent = null);

super.new(name, parent);
endfunction

function display();
`uvm_info(get_type_name(), "inside component_B", UVM_LOW);
endfunction
endclass

class my_test extends uvm_test;

`uvm_component_utils(my_test)
component_A comp_A;

function new(string name = "my_test", uvm_component parent = null);

super.new(name, parent);
endfunction

function void build_phase(uvm_phase phase);

uvm_factory factory = uvm_factory::get();
super.build_phase(phase);

set_inst_override_by_type("comp_A",component_A::get_type(), component_B::get_type());
comp_A = component_A::type_id::create("comp_A", this);
factory.print();
endfunction

function void end_of_elaboration_phase(uvm_phase phase);

super.end_of_elaboration_phase(phase);
uvm_top.print_topology();
endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);
comp_A.display();
endtask
endclass

module tb_top;
initial begin
run_test("my_test");
end
endmodule

Output:
####
#
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# --------------------------------------
# Name Type Size Value
# --------------------------------------
# uvm_test_top my_test - @466
# comp_A component_B - @473
# --------------------------------------
#
# UVM_INFO first.sv(24) @ 0: uvm_test_top.comp_A [component_B] inside component_B
#
# --- UVM Report Summary ---

1] UVM Factory =Modified 1 june Page 171

# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 5
# UVM_WARNING : 0
# UVM_ERROR : 0
# UVM_FATAL : 0
# ** Report counts by id
# [Questa UVM] 2
# [RNTST] 1
# [UVMTOP] 1
# [component_B] 1
# ** Note: $finish : C:/questasim64_10.7c/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430)
# Time: 0 ns Iteration: 215 Instance: /tb_top
#1
# Break in Task uvm_pkg/uvm_root::run_test at C:/questasim64_
10.7c/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh line 430
# quit -sim
# End time: 13:07:11 on Jun 01,2023, Elapsed time: 0:00:57
# Errors: 0, Warnings: 3

Munsif Example

1] UVM Factory =Modified 1 june Page 172

1] UVM Factory =Modified 1 june Page 173
Code :

`include "uvm_macros.svh";
import uvm_pkg::*;

`define RAM_WIDTH 8
`define ADDR_SIZE 4

class parent extends uvm_sequence_item;

rand bit [`RAM_WIDTH -1 :0] din;
rand bit [`ADDR_SIZE -1:0] addr;
rand bit er_enb;

`uvm_object_utils_begin(parent)
`uvm_field_int(din,UVM_ALL_ON +UVM_DEC)
`uvm_field_int(addr,UVM_ALL_ON +UVM_DEC)
`uvm_field_int(er_enb,UVM_ALL_ON +UVM_DEC)
`uvm_object_utils_end

1] UVM Factory =Modified 1 june Page 174

 function new(input string name ="parent");
super.new(name);
endfunction
constraint cons { din inside {[10:40]};
addr inside {[0:10]};

}
endclass

class child extends parent;

`uvm_object_utils(child)
constraint cons2 { addr==10;}
function new(input string name ="child");
super.new(name);
endfunction
endclass

module tb();
parent p;
function void build();
p=parent::type_id::create("p");
p.randomize();
p.print();
endfunction

initial
begin

repeat(2)
build();

factory.set_type_override_by_type (parent::get_type(),child::get_type());

repeat(2)
build();
end
endmodule

Output:

UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM]

QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(216) @ 0: reporter [Questa UVM]
questa_uvm::init(+struct)
# -------------------------------
# Name Type Size Value
# -------------------------------
#p parent - @466
# din integral 8 'd25
# addr integral 4 'd0
# er_enb integral 1 1
# -------------------------------
# -------------------------------
# Name Type Size Value
# -------------------------------
#p parent - @470
# din integral 8 'd34
# addr integral 4 'd6
# er_enb integral 1 1
# -------------------------------
# -------------------------------
# Name Type Size Value
# -------------------------------
#p child - @474
# din integral 8 'd32
# addr integral 4 10
# er_enb integral 1 'd0
# -------------------------------
# -------------------------------
# Name Type Size Value
# -------------------------------

1] UVM Factory =Modified 1 june Page 175

# -------------------------------
#p child - @478
# din integral 8 'd16
# addr integral 4 10
# er_enb integral 1 1
# -------------------------------
# quit -sim
# End time: 19:10:48 on Jul 06,2023, Elapsed time: 0:00:23
# Errors: 0, Warnings: 1

1] UVM Factory =Modified 1 june Page 176

Reporting mechanism == LOW updated
29 December 2022 12:24

1] uvm reporting mechanism

1.1] The code for understanding the uvm info, warning,error,fatal
Messaging and UVM Reporting has the concepts of Severity, Verbosity and Simulation Handing Behavior. Each of them
can be independently specified and controlled. Now lets see what each of these indicates:

• Severity
○ Severity indicates importance
○ Examples are Fatal, Error, Warning & Info
• Verbosity
○ Verbosity indicates filter level
○ Examples are None, Low, Medium, High, Full & Debug
• Simulation Handling Behavior
○ Simulation handling behavior controls simulator behavior
○ Examples are Exit, Count, Display, Log, Call Hook & No Action

UVM Reporting provides Macros to embed report messages. Followings are the UVM Macros to be used:

`uvm_info(string ID, string MSG, verbosity); -----------> Default verbosity is UVM_MEDIUM

`uvm_error(string ID, string MSG); -------------> Default verbosity is UVM_NONE
`uvm_warning(string ID, string MSG); -------------> Default verbosity is UVM_NONE
`uvm_fatal(string ID, string MSG); -------------> Default verbosity is UVM_NONE

From the syntax of the above mentioned Macros it is very well evident how we can embed the message of our choice with
a particular macro. The provided message ID helps in easy search, e.g. grep, in the simulation log. In addition, total
count of a particular severity can also be seen using message ID at the end of the simulation log.

Keypoints:
1) Verilog $display does not provide a Filtering facility whereas UVM provides the Message filtering capabilities to notify
only important messages to the User.

2) Verbosity level is used for filtering the message so the `uvm_info messages which possess verbosity level less than or
equal to the current configure verbosity level will be sent to the Console.

3) UVM reporting Services are built-in for all the components hence can be utilized in any UVM component. They are
derived from UVM_REPORT_OBJECT class.

4) string id is used for filtering. The UVM reporting macros API's (`uvm_info, `uvm_warning, etc.) are recommended over
default Messaging API's (`uvm_report_info) because macro API first perform verbosity level check before working on the
String messages.

5) `uvm_warning, `uvm_error, and `uvm_fatal have default Verbosity hence will always be displayed on the console to
notify bugs inside the design. The verbosity level of warning,error,fatal is UVM_NONE.

6) Default Verbosity level of `uvm_info is UVM_MEDIUM. But most of the time we use the UVM_NONE verbosity to print
all message.

7) Default Verbosity level (UVM_MEDIUM) can be overridden by using set_report_verbosity_level or

set_report_severity_id_action for specific component.

1] Repoerting mechanism LOW Page 177

set_report_severity_id_action for specific component.

Code1 :
import uvm_pkg::*;
`include "uvm_macros.svh"

module tb;

initial
begin
`uvm_info("MOD","the info statement 1",UVM_NONE);
`uvm_warning("MOD","the warning statement");
`uvm_error("MOD","the error statement");
`uvm_fatal("MOD","the fatal error statement");
`uvm_info("MOD","the info statement 2",UVM_NONE);

end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO testbench.sv(8) @ 0: reporter [MOD] the info statement 1

UVM_WARNING testbench.sv(9) @ 0: reporter [MOD] the warning statement
UVM_ERROR testbench.sv(10) @ 0: reporter [MOD] the error statement
UVM_FATAL testbench.sv(11) @ 0: reporter [MOD] the fatal error statement
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 2
UVM_WARNING : 1
UVM_ERROR : 1
UVM_FATAL : 1
** Report counts by id
[MOD] 4
[UVM/RELNOTES] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 135.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.780 seconds; Data structure size: 0.1Mb
Thu Dec 29 02:34:36 2022
Done

Evdha jo part aahe to fkt UVM_fatal mule execute hoto.

1] Repoerting mechanism LOW Page 178

Evdha jo part aahe to fkt UVM_fatal mule execute hoto.

Without uvm_fatal:

Important Facts and Terminology

A class library consists of a collection of classes to allow the implementation of the entire testbench
environment.uvm_pkg is the library file consisting of all the UVM files required to perform Formal Verification in the
Single System Verilog Package file. Users need to compile the package file outside the module.
Vivado comes with the precompiled UVM version 1.2 library hence we need not include or compile
`include "uvm_pkg.svh"

1] Repoerting mechanism LOW Page 179

`include "uvm_pkg.svh"
Once the package is compiled user can access the package by including
import uvm_pkg::*;
UVM macros are the compiler directive hence need to be added with every code.
`include "uvm_macros.svh"

1.2] Verbosity Level in UVM

1] Repoerting mechanism LOW Page 180

1] Code to check set the verbosity of class using component

Code :
`include "uvm_macros.svh";
import uvm_pkg::*;

class verbosity extends uvm_component;

`uvm_component_utils(verbosity);

function new(string path="verbosity",uvm_component parent=null);

super.new(path,parent);
endfunction

task runp();
`uvm_info("verobosity1",$sformatf("class member execution 1"),UVM_LOW);
`uvm_info("verobosity2",$sformatf("class member execution 2"),UVM_HIGH);
endtask

endclass

module tb();
verbosity v;

initial
begin
v=new("DIS",null);
v.set_report_verbosity_level(UVM_FULL);
v.runp();
end
endmodule

Output:

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO testbench.sv(12) @ 0: DIS [verobosity1] class member execution 1

1] Repoerting mechanism LOW Page 181

UVM_INFO testbench.sv(12) @ 0: DIS [verobosity1] class member execution 1
UVM_INFO testbench.sv(13) @ 0: DIS [verobosity2] class member execution 2
VCS Simulation Report
Time: 0 ns
CPU Time: 0.440 seconds; Data structure size: 0.1Mb
Thu Dec 29 11:38:44 2022

Note:
Ethe
UVM_INFO testbench.sv(12) @ 0: DIS [verobosity1] class member execution 1
ha aapan jenva object create karto tenva takle jaate.

Some Changes:
module tb();
verbosity v;

initial
begin
v=new("DIS",null);
v.set_report_verbosity_level(UVM_MEDIUM);
v.runp();
end
endmodule

Output :
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO testbench.sv(12) @ 0: DIS [verobosity1] class member execution 1

VCS Simulation Report
Time: 0 ns
CPU Time: 0.500 seconds; Data structure size: 0.1Mb
Thu Dec 29 11:45:05 2022

Ethe aata `uvm_info("verobosity2",$sformatf("class member execution 2"),UVM_HIGH); he line print nahi zali aahe
karan aapan aata verbosity level ha UVM_MEDIUM kele aahe .

2] code for get the verbosity level of class using component

Code :
`include "uvm_macros.svh";
import uvm_pkg::*;

class verbosity extends uvm_component;

`uvm_component_utils(verbosity);

function new(string path="verbosity",uvm_component parent=null);

1] Repoerting mechanism LOW Page 182

 function new(string path="verbosity",uvm_component parent=null);
super.new(path,parent);
endfunction

task runp();
`uvm_info("verobosity1",$sformatf("class member execution 1"),UVM_LOW);
`uvm_info("verobosity2",$sformatf("class member execution 2"),UVM_HIGH);
endtask

endclass

module tb();
verbosity v;
int a;

initial
begin
v=new("DIS");
v.set_report_verbosity_level(UVM_MEDIUM);
v.runp();
a=v.get_report_verbosity_level();
`uvm_info("MOD",$sformatf("value of verbosity =%0d",a),UVM_NONE);
end
endmodule

Output :

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO testbench.sv(12) @ 0: DIS [verobosity1] class member execution 1

UVM_INFO testbench.sv(28) @ 0: reporter [MOD] value of verbosity =200
VCS Simulation Report
Time: 0 ns
CPU Time: 0.440 seconds; Data structure size: 0.1Mb
Thu Dec 29 12:00:00 2022

Note:
ethe class che verbosity milte. Tymule aapan get method cha use kela aahe.

3] Get and set verbosity using object

Code :

class dis extends uvm_report_object;

rand bit [15:0] din;

`uvm_object_utils_begin(dis)
`uvm_field_int(din, UVM_DEFAULT);
`uvm_object_utils_end

function new(string name = "DIS");

super.new(name);

1] Repoerting mechanism LOW Page 183

 super.new(name);
endfunction

task run();
`uvm_info("DIS", $sformatf("Value of DIN : %0d",din),UVM_NONE);
endtask

endclass

module tb;
dis d1;
integer level;

initial begin
d1 = new("DIS");
level = d1.get_report_verbosity_level;
`uvm_info("INFO",$sformatf("Ver Level : %0d",level),UVM_NONE);
d1.randomize;
d1.run;
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO testbench.sv(26) @ 0: reporter [INFO] Ver Level : 200

UVM_INFO testbench.sv(13) @ 0: DIS [DIS] Value of DIN : 55225
VCS Simulation Report
Time: 0 ns
CPU Time: 0.500 seconds; Data structure size: 0.1Mb
Thu Dec 29 12:36:28 2022
Done

4] Understand the uvm_info in testbench

Testbench top define karatana input and output chi garaj nahi aahe.

Code :
`include "uvm_macros.svh";
import uvm_pkg::*;

module tb();
int a;

initial
begin
#45;
`uvm_info("TB","hello word in uvm_info statement",UVM_NONE);
$display("hello word in display statement");

1] Repoerting mechanism LOW Page 184

 $display("hello word in display statement");
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO testbench.sv(10) @ 45: reporter [TB] hello word in uvm_info statement

hello word in display statement
VCS Simulation Report
Time: 0 ns
CPU Time: 0.460 seconds; Data structure size: 0.1Mb
Sat Dec 31 23:40:21 2022

Output madhe kontya file madhun uvm_info print zale aahe te kalte ex. Testbench.sv(10)
Output madhe konty time la uvm_info print zale te kalte : ex .45
String ID cha message print hoto.

5] Set and get verbosity in uvm module tb code

Code :
`include "uvm_macros.svh";
import uvm_pkg::*;

module tb();

initial
begin
`uvm_info("TB","inside the uvm_none",UVM_NONE);
`uvm_info("TB","inside the uvm_low",UVM_LOW);
`uvm_info("TB","inside the uvm_medium",UVM_MEDIUM);
`uvm_info("TB","inside the uvm_high",UVM_HIGH);
`uvm_info("TB","inside the uvm_full",UVM_FULL);

end
endmodule

Output:

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

1] Repoerting mechanism LOW Page 185

UVM_INFO testbench.sv(9) @ 0: reporter [TB] inside the uvm_none
UVM_INFO testbench.sv(10) @ 0: reporter [TB] inside the uvm_low
UVM_INFO testbench.sv(11) @ 0: reporter [TB] inside the uvm_medium
VCS Simulation Report
Time: 0 ns
CPU Time: 0.520 seconds; Data structure size: 0.1Mb
Sun Jan 1 00:25:39 2023

Note:

1] Ethe uvm_info print hotana default verbosity hi uvm_medium aahe. Tymule uvm_medium chya khaleche serve print
hotata manje UVM_LOW, UVM_NONE, UVM_MEDIUM print hotat.
2] Ethe aata uvm_HIGH,UVM_FULL print nahi hote. Karan aapan ethe verbosity level set nahi kele aahe.

Some changes:
1] initial
begin
uvm_top.set_report_verbosity_level(UVM_FULL);
end

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO testbench.sv(9) @ 0: reporter [TB] inside the uvm_none

UVM_INFO testbench.sv(10) @ 0: reporter [TB] inside the uvm_low
UVM_INFO testbench.sv(11) @ 0: reporter [TB] inside the uvm_medium
UVM_INFO testbench.sv(12) @ 0: reporter [TB] inside the uvm_high
UVM_INFO testbench.sv(13) @ 0: reporter [TB] inside the uvm_full
VCS Simulation Report
Time: 0 ns
CPU Time: 0.620 seconds; Data structure size: 0.1Mb
Sun Jan 1 00:30:33 2023

Note : ethe uvm_top ghetale aahe karan aapan set module tb saathi karat aahot tymule. Uvm_top ha uvm_root cha
handle aahe.

2] Run option madhe +UVM_VERBOSITY=UVM_FULL ya switch cha use karava. Ya switch cha use kela ne jevdhe kahi
UVM_INFO statement aahe tyche verbosity level change hote

1] Repoerting mechanism LOW Page 186

Code :
`include "uvm_macros.svh";
import uvm_pkg::*;

module tb();

initial
begin

`uvm_info("TB","inside the uvm_none",UVM_NONE);

`uvm_info("TB","inside the uvm_low",UVM_LOW);
`uvm_info("TB","inside the uvm_medium",UVM_MEDIUM);
`uvm_info("TB","inside the uvm_high",UVM_HIGH);
`uvm_info("TB","inside the uvm_full",UVM_FULL);

end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO testbench.sv(9) @ 0: reporter [TB] inside the uvm_none

UVM_INFO testbench.sv(10) @ 0: reporter [TB] inside the uvm_low
UVM_INFO testbench.sv(11) @ 0: reporter [TB] inside the uvm_medium
UVM_INFO testbench.sv(12) @ 0: reporter [TB] inside the uvm_high
UVM_INFO testbench.sv(13) @ 0: reporter [TB] inside the uvm_full
VCS Simulation Report
Time: 0 ns
CPU Time: 0.520 seconds; Data structure size: 0.1Mb
Sun Jan 1 00:34:38 2023

Note:
1] Ethe aapan +UVM_VERBOSITY=UVM_FULL ya switch cha use kela tymule ethe serve print zale aahe

1] Repoerting mechanism LOW Page 187

6] Change the verbosity of string ID
Ethe string ID che verbosity level change karaya che asel tar set_report_id_verbosity( " je string id aahe te lihave", konti
verbosity level set karayachi aahe ti verbosity level)

Code :
`include "uvm_macros.svh";
import uvm_pkg::*;

class driver extends uvm_driver;

`uvm_component_utils(driver);

function new(string path="driver",uvm_component parent=null);

super.new(path,parent);
endfunction

task run();
`uvm_info("drv1"," info 1",UVM_NONE);
`uvm_info("drv1"," info 2",UVM_MEDIUM);
`uvm_info("drv2"," info 3",UVM_MEDIUM);
`uvm_info("drv2"," info 4",UVM_HIGH);
endtask
endclass

module tb();
driver d;

initial
begin
d=new("driver1",null);
d.set_report_id_verbosity("drv1",UVM_LOW);
d.run();
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO testbench.sv(13) @ 0: driver1 [drv1] info 1

UVM_INFO testbench.sv(15) @ 0: driver1 [drv2] info 3
VCS Simulation Report
Time: 0 ns
CPU Time: 0.540 seconds; Data structure size: 0.1Mb
Sun Jan 1 10:27:59 2023

Note:
1] varti je output aahe tithe string drv1 che fkt one statement che print zale aahe. Karan tithe drv1 che verbosity level
change kele aahe

1] Repoerting mechanism LOW Page 188

change kele aahe

7] Ji hierarchy aahe tyche change karayache verbosity level change.

Code :
`include "uvm_macros.svh"
import uvm_pkg::*;

/////////////////////////////////////////////////
class driver extends uvm_monitor;
`uvm_component_utils(driver);

function new(string path,uvm_component parent);

super.new(path,parent);
endfunction

task run();
`uvm_info("DRV","driver code executed",UVM_HIGH);
endtask
endclass

/////////////////////////////////////////////////
class monitor extends uvm_monitor;
`uvm_component_utils(monitor);

function new(string path,uvm_component parent);

super.new(path,parent);
endfunction

task run();
`uvm_info("MON","monitor code executed",UVM_NONE);
endtask
endclass

class env extends uvm_env;

`uvm_component_utils(env);

driver drv;
monitor mon;

function new(string path,uvm_component parent);

super.new(path,parent);
endfunction

task run();
drv=new("drv",this);
mon=new("mon",this);
drv.run();
mon.run();

`uvm_info("ENV","envirnment class executed",UVM_NONE);

endtask
endclass

module tb();
env e;

1] Repoerting mechanism LOW Page 189

 env e;
initial
begin
e=new("env",null);
e.set_report_verbosity_level_hier(UVM_HIGH); ethe ji hierarchy banli aahe env---------> driver/monitor yachi
verbosity change hote
e.run();
end
endmodule

Output:
UVM_INFO testbench.sv(13) @ 0: env.drv [DRV] driver code executed
UVM_INFO testbench.sv(26) @ 0: env.mon [MON] monitor code executed
UVM_INFO testbench.sv(46) @ 0: env [ENV] envirnment class executed
VCS Simulation Report
Time: 0 ns

1.3] Changing the severity of macros

set_report_severity_override(jyla change karache aahe te severity,jithe change karayache aahe te);

UVM_FATAL che ----------> UVM_ERROR madhe conversion hote.

d.set_report_severity_override(UVM_FATAL,UVM_ERROR);

1] change the severity of whole class

Code :
`include "uvm_macros.svh"
import uvm_pkg::*;
class driver extends uvm_monitor;
`uvm_component_utils(driver);

function new(string path , uvm_component parent);

super.new(path, parent);
endfunction

task run();
`uvm_info("drv","uvm_info print",UVM_NONE);
`uvm_warning("drv","uvm_warning print");
`uvm_error("drv","uvm_error print");
`uvm_fatal("drv","uvm_fatal print");
endtask
endclass

module tb();
driver d;
initial
begin
d=new("env",null);
d.set_report_severity_override(UVM_FATAL,UVM_ERROR);
d.run();
end

1] Repoerting mechanism LOW Page 190

 end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO testbench.sv(13) @ 0: env [drv] uvm_info print

UVM_WARNING testbench.sv(14) @ 0: env [drv] uvm_warning print
UVM_ERROR testbench.sv(15) @ 0: env [drv] uvm_error print
UVM_ERROR testbench.sv(16) @ 0: env [drv] uvm_fatal print
VCS Simulation Report
Time: 0 ns
CPU Time: 0.500 seconds; Data structure size: 0.1Mb
Sun Jan 1 11:04:51 2023

Some changes:

Code :
module tb();
int a;
driver d1;

initial
begin
d1=new("drivernew",null);
d1.set_report_verbosity_level(UVM_LOW);
d1.set_report_severity_override(UVM_FATAL,UVM_INFO);
d1.rund();
a=d1.get_report_verbosity_level();
$display("value of verbosity level=%0d",a);
end
endmodule

Output:
UVM_INFO testbench.sv(13) @ 10: drivernew [drv] inside the info driver 1
UVM_ERROR testbench.sv(14) @ 10: drivernew [drv] inside the error driver1
UVM_WARNING testbench.sv(15) @ 10: drivernew [drv] inside the warning driver1
UVM_INFO testbench.sv(16) @ 10: drivernew [drv1] inside the fatal driver1
value of verbosity level=100
VCS Simulation Report
Time: 10 ns
CPU Time: 0.820 seconds; Data structure size: 0.1Mb
Mon Feb 20 22:52:03 2023

Note:

1] Jar aapan class cha verbosity change keli pan tycha kahi effect nahi zala UVM_FATAL ----> UVM_INFO kartana
2] UVM_FATAL che UVM_INFO zale tar tyche default verbosity hi UVM_MEDIUM aasayela pahije pan tase hote nahi. Te
direct print karte class cha verbosity pahat nahi.

1] Repoerting mechanism LOW Page 191

direct print karte class cha verbosity pahat nahi.

2] changing severity using tag id

Code

`include "uvm_macros.svh";
import uvm_pkg::*;

class driver extends uvm_driver;

`uvm_component_utils(driver);
function new(string path,uvm_component parent);
super.new(path,parent);
endfunction

task run();
`uvm_info("drv","inside the info",UVM_NONE);
`uvm_warning("drv","inside the warning");
`uvm_fatal("drv","inside the fatal drv");
`uvm_error("drv","inside the error");
`uvm_fatal("drv1","inside the fatal in drv1");
endtask
endclass

module tb();
driver d;

initial
begin
d=new("DRV",null);
d.set_report_severity_id_override(UVM_FATAL,"drv",UVM_ERROR); // tag ha drv aahe titche fkt apply karta yeto
d.run();
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO testbench.sv(12) @ 0: DRV [drv] inside the info

UVM_WARNING testbench.sv(13) @ 0: DRV [drv] inside the warning
UVM_ERROR testbench.sv(14) @ 0: DRV [drv] inside the fatal drv
UVM_ERROR testbench.sv(15) @ 0: DRV [drv] inside the error
UVM_FATAL testbench.sv(16) @ 0: DRV [drv1] inside the fatal in drv1
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

1] Repoerting mechanism LOW Page 192

--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 2
UVM_WARNING : 1
UVM_ERROR : 2
UVM_FATAL : 1
** Report counts by id
[UVM/RELNOTES] 1
[drv] 4
[drv1] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 135.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.580 seconds; Data structure size: 0.1Mb
Sun Jan 1 11:11:28 2023

1.4] Quit count for uvm_error

set_report_max_quit_count(3) . Ya function cha use hote uvm_error count karnyasaathi. Ethe aapan bracket madhe
uvm_error count chi limit set karu shakto.

Code :
`include "uvm_macros.svh";
import uvm_pkg::*;

class driver extends uvm_driver;

`uvm_component_utils(driver);
function new(string path,uvm_component parent);
super.new(path,parent);
endfunction

task run();
`uvm_info("drv","inside the info",UVM_NONE);
`uvm_warning("drv","inside the warning");
`uvm_error("drv","inside the error1");
`uvm_error("drv","inside the error2");
`uvm_error("drv","inside the error3");
`uvm_error("drv","inside the error4");
`uvm_error("drv","inside the error5");
endtask
endclass

module tb();
driver d;

initial
begin
d=new("DRV",null);
d.set_report_max_quit_count(3);
d.run();
end

1] Repoerting mechanism LOW Page 193

 end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO testbench.sv(11) @ 0: DRV [drv] inside the info

UVM_WARNING testbench.sv(12) @ 0: DRV [drv] inside the warning
UVM_ERROR testbench.sv(13) @ 0: DRV [drv] inside the error1
UVM_ERROR testbench.sv(14) @ 0: DRV [drv] inside the error2
UVM_ERROR testbench.sv(15) @ 0: DRV [drv] inside the error3
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

Quit count reached!

Quit count : 3 of 3
** Report counts by severity
UVM_INFO : 2
UVM_WARNING : 1
UVM_ERROR : 3
UVM_FATAL : 0
** Report counts by id
[UVM/RELNOTES] 1
[drv] 5

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 135.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.680 seconds; Data structure size: 0.1Mb
Sun Jan 1 11:25:16 2023

1] Repoerting mechanism LOW Page 194

UVM Classes =Low
01 January 2023 22:18

UVM Classes=Low
1] jn uvm che object nehami use kele jatat tyna aapan uvm_component manto . Tyche nature he statsic aaste.
Je object jenva kaam padle tenvache use kele jatat tyna aapan uvm_object aase manto. Tyche nature he dynamic aaste.

2] UVM Classes LOW Page 195

uvm_sequence_item ----> transaction
Uvm_sequence ------> generator
Uvm_sequencer

Flow of execaution

2] UVM Classes LOW Page 196

Flow of execaution

1] uvm_sequence_item( transaction) ---------> uvm_sequence(generator) ---------> uvm_sequencer -------->uvm_driver

Agent contain the monitor, driver,sequencer

2] UVM Classes LOW Page 197

UVM testbench architecture

2] UVM Classes LOW Page 198

2] UVM Classes LOW Page 199
2] UVM Classes LOW Page 200
UVM_OBJECT = Low
06 January 2023 21:55

1] Jar aapan uvm filed macro use nahi kela uvm object madhe tar aaapn print() sarkhe core method cha use nahi karu
shakat .

1] Introduction

2]

3] UVM Object LOW Page 201

3]

3] UVM Object LOW Page 202

3] UVM Object LOW Page 203
3] Regsistration of class using UVM_OBJECT

3] UVM Object LOW Page 204

3] UVM Object LOW Page 205
3] UVM Object LOW Page 206
1] code for uvm_object regsistration without field macro

Jar field macros ne che jar aapan object la define kela tar che aapan print,compare,copy method cha use karta yeto

Code :
`include "uvm_macros.svh";
import uvm_pkg::*;

class object1 extends uvm_object;

`uvm_object_utils(object1); // ethe field macro cha use kela nahi aahe. Tymule print() method cha output yet
nahi
rand bit [2:0] a;

function new(string path="object");

super.new(path);
endfunction
endclass

module tb();

3] UVM Object LOW Page 207

module tb();
object1 obj;
initial
begin
obj=new("object");
obj.randomize();
$display("value of a=%0d",obj.a);
obj.print(); ///// print method fkt jenva object field macro ne define kele jaate tenva che print hote correct
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

value of a=1
----------------------------
Name Type Size Value
----------------------------
object object1 - @336 /////////// value he different aahe.
----------------------------
VCS Simulation Report
Time: 0 ns
CPU Time: 0.800 seconds; Data structure size: 0.1Mb
Fri Jan 6 23:49:28 2023

2] code for uvm_object regsistration with field macro in factory using begin end
(maximum time uvm_object saathiche use karave)

https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.1c/html/files/macros/uvm_object_defines-
svh.html

3] UVM Object LOW Page 208

3] UVM Object LOW Page 209
Code:
`include "uvm_macros.svh";
import uvm_pkg::*;

class object1 extends uvm_object;

rand bit [2:0] a;

`uvm_object_utils_begin(object1)
`uvm_field_int(a,UVM_DEFAULT)
`uvm_object_utils_end

function new(string path="object");

super.new(path);
endfunction
endclass

module tb();
object1 obj;
initial
begin
obj=new("object");
obj.randomize();
$display("value of a=%0d",obj.a);
obj.print();
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

value of a=1
-----------------------------
Name Type Size Value
-----------------------------
object object1 - @336
a integral 3 'h1 ////// value same aahe karan object field macro ne define kela aahe
-----------------------------
VCS Simulation Report
Time: 0 ns
CPU Time: 0.720 seconds; Data structure size: 0.1Mb
Fri Jan 6 23:45:28 2023

3] code for ENUM,Real,String data type object print using field macro

Code :

`include "uvm_macros.svh"
import uvm_pkg::*;

3] UVM Object LOW Page 210

import uvm_pkg::*;

class obj extends uvm_object;

typedef enum bit [3:0] {s0 , s1, s2, s3} state_type;

rand state_type state;

real temp = 12.34;

string str = "UVM";

function new(string path = "obj");

super.new(path);
endfunction

`uvm_object_utils_begin(obj)
`uvm_field_enum(state_type, state, UVM_DEFAULT); // two time define karave legel variable
`uvm_field_string(str,UVM_DEFAULT);
`uvm_field_real(temp, UVM_DEFAULT);
`uvm_object_utils_end

endclass

module tb;
obj o;

initial begin
o = new("obj");
o.randomize();
o.print;
end

endmodule

Output:

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

------------------------------------
Name Type Size Value
------------------------------------
obj obj - @336
state state_type 4 s1
str string 3 UVM
temp real 64 12.340000
------------------------------------
VCS Simulation Report
Time: 0 ns
CPU Time: 0.540 seconds; Data structure size: 0.1Mb
Sat Jan 7 00:36:47 2023

3] UVM Object LOW Page 211

4] Code for print the array using field macro

Code :
`include "uvm_macros.svh";
import uvm_pkg::*;

class object1 extends uvm_object;

rand bit [7:0] a[3:0];

`uvm_object_utils_begin(object1)
`uvm_field_sarray_int(a,UVM_DEFAULT)
`uvm_object_utils_end

function new(string path="object");

super.new(path);
endfunction
endclass

module tb();
object1 obj;
int i;
initial
begin
obj=new("object");
obj.randomize();
$display("value of a=%0d",obj.a[i]);
obj.print();
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

value of a=163
----------------------------------
Name Type Size Value

3] UVM Object LOW Page 212

Name Type Size Value
----------------------------------
object object1 - @336
a sa(integral) 1 -
[0] integral 8 'ha3
[1] integral 8 'ha7
[2] integral 8 'h6c
[3] integral 8 'hb9
----------------------------------
VCS Simulation Report
Time: 0 ns
CPU Time: 0.820 seconds; Data structure size: 0.1Mb
Sat Jan 7 00:45:20 2023

5] all array implementation using field macros

Code :
`include "uvm_macros.svh"
import uvm_pkg::*;

class array extends uvm_object;

////////static array
int arr1[3] = {1,2,3};

///////Dynamic array
int arr2[];

///////Queue
int arr3[$];

////////Associative array
int arr4[int];

function new(string path = "array");

super.new(path);
endfunction

`uvm_object_utils_begin(array)
`uvm_field_sarray_int(arr1, UVM_DEFAULT);
`uvm_field_array_int(arr2, UVM_DEFAULT);
`uvm_field_queue_int(arr3, UVM_DEFAULT);
`uvm_field_aa_int_int(arr4, UVM_DEFAULT);
`uvm_object_utils_end

task run();

///////////////////Dynamic array value update

arr2 = new[3];
arr2[0] = 2;
arr2[1] = 2;
arr2[2] = 2;

///////////////////Queue

3] UVM Object LOW Page 213

 ///////////////////Queue
arr3.push_front(3);
arr3.push_front(3);

////////////////////Associative arrays
arr4[1] = 4;
arr4[2] = 4;
arr4[3] = 4;
arr4[4] = 4;

endtask

endclass

////////////////////////////////////////////

module tb;
array a;

initial begin
a = new("array");
a.run();
a.print();
end

endmodule

Output:
You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM]
QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(216) @ 0: reporter [Questa UVM]
questa_uvm::init(+struct)
# ----------------------------------
# Name Type Size Value
# ----------------------------------
# array array - @466
# arr1 sa(integral) 3 -
# [0] integral 32 'h1
# [1] integral 32 'h2
# [2] integral 32 'h3
# arr2 da(integral) 3 -
# [0] integral 32 'h2
# [1] integral 32 'h2
# [2] integral 32 'h2
# arr3 da(integral) 2 -
# [0] integral 32 'h3
# [1] integral 32 'h3
# arr4 aa(int,int) 4 -
# [1] integral 32 'h4
# [2] integral 32 'h4
# [3] integral 32 'h4
# [4] integral 32 'h4
# ----------------------------------

3] UVM Object LOW Page 214

# ----------------------------------
# quit -sim
# End time: 16:39:17 on Feb 22,2023, Elapsed time: 0:00:06
# Errors: 0, Warnings: 0

2] Core method use in field macros

a] Copy Method

Code :
`include "uvm_macros.svh";
import uvm_pkg::*;

class object1 extends uvm_object;

rand bit [7:0] a;

`uvm_object_utils_begin(object1)
`uvm_field_int(a,UVM_DEFAULT)
`uvm_object_utils_end

3] UVM Object LOW Page 215

 `uvm_object_utils_end

function new(string path="object");

super.new(path);
endfunction
endclass

module tb();
object1 first;
object1 second;

initial
begin
first=new("first");
second=new("second"); // ye method madhe aapan new data cha memory create keli .
first.randomize();
first.print();
second.copy(first); // target.copy(start)
second.print(); /aapan field macros che copy method ne first madhla data second madhe copy kela
first.print();
end
endmodule

Output :
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

----------------------------
Name Type Size Value
----------------------------
first object1 - @336
a integral 8 'hb9
----------------------------
-----------------------------
Name Type Size Value
-----------------------------
second object1 - @337
a integral 8 'hb9
-----------------------------
----------------------------
Name Type Size Value
----------------------------
first object1 - @336
a integral 8 'hb9
----------------------------
VCS Simulation Report
Time: 0 ns
CPU Time: 0.840 seconds; Data structure size: 0.1Mb
Sat Jan 7 01:02:00 2023

b] Compare Method
Target.compare(start);

3] UVM Object LOW Page 216

Code :
`include "uvm_macros.svh";
import uvm_pkg::*;

class trial extends uvm_object;

rand bit[4:0] a=12;

`uvm_object_utils_begin(trial)
`uvm_field_int(a,UVM_DEFAULT)

`uvm_object_utils_end

function new(string path="trial");

super.new(path);
endfunction

task runt();
`uvm_info("class","inside the class",UVM_NONE);
endtask
endclass

module tb();
int status;
trial t1;
trial t2;

initial
begin
t1=new("trial1new");
t2=new("trial2new");
t1.randomize();
t2.randomize();
t1.print();
t2.print();
status=t2.compare(t1); // ethe status dhalvale jaate jar same asel tar output 1 nahir zero(0)
$display("value of status=%0d",status);
t1.runt();
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM]
QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(216) @ 0: reporter [Questa UVM]
questa_uvm::init(+struct)
# --------------------------------
# Name Type Size Value
# --------------------------------
# trial1new trial - @466
# a integral 5 'h17
# --------------------------------

3] UVM Object LOW Page 217

# --------------------------------
# --------------------------------
# Name Type Size Value
# --------------------------------
# trial2new trial - @467
# a integral 5 'h0
# --------------------------------
# UVM_INFO @ 0: reporter [MISCMP] Miscompare for trial2new.a: lhs = 'h0 : rhs = 'h17
# UVM_INFO @ 0: reporter [MISCMP] 1 Miscompare(s) for object trial1new@466 vs. trial2new@467
# value of status=0
# UVM_INFO first.sv(17) @ 0: reporter [class] inside the class
# quit -sim
# End time: 16:09:42 on Feb 22,2023, Elapsed time: 0:00:07
# Errors: 0, Warnings: 2

Some changes:
class trial extends uvm_object;
bit[4:0] a=12;

`uvm_object_utils_begin(trial)
`uvm_field_int(a,UVM_DEFAULT)
`uvm_object_utils_end

module tb();
int status;
trial t1;
trial t2;

initial
begin
t1=new("trial1new");
t2=new("trial2new");

t1.print();
t2.print();
status=t2.compare(t1);
$display("value of status=%0d",status);
t1.runt();
end

Output:

You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM]
QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(216) @ 0: reporter [Questa UVM]
questa_uvm::init(+struct)
# --------------------------------
# Name Type Size Value
# --------------------------------
# trial1new trial - @466
# a integral 5 'hc
# --------------------------------

3] UVM Object LOW Page 218

# --------------------------------
# --------------------------------
# Name Type Size Value
# --------------------------------
# trial2new trial - @467
# a integral 5 'hc
# --------------------------------
# value of status=1
# UVM_INFO first.sv(17) @ 0: reporter [class] inside the class
# quit -sim
# End time: 16:15:59 on Feb 22,2023, Elapsed time: 0:00:05
# Errors: 0, Warnings: 0

c] Factory Override new vs create method

a] Factory override using create method

Code :

`include "uvm_macros.svh";
import uvm_pkg::*;

class first extends uvm_object;

rand bit [3:0] data;

`uvm_object_utils_begin(first);
`uvm_field_int(data, UVM_DEFAULT);
`uvm_object_utils_end

function new(string path="first");

super.new(path);
endfunction
endclass

class new_first extends first;

rand bit [3:0] ack;

`uvm_object_utils_begin(new_first);
`uvm_field_int(ack,UVM_DEFAULT);
`uvm_object_utils_end

function new(string path="new_first");

super.new(path);
endfunction
endclass

class comp extends uvm_component;

`uvm_component_utils(comp);
first f;
function new(string path="comp",uvm_component parent ="null"); //factory override saathi component chi garaj aaste
super.new(path,parent);
f=first::type_id::create("f");
f.randomize();
f.print();
endfunction
endclass

3] UVM Object LOW Page 219

module tb();
comp c;
initial
begin
c.set_type_override_by_type(first::get_type,new_first::get_type);
c=comp::type_id::create("comp",null);
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM]
QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(216) @ 0: reporter [Questa UVM]
questa_uvm::init(+struct)
# ------------------------------
# Name Type Size Value
# ------------------------------
#f new_first - @473
# data integral 4 'h9 // old and new data print hoto ethe
# ack integral 4 'h4 //new data pan print hoto ethe
# ------------------------------
# quit -sim
# End time: 17:08:00 on Feb 22,2023, Elapsed time: 0:00:06
# Errors: 0, Warnings: 1

b] Factory override using new method

Code :
`include "uvm_macros.svh";
import uvm_pkg::*;

class first extends uvm_object;

rand bit [3:0] data;

`uvm_object_utils_begin(first);
`uvm_field_int(data, UVM_DEFAULT);
`uvm_object_utils_end

function new(string path="first");

super.new(path);
endfunction
endclass

class new_first extends first;

rand bit [3:0] ack;

`uvm_object_utils_begin(new_first);
`uvm_field_int(ack,UVM_DEFAULT);
`uvm_object_utils_end

3] UVM Object LOW Page 220

 `uvm_object_utils_end

function new(string path="new_first");

super.new(path);
endfunction
endclass

class comp extends uvm_component;

`uvm_component_utils(comp);
first f;
function new(string path="comp",uvm_component parent =null);
super.new(path,parent);
f=new("f");
f.randomize();
f.print();
endfunction
endclass

module tb();
comp c;
initial
begin
c.set_type_override_by_type(first::get_type,new_first::get_type);
c=new("comp",null);
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM]
QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(216) @ 0: reporter [Questa UVM]
questa_uvm::init(+struct)
# -----------------------------
# Name Type Size Value
# -----------------------------
#f first - @473
# data integral 4 'h9 // new data print hote nahi new method ne
# -----------------------------
# quit -sim
# End time: 17:14:15 on Feb 22,2023, Elapsed time: 0:00:07
# Errors: 0, Warnings: 1

2] Clone method

a] Casting in systemverilog

3] UVM Object LOW Page 221

 a] Casting in systemverilog
Casting is a process of converting from one data type into another data type for compatibility
In Manufacturing, Casting is a process in which liquid metal is converted into the desired object. Similarly,
SystemVerilog casting means the conversion of one data type to another datatype. During value or variable assignment to
a variable, it is required to assign value or variable of the same data type. Some situations need assignment of different
data type, in such situations, it is necessary to convert data type and assign. Otherwise, the assignment of different data
type results in a compilation error. The method of data type conversion is called casting.
In systemVerilog, there are two types of casting,
• Static casting
• Dynamic casting

Static casting
• SystemVerilog static casting is not applicable to OOP
• Static casting converts one data type to another compatible data types (example string to int)
• As the name says ‘Static’, the conversion data type is fixed
• Static casting will be checked during compilation, so there won’t be run-time checking and error reporting
• Casting is applicable to value, variable or to an expression
• A data type can be changed by using a cast ( ‘ ) operation
• The vale/variable/expression to be cast must be enclosed in parentheses or within concatenation or replication braces

Static casting example

In the below example,
the real type is converted into int type. i.e multiplication of two real numbers results in real value, the result is converted
into int and then assigned to a variable of int type.
Note: the casting is applied to expression here.

Code :
module casting;
real r_a;
int i_a;
initial begin
r_a = (2.1 * 3.2);
//real to integer conversion
i_a = int'(2.1 * 3.2); //or i_a = int'(r_a);

$display("real value is %0f",r_a);

$display("int value is %0d",i_a);
end
endmodule

Output:
CPU time: .424 seconds to compile + .551 seconds to elab + .728 seconds to link
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09; Runtime version S-2021.09; Jan 7 01:28 2023
real value is 6.720000
int value is 7
VCS Simulation Report
Time: 0 ns
CPU Time: 0.700 seconds; Data structure size: 0.0Mb
Sat Jan 7 01:28:19 2023

Dynamic casting
• Dynamic casting is used to, safely cast a super-class pointer (reference) into a subclass pointer (reference) in a class

3] UVM Object LOW Page 222

• Dynamic casting is used to, safely cast a super-class pointer (reference) into a subclass pointer (reference) in a class
hierarchy
• Dynamic casting will be checked during run time, an attempt to cast an object to an incompatible object will result in a
run-time error
• Dynamic casting is done using the $cast(destination, source) method
• With $cast compatibility of the assignment will not be checked during compile time, it will be checked during run-time

Let’s see how we can use the casting,

It is always legal to assign a child class variable to a variable of a class higher in the inheritance tree (parent class).
parent_class = child_class; //allowed
It is never legal to directly assign a parent class (super class) variable to a variable of one of its subclasses (child class).
child_class = parent_class; //not-allowed

However, it is legal to assign a super-class (parent class) handle to a subclass (child class) variable if the super-class (parent
class) handle refers to an object of the given subclass(child class).
parent_class = child_class ;
child_class = parent_class; //allowed because parent_class is pointing to child_class.
Though parent_class is pointing to the child_class, we will get a compilation error saying its not compatible type for the
assignment.
This we can over come by make use of $cast method, i.e,
$cast(child_class,parent_class);

Why is it called as dynamic casting?

In the above parent class assignment with child class example. type of parent class is changing dynamically i.e on
declaration it is of parent class type, on child class assignment it is of child class type.
Parent class handle during $cast execution is considered for the assignment, so it referred to as dynamic casting.

Code 1] assigning child class handle to parent class handle

class parent_class;
int data;
function display();
$display("value of data=%0d",data);
endfunction
endclass

class child_class extends parent_class;

int addr;

function display();
super.display();
$display("value of addr=%0d",addr);
endfunction
endclass

module tb();
parent_class p=new();
child_class c=new();

initial
begin
c.data=20;
c.addr=30;
c.display();
end
endmodule

Output:
3] UVM Object LOW Page 223
 Output:
Contains Synopsys proprietary information.
Compiler version S-2021.09; Runtime version S-2021.09; Jan 7 01:38 2023
value of data=20
value of addr=30
VCS Simulation Report
Time: 0 ns
CPU Time: 0.660 seconds; Data structure size: 0.0Mb
Sat Jan 7 01:38:33 2023

Some changes:

1]

2] Clone method

a] Casting in systemverilog
Casting is a process of converting from one data type into another data type for compatibility
In Manufacturing, Casting is a process in which liquid metal is converted into the desired object. Similarly,
SystemVerilog casting means the conversion of one data type to another datatype. During value or variable assignment to
a variable, it is required to assign value or variable of the same data type. Some situations need assignment of different
data type, in such situations, it is necessary to convert data type and assign. Otherwise, the assignment of different data
type results in a compilation error. The method of data type conversion is called casting.
In systemVerilog, there are two types of casting,
• Static casting
• Dynamic casting

Static casting
• SystemVerilog static casting is not applicable to OOP
• Static casting converts one data type to another compatible data types (example string to int)
• As the name says ‘Static’, the conversion data type is fixed
• Static casting will be checked during compilation, so there won’t be run-time checking and error reporting
• Casting is applicable to value, variable or to an expression
• A data type can be changed by using a cast ( ‘ ) operation
• The vale/variable/expression to be cast must be enclosed in parentheses or within concatenation or replication braces

Static casting example

In the below example,
the real type is converted into int type. i.e multiplication of two real numbers results in real value, the result is converted
into int and then assigned to a variable of int type.
Note: the casting is applied to expression here.

Code :

3] UVM Object LOW Page 224

 module casting;

real r_a;
int i_a;

initial begin

r_a = (2.1 * 3.2);

//real to integer conversion

i_a = int'(2.1 * 3.2); //or i_a = int'(r_a);

$display("real value is %f",r_a);

$display("int value is %d",i_a);
end
endmodule

Output:
Compiler version S-2021.09; Runtime version S-2021.09; Nov 19 23:36 2022
real value is 6.720000
int value is 7
VCS Simulation Report
Time: 0 ns
CPU Time: 0.740 seconds; Data structure size: 0.0Mb
Sat Nov 19 23:36:30 2022

Dynamic casting
• Dynamic casting is used to, safely cast a super-class pointer (reference) into a subclass pointer (reference) in a class
hierarchy
• Dynamic casting will be checked during run time, an attempt to cast an object to an incompatible object will result
in a run-time error
• Dynamic casting is done using the $cast(destination, source) method
• With $cast compatibility of the assignment will not be checked during compile time, it will be checked during run-
time

Let’s see how we can use the casting,

It is always legal to assign a child class variable to a variable of a class higher in the inheritance tree (parent class).
parent_class = child_class; //allowed
It is never legal to directly assign a parent class (super class) variable to a variable of one of its subclasses (child class).
child_class = parent_class; //not-allowed

However, it is legal to assign a super-class (parent class) handle to a subclass (child class) variable if the super-class (parent
class) handle refers to an object of the given subclass(child class).
parent_class = child_class ;
child_class = parent_class; //allowed because parent_class is pointing to child_class.
Though parent_class is pointing to the child_class, we will get a compilation error saying its not compatible type for the
assignment.
This we can over come by make use of $cast method, i.e,
$cast(child_class,parent_class);

Why is it called as dynamic casting?

In the above parent class assignment with child class example. type of parent class is changing dynamically i.e
on declaration it is of parent class type, on child class assignment it is of child class type.
Parent class handle during $cast execution is considered for the assignment, so it referred to as dynamic
casting.

1] assigning child class handle to parent class handle

class parent_class;
bit [31:0] addr;

function display();

3] UVM Object LOW Page 225

 function display();
$display("Addr = %0d",addr);
endfunction
endclass

class child_class extends parent_class;

bit [31:0] data;

function display();
super.display();
$display("Data = %0d",data);
endfunction
endclass

module inheritence;
initial begin
parent_class p=new();
child_class c=new();
c.addr = 10;
c.data = 20;
p = c; //assigning child class handle to parent class handle
c.display();
end
Endmodule

Output:

Compiler version S-2021.09; Runtime version S-2021.09; Nov 19 23:48 2022

Addr = 10
Data = 20
VCS Simulation Report
Time: 0 ns
CPU Time: 0.800 seconds; Data structure size: 0.0Mb
Sat Nov 19 23:48:35 2022

2] assigning parent class handle to child class handle

This assignment is invalid, it leads to a compilation error.

class parent_class;
bit [31:0] addr;

function display();
$display("Addr = %0d",addr);
endfunction
endclass

class child_class extends parent_class;

bit [31:0] data;

function display();
super.display();
$display("Data = %0d",data);
endfunction
endclass

module inheritence;
initial begin
parent_class p=new();
child_class c=new();
c.addr = 10;
c.data = 20;
c = p; //assigning child class handle to parent class handle
c.display();
end
endmodule

3] UVM Object LOW Page 226

Output:
Error-[SV-ICA] Illegal class assignment
testbench.sv, 24
"c = p;"
Expression 'p' on rhs is not a class or a compatible class and hence cannot
be assigned to a class handle on lhs.
Source type: class $unit::parent_class
Target type: class $unit::child_class
Please make sure that the lhs and rhs expressions are compatible.

2 warnings
1 error
CPU time: .194 seconds to compile
Exit code expected: 0, received: 1

3] assigning parent class handle to child class handle

assigning parent class handle (which is pointing to child class handle) to child class handle, leads to compile
error.

class parent_class;
bit [31:0] addr;

function display();
$display("Addr = %0d",addr);
endfunction
endclass

class child_class extends parent_class;

bit [31:0] data;

function display();
super.display();
$display("Data = %0d",data);
endfunction
endclass

module inheritence;
initial begin
parent_class p;
child_class c=new();
child_class c1;
c.addr = 10;
c.data = 20;
p = c; //p is pointing to child class handle c.
c1 = p; //type check fails during compile time.
c1.display();
end
endmodule

Output:
Error-[SV-ICA] Illegal class assignment
testbench.sv, 29
"c1 = p;"
Expression 'p' on rhs is not a class or a compatible class and hence cannot
be assigned to a class handle on lhs.
Source type: class $unit::parent_class
Target type: class $unit::child_class
Please make sure that the lhs and rhs expressions are compatible.

2 warnings
1 error
CPU time: .288 seconds to compile
Exit code expected: 0, received: 1

4] Use of $cast or casting

In the above example, assigning parent class handle (which is pointing to child class handle) to child class handle is valid
but compilation error is observed.

3] UVM Object LOW Page 227

but compilation error is observed.
During the compile time, as the handle of p is of parent class type which leads to compile error.
With the use of $cast(), type check during compile time can be skipped.

Code :
class parent_class;
bit [31:0] addr;

function display();
$display("Addr = %0d",addr);
endfunction
endclass

class child_class extends parent_class;

bit [31:0] data;

function display();
super.display();
$display("Data = %0d",data);
endfunction
endclass

module inheritence;
initial begin
parent_class p;
child_class c=new();
child_class c1;
c.addr = 10;
c.data = 20;
p = c; //p is pointing to child class handle c.
$cast(c1,p); //with the use of $cast, type chek will occur during runtime
c1.display();
end
endmodule

Output:
CPU time: .432 seconds to compile + .456 seconds to elab + .813 seconds to link
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09; Runtime version S-2021.09; Nov 19 23:53 2022
Addr = 10
Data = 20
VCS Simulation Report
Time: 0 ns
CPU Time: 0.800 seconds; Data structure size: 0.0Mb
Sat Nov 19 23:53:10 2022

Example code for clone method

`include "uvm_macros.svh"
import uvm_pkg::*;

class first extends uvm_object;

rand bit [3:0] data;

function new(string path = "first");

super.new(path);
endfunction

`uvm_object_utils_begin(first)
`uvm_field_int(data, UVM_DEFAULT);
`uvm_object_utils_end

endclass

3] UVM Object LOW Page 228

module tb;
first f;
first s;

initial begin
f = new("first");
f.randomize();
$cast(s, f.clone()); $cast cha use karun ethe clone method cha use kela aahe
f.print();
s.print();
end

endmodule

Output :
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

-----------------------------
Name Type Size Value
-----------------------------
first first - @336
data integral 4 'h9
-----------------------------
-----------------------------
Name Type Size Value
-----------------------------
first first - @337
data integral 4 'h9
-----------------------------
VCS Simulation Report
Time: 0 ns
CPU Time: 0.500 seconds; Data structure size: 0.1Mb

3] UVM Object LOW Page 229

Config_db =HIGH
02 December 2022 11:39

1] Config_db is mechanism which share the data between two classes.

5] config_db =HIGH Page 230

uvm_config_db#(which data type we are sharing between two classes)::Set(context + instance_name + key +
value)

Set(context +instance_name+key+value)

Context,instance name,key value je aahet set an get same aasave kenva pan

Ethe set and get method che instance_name and key same aahe.

Uvm_config_db # (data type of transfer value) :: get( context,instance name,key, value)

A] Context ( stastic =null , dynamic =this) mostly null use kartaat

5] config_db =HIGH Page 231

A] Context ( stastic =null , dynamic =this) mostly null use kartaat
1] null asel tar testbench envirenment madhe jevdhe kahi classes aahet tyna te access karta yeil

Uvm_config_db # (int) :: set(context

Jar component stastic asel tar ----------> null cha use karava EX. Module and endmodule cha part ha stastic aasto. Tithe context ha null cha use karto.

uvm_config_db # (int) :: set(context

Jar component dynamic asel tar ----------> this cha use karava EX. Class and endclass cha part ha dynamic aasto. Tithe context ha this use karto .

B] Instance name :

Ha instance name ha same aasla pahije set and get method cha

3] Key
Name of variable which value of we are sharing. Jo data aahe tychi

4] Value
Ethe variable che value lihavi kinva name of data where we hold the value.

Uvm_config_db # (int) :: set(context,instance name in double coat

1] set and get method che instance name same aasave. Instance name kahi pan thevu shakto aapan.
Uvm_config_db # (int) :: set(context,instance name in double code, key value in double coat,source of data)
Key value he generaaly variable che naav detat.

0] Best Code for to understand

//test ->env -> 2 AGENTS.......................[HIERARCY]

5] config_db =HIGH Page 232

//test ->env -> 2 AGENTS.......................[HIERARCY]

module top;
import uvm_pkg::*;
`include "uvm_macros.svh"

//AGENT
class agent extends uvm_component;
`uvm_component_utils(agent)
string s="default";

function new(string name="agent",uvm_component parent);

super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);

`uvm_info(get_full_name(),"inside build phase of agent",UVM_NONE);

if(!uvm_config_db#(string)::get(this,"","NAME",s))
begin
`uvm_error(this.get_full_name(),"cant get the value in agent");
end
`uvm_info(this.get_full_name(),$psprintf("NAME:%s",s),UVM_LOW);
endfunction

endclass

//ENV
class env extends uvm_component;
`uvm_component_utils(env)
string m="default";
agent agent1,agent2;

function new(string name="env",uvm_component parent);

super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);

agent1=agent::type_id::create("agent1",this);
agent2=agent::type_id::create("agent2",this);

`uvm_info(get_full_name(),"inside build phase of env",UVM_NONE);

if(!uvm_config_db#(string)::get(this,"","NAME",m))
begin
`uvm_error(this.get_full_name(),"cant get the value in env");
end

`uvm_info(this.get_full_name(),$psprintf("NAME:%s",m),UVM_LOW);
endfunction
endclass

//Test Class
class my_test extends uvm_test;
`uvm_component_utils(my_test)

5] config_db =HIGH Page 233

 `uvm_component_utils(my_test)
env env_h;

function new(string name="my_test",uvm_component parent);

super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);

//creating ENV
env_h=env::type_id::create("env_h",this);

uvm_config_db#(string)::set(this,"env_h*","NAME","Rajat_Jain");

//uvm_config_db#(string)::set(this,"env_h.agent1","NAME","Rajat_Jain"); //SET FOR DIFFERENT AGENTS

//uvm_config_db#(string)::set(this,"env_h.agent2","NAME","zzzzzzzzzz");

//uvm_config_db#(string)::set(this,"env_h.*","NAME","Rajat_Jain"); //EXCEPT ENV GET IN LOWER AGENTS

//uvm_config_db#(string)::set(null,"uvm_test_top.env_h*","NAME","Rajat_Jain"); //Null with whole hierarcy

// uvm_config_db#(string)::set(this.env_h,"*","NAME","Rajat_Jain"); //need to try this

endfunction
endclass

initial
begin
run_test("my_test");
end
endmodule

UVM_INFO @ 0: reporter [RNTST] Running test my_test...

UVM_INFO testbench.sv(45) @ 0: uvm_test_top.env_h [uvm_test_top.env_h] inside build phase of env
UVM_INFO testbench.sv(51) @ 0: uvm_test_top.env_h [uvm_test_top.env_h] NAME:Rajat_Jain
UVM_INFO testbench.sv(18) @ 0: uvm_test_top.env_h.agent1 [uvm_test_top.env_h.agent1] inside build phase of agent
UVM_INFO testbench.sv(24) @ 0: uvm_test_top.env_h.agent1 [uvm_test_top.env_h.agent1] NAME:Rajat_Jain
UVM_INFO testbench.sv(18) @ 0: uvm_test_top.env_h.agent2 [uvm_test_top.env_h.agent2] inside build phase of agent
UVM_INFO testbench.sv(24) @ 0: uvm_test_top.env_h.agent2 [uvm_test_top.env_h.agent2] NAME:Rajat_Jain
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 8
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[UVM/RELNOTES] 1
[uvm_test_top.env_h] 2
[uvm_test_top.env_h.agent1] 2
[uvm_test_top.env_h.agent2] 2

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCSSimulationReport
Time: 0 ns

1] Using Null context

`include "uvm_macros.svh";
import uvm_pkg::*;

5] config_db =HIGH Page 234

import uvm_pkg::*;
class env extends uvm_env;
`uvm_component_utils(env);
int data;

function new(string path="env",uvm_component parent =null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
if(uvm_config_db#(int)::get(null,"vishal","rahul",data))
`uvm_info("env",$sformatf("inside the db and value of data=%0d",data),UVM_NONE) // semicolon( ; ) ethe
//semicolon cha use karaycha nahi.use kela tar output yet nahi syntax error yeto ethe.
else
`uvm_error("env","else part and config db is not work ");
endfunction

endclass

class test extends uvm_test;

`uvm_component_utils(test);
env e;

function new(string path="test",uvm_component parent =null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("env1",this);
uvm_config_db#(int)::set(null,"vishal","rahul",15);
endfunction

endclass

module tb();
initial
begin
run_test("test");
end
endmodule

Output:
UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(216) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test test...
# UVM_INFO first.sv(14) @ 0: uvm_test_top.env1 [env] inside the db and value of data=15
#
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 4
# UVM_WARNING : 0
# UVM_ERROR : 0
# UVM_FATAL : 0
# ** Report counts by id
# [Questa UVM] 2
# [RNTST] 1
# [env] 1
# ** Note: $finish : C:/questasim64_10.7c/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430)
# Time: 0 ns Iteration: 215 Instance: /tb
#1
# Break in Task uvm_pkg/uvm_root::run_test at C:/questasim64_10.7c/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh line 430
# quit -sim
# End time: 15:42:21 on Mar 14,2023, Elapsed time: 0:08:12
# Errors: 0, Warnings: 0

5] config_db =HIGH Page 235

Note :
1] instance_name and key he donhi pan same aasle pahije set and get method che.

2] Build Phase madhe config_db la use karave.

2] Use of this keyword in context

Code :
`include "uvm_macros.svh";
import uvm_pkg::*;
class env extends uvm_env;
`uvm_component_utils(env);
int data;

function new(string path="env",uvm_component parent =null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
if(uvm_config_db#(int)::get(this,"vishal","rahul",data))
`uvm_info("env",$sformatf("inside the db and value of data=%0d",data),UVM_NONE)
else
`uvm_error("env","else part and config db is not work ");
endfunction

endclass

class test extends uvm_test;

`uvm_component_utils(test);
env e;
int send=15;

function new(string path="test",uvm_component parent =null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("env1",this);
uvm_config_db#(int)::set(this,"env1.vishal","rahul",send); // Ethe jar aapan env1 nahi lihale naste tar output aale
// naste karan same instance name and key he same aale naste tymule
`uvm_info("env",$sformatf("send value send=%0d",send),UVM_NONE) ;
endfunction

endclass

module tb();
initial
begin
run_test("test");
end
endmodule

Output:
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3

5] config_db =HIGH Page 236

# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test test...
# UVM_INFO testbench.sv(37) @ 0: uvm_test_top [env] send value send=15
# UVM_INFO testbench.sv(14) @ 0: uvm_test_top.env1 [env] inside the db and value of data=15
# UVM_INFO verilog_src/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]
# --- UVM Report Summary ---
#
# ** Report counts by severity

Some changes :

Code :
class test extends uvm_test;
`uvm_component_utils(test);
env e;
int send=15;

function new(string path="test",uvm_component parent =null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase); test. env.vishal

super.build_phase(phase);
e=env::type_id::create("env1",this);
uvm_config_db#(int)::set(this,"vishal","rahul",send); // remove the env1
`uvm_info("env",$sformatf("send value send=%0d",send),UVM_NONE) ;
endfunction

endclass

Output:
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test test...
# UVM_INFO testbench.sv(37) @ 0: uvm_test_top [env] send value send=15
# UVM_ERROR testbench.sv(16) @ 0: uvm_test_top.env1 [env] else part and config db is not work
# UVM_FATAL @ 0: reporter [BUILDERR] stopping due to build errors
# UVM_INFO verilog_src/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]
# --- UVM Report Summary ---
#
# ** Report counts by severity

5] config_db =HIGH Page 237

Phase new = HIGH
16 July 2023 23:58

All UVM_Phase are used for class which is derived from UVM_COMPONENT.
UVM_PHASE is not applicable for UVM_OBJECT

The phases are an important concept in uvm that applies to all testbench components.

1] Each testbench component is derived from uvm_component that has predefined phases . They are represented as
callback methods. Hence, the user may implement these callbacks.

2] Each component can not move to the next phase unless the current phase execution is completed for all the components.
This provides proper synchronization between all the components.

3] UVM phases are executed in a certain order and all are virtual methods.
Few phases that consume simulation time for execution are implemented as tasks and other phases that do not consume
any simulation time are implemented as functions.

4] Main categories in UVM phases.

a. Build phases: Used to configure or construct the testbench.
b. Run-time phases: Time-consuming testbench activity like running the test case.
c. Clean up phases: Collect and report the results of the simulation.

6] UVM Phase Page 238

How does UVM phase execution start?
The run_test() method is required to call from the static part of the testbench. This will trigger up the UVM testbench. It is
usually called in the initial block from the top-level testbench module. The run_test() method call to construct the UVM
environment root component and then initiates the UVM phasing mechanism.

1] Build phases
To construct a testbench, it is necessary to build component objects first and then are connected to form a hierarchy, The
build phase category consists

Phase Name Description Excecution

approach
build_phase Build or create testbench component Top to down

connect_phase Connect different testbench component using the TLM port mechanism Bottom to top

end_of_elaborati Before simulation starts, this phase is used to make any final adjustment to the Bottom to top
on_phase structure, configuration, or connectivity of the testbench. It also displays UVM topology.

6] UVM Phase Page 239

2] Run-time phases
Once testbench components are created and connected in the testbench, it follows run phases where actual simulation time
consumes. After completing, start_of_simulation phase, there are two paths for run -time phases. The run_phase and
pre_reset phase both start at the same time.

start_of_simulation_phase: Used to display testbench topology or configuration. Bottom to top

Need to add run phase

3] Clean up phases
The clean-up phases are used to collect information from functional coverage monitors and scoreboards to see whether the
coverage goal has been reached or the test case has passed. The cleanup phases will start once the run phases are
completed. They are implemented as functions and work from the bottom to the top of the component hierarchy. The
extract, check, and report phase may be used by analysis components.

Phase Description Approach

extract Used to retrieve and process the information from functional coverage monitors and scoreboards. Bottom to
This phase may also calculate any statistical information that will be used by report_phase. top

check Checks DUT behaviour and identity for any error that occurred during the execution of the testbench. Bottom to
top

report Used to display simulation results. It can also write results to the file Bottom to
top

final Used to complete any outstanding actions that are yet to be completed in the testbench. Top to
down

2] Raise objection

6] UVM Phase Page 240

Uvm Phase madhe aapan time delay dila tar to work nahi karat karan, uvm phase delay la support nahi karat.

Code 1:
`include "uvm_macros.svh";
import uvm_pkg::*;

class driver extends uvm_driver;

`uvm_component_utils(driver);

function new(string path="drv",uvm_component parent=null);

super.new(path,parent);
endfunction

task reset_phase(uvm_phase phase);

`uvm_info("drv","reset_phase started",UVM_NONE);
#100;
`uvm_info("drv","reset_phase completed",UVM_NONE);
endtask
endclass

module tb();

initial
begin
run_test("driver");
end
endmodule

Output:

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test driver...

UVM_INFO testbench.sv(14) @ 0: uvm_test_top [drv] reset_phase started // ethe send info print nahi zala
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 3
UVM_WARNING : 0

6] UVM Phase Page 241

UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[UVM/RELNOTES] 1
[drv] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns

aapan aata raise and drop objection cha use kela aahe tymule aata aapan simulation to time delay gheto. To time delay
sampla ki next phase madhe entry gheto

Code 2:
`include "uvm_macros.svh";
import uvm_pkg::*;

class driver extends uvm_driver;

`uvm_component_utils(driver);

function new(string path="drv",uvm_component parent=null);

super.new(path,parent);
endfunction

task reset_phase(uvm_phase phase);

phase.raise_objection(this);

`uvm_info("drv","reset_phase started",UVM_NONE);
#100;
`uvm_info("drv","reset_phase completed",UVM_NONE);
phase.drop_objection(this);
endtask

endclass

module tb();

initial
begin
run_test("driver");
end
endmodule

Output:

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

6] UVM Phase Page 242

UVM_INFO @ 0: reporter [RNTST] Running test driver...
UVM_INFO testbench.sv(14) @ 0: uvm_test_top [drv] reset_phase started
UVM_INFO testbench.sv(16) @ 100: uvm_test_top [drv] reset_phase completed
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 100: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 4
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[UVM/RELNOTES] 1
[drv] 2

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 100
VCS Simulation Report
Time: 100 ns
CPU Time: 0.460 seconds; Data structure size: 0.1Mb
Tue Dec 20 12:32:40 2022

3] Ek phase complete zale ki next phase madhe jaato simulator

Code :

`include "uvm_macros.svh";
import uvm_pkg::*;

class driver extends uvm_driver;

`uvm_component_utils(driver);

function new(string path="drv",uvm_component parent=null);

super.new(path,parent);
endfunction

task reset_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("drv","reset phase started",UVM_NONE);
#10;
`uvm_info("drv","reset phase completed",UVM_NONE);
phase.drop_objection(this);
endtask

task main_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("drv","main phase started",UVM_NONE);
#100;
`uvm_info("drv","main phase complete",UVM_NONE);
phase.drop_objection(this);
endtask
endclass

module tb();

initial

6] UVM Phase Page 243

 initial
begin
run_test("driver");
end
endmodule

Result:
You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM]
QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM]
questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test driver...
# UVM_INFO testbench.sv(13) @ 0: uvm_test_top [drv] reset phase started
# UVM_INFO testbench.sv(15) @ 10: uvm_test_top [drv] reset phase completed
# UVM_INFO testbench.sv(21) @ 10: uvm_test_top [drv] main phase started
# UVM_INFO testbench.sv(23) @ 110: uvm_test_top [drv] main phase complete
# UVM_INFO verilog_src/uvm-1.2/src/base/uvm_report_server.svh(847) @ 110: reporter [UVM/REPORT/SERVER]
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 8
# UVM_WARNING : 0
# UVM_ERROR : 0
# UVM_FATAL : 0
# ** Report counts by id
# [Questa UVM] 2
# [RNTST] 1
# [UVM/RELNOTES] 1
# [drv] 4
#
# ** Note: $finish : /usr/share/questa/questasim/linux_x86_64/../verilog_src/uvm -1.2/src/base/uvm_root.svh(517)
# Time: 110 ns Iteration: 120 Instance: /tb
# End time: 04:01:25 on Dec 21,2022, Elapsed time: 0:00:08
# Errors: 0, Warnings: 2
Done

4] Ethe reset phase nanter che main phase start hote imp

Code 4:
`include "uvm_macros.svh";
import uvm_pkg::*;

///////////////////////////////////////////////////////////////

class driver extends uvm_driver;

`uvm_component_utils(driver)

function new(string path = "test", uvm_component parent = null);

super.new(path, parent);

6] UVM Phase Page 244

 super.new(path, parent);
endfunction

task reset_phase(uvm_phase phase);

phase.raise_objection(this); // name same aasle pahije
`uvm_info("drv", "Driver Reset Started", UVM_NONE);
#10;
`uvm_info("drv", "Driver Reset Ended", UVM_NONE);
phase.drop_objection(this);
endtask

task main_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("drv", "Driver Main Phase Started", UVM_NONE);
#20;
`uvm_info("drv", "Driver Main Phase Ended", UVM_NONE);
phase.drop_objection(this);
endtask

endclass

///////////////////////////////////////////////////////////////

class monitor extends uvm_monitor;

`uvm_component_utils(monitor)

function new(string path = "monitor", uvm_component parent = null);

super.new(path, parent);
endfunction

task reset_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("mon", "Monitor Reset Started", UVM_NONE);
#30;
`uvm_info("mon", "Monitor Reset Ended", UVM_NONE);
phase.drop_objection(this);
endtask

task main_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("mon", "Monitor Main Phase Started", UVM_NONE);
#50;
`uvm_info("mon", "Monitor Main Phase Ended", UVM_NONE);
phase.drop_objection(this);
endtask

endclass

////////////////////////////////////////////////////////////////////////////////////

class env extends uvm_env;

`uvm_component_utils(env)

driver d;
monitor m;

6] UVM Phase Page 245

 monitor m;

function new(string path = "env", uvm_component parent = null);

super.new(path, parent);
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
d = driver::type_id::create("d", this);
m = monitor::type_id::create("m", this);
endfunction

endclass

////////////////////////////////////////////////////////////////////////////////////////

class test extends uvm_test;

`uvm_component_utils(test)

env e;

function new(string path = "test", uvm_component parent = null);

super.new(path, parent);
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
e = env::type_id::create("e", this);
endfunction

endclass

///////////////////////////////////////////////////////////////////////////
module tb;

initial begin
run_test("test");
end
endmodule

Result:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(16) @ 0: uvm_test_top.e.d [drv] Driver Reset Started
UVM_INFO testbench.sv(48) @ 0: uvm_test_top.e.m [mon] Monitor Reset Started
UVM_INFO testbench.sv(18) @ 10: uvm_test_top.e.d [drv] Driver Reset Ended
UVM_INFO testbench.sv(50) @ 30: uvm_test_top.e.m [mon] Monitor Reset Ended
UVM_INFO testbench.sv(25) @ 30: uvm_test_top.e.d [drv] Driver Main Phase Started
UVM_INFO testbench.sv(57) @ 30: uvm_test_top.e.m [mon] Monitor Main Phase Started
UVM_INFO testbench.sv(27) @ 50: uvm_test_top.e.d [drv] Driver Main Phase Ended

6] UVM Phase Page 246

UVM_INFO testbench.sv(27) @ 50: uvm_test_top.e.d [drv] Driver Main Phase Ended
UVM_INFO testbench.sv(59) @ 80: uvm_test_top.e.m [mon] Monitor Main Phase Ended
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 80: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 10
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[UVM/RELNOTES] 1
[drv] 4
[mon] 4

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 80
VCS Simulation Report
Time: 80 ns
CPU Time: 0.880 seconds; Data structure size: 0.1Mb
Wed Dec 21 04:19:40 2022
Done

Ethe serve reset phase end zala ki tenva serve main phase start zala aahe.Time delay varun paha.

5] Normal phase example

Code :

`include "uvm_macros.svh";
import uvm_pkg::*;

class test extends uvm_test;

`uvm_component_utils(test);

function new (string path="test",uvm_component parent=null);

super.new(path,parent);
endfunction

//////////// construction phase ////////

function void build_phase(uvm_phase phase);

super.build_phase(phase);
`uvm_info("test","build phase executed",UVM_NONE);
endfunction

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info("test","connect_phase executed",UVM_NONE);
endfunction

function void end_of_elaboration_phase(uvm_phase phase);

super.end_of_elaboration_phase(phase);

6] UVM Phase Page 247

 super.end_of_elaboration_phase(phase);
`uvm_info("test","end of elaboration executed ",UVM_NONE);
endfunction

function void start_of_simulation_phase(uvm_phase phase);

super.start_of_simulation_phase(phase);
`uvm_info("test","start of simulation is executed",UVM_NONE);
endfunction

///////////// run phase /////////////

task run_phase(uvm_phase phase);

`uvm_info("test"," run phase executed",UVM_NONE);
endtask

//////// clean up phases //////////

function void extract_phase(uvm_phase phase);

super.extract_phase(phase);
`uvm_info("test","extract phase executed",UVM_NONE);
endfunction

function void check_phase(uvm_phase phase);

super.check_phase(phase);
`uvm_info("test","check_phase executed",UVM_NONE);
endfunction

function void report_phase(uvm_phase phase);

super.report_phase(phase);
`uvm_info("test","report phase executed ",UVM_NONE);
endfunction

function void final_phase(uvm_phase phase);

super.final_phase(phase);
`uvm_info("test","final phase is executed",UVM_NONE);
endfunction

endclass

module tb();

initial
begin
run_test("test");
end
endmodule

Output:

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

6] UVM Phase Page 248

UVM_INFO @ 0: reporter [RNTST] Running test test...
UVM_INFO testbench.sv(15) @ 0: uvm_test_top [test] build phase executed
UVM_INFO testbench.sv(20) @ 0: uvm_test_top [test] connect_phase executed // serve phase he sequentially run
hotat
UVM_INFO testbench.sv(25) @ 0: uvm_test_top [test] end of elaboration executed
UVM_INFO testbench.sv(30) @ 0: uvm_test_top [test] start of simulation is executed
UVM_INFO testbench.sv(36) @ 0: uvm_test_top [test] run phase executed
UVM_INFO testbench.sv(45) @ 0: uvm_test_top [test] extract phase executed
UVM_INFO testbench.sv(50) @ 0: uvm_test_top [test] check_phase executed
UVM_INFO testbench.sv(55) @ 0: uvm_test_top [test] report phase executed
UVM_INFO testbench.sv(60) @ 0: uvm_test_top [test] final phase is executed
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 11
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[UVM/RELNOTES] 1
[test] 9

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns

6] Jar aapan tyche sequence change kele tar kothe hi

Code :

`include "uvm_macros.svh";
import uvm_pkg::*;

class test extends uvm_test;

`uvm_component_utils(test);

function new (string path="test",uvm_component parent=null);

super.new(path,parent);
endfunction

///////////// mixed phase //////

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info("test","connect_phase executed",UVM_NONE);
endfunction

function void end_of_elaboration_phase(uvm_phase phase);

super.end_of_elaboration_phase(phase);
`uvm_info("test","end of elaboration executed ",UVM_NONE);
endfunction

6] UVM Phase Page 249

 endfunction

function void extract_phase(uvm_phase phase);

super.extract_phase(phase);
`uvm_info("test","extract phase executed",UVM_NONE);
endfunction

function void final_phase(uvm_phase phase);

super.final_phase(phase);
`uvm_info("test","final phase is executed",UVM_NONE);
endfunction

task run_phase(uvm_phase phase);

`uvm_info("test"," run phase executed",UVM_NONE);
endtask

function void build_phase(uvm_phase phase);

super.build_phase(phase);
`uvm_info("test","build phase executed",UVM_NONE);
endfunction

function void start_of_simulation_phase(uvm_phase phase);

super.start_of_simulation_phase(phase);
`uvm_info("test","start of simulation is executed",UVM_NONE);
endfunction

function void check_phase(uvm_phase phase);

super.check_phase(phase);
`uvm_info("test","check_phase executed",UVM_NONE);
endfunction

function void report_phase(uvm_phase phase);

super.report_phase(phase);
`uvm_info("test","report phase executed ",UVM_NONE);
endfunction

endclass

module tb();

initial
begin
run_test("test");
end
endmodule

Output
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(40) @ 0: uvm_test_top [test] build phase executed
UVM_INFO testbench.sv(15) @ 0: uvm_test_top [test] connect_phase executed
UVM_INFO testbench.sv(20) @ 0: uvm_test_top [test] end of elaboration executed
UVM_INFO testbench.sv(45) @ 0: uvm_test_top [test] start of simulation is executed

6] UVM Phase Page 250

UVM_INFO testbench.sv(45) @ 0: uvm_test_top [test] start of simulation is executed
UVM_INFO testbench.sv(35) @ 0: uvm_test_top [test] run phase executed
UVM_INFO testbench.sv(25) @ 0: uvm_test_top [test] extract phase executed
UVM_INFO testbench.sv(50) @ 0: uvm_test_top [test] check_phase executed
UVM_INFO testbench.sv(55) @ 0: uvm_test_top [test] report phase executed
UVM_INFO testbench.sv(30) @ 0: uvm_test_top [test] final phase is executed
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 11
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[UVM/RELNOTES] 1
[test] 9

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.460 seconds; Data structure size: 0.1Mb
Mon Dec 12 07:52:27 2022

Eteh aapan pahile aahe .phases he one bye one run hotat. Tymule aapan kothe pan define kele tar kahi hote nahi.

7] Timeout no use

Code :

`include "uvm_macros.svh"
import uvm_pkg::*;
///default : 9200sec

class comp extends uvm_component;

`uvm_component_utils(comp)

function new(string path = "comp", uvm_component parent = null);

super.new(path, parent);
endfunction

task reset_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("comp","Reset Started", UVM_NONE);
#10;
`uvm_info("comp","Reset Completed", UVM_NONE);
phase.drop_objection(this);
endtask

6] UVM Phase Page 251

 endtask

task main_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("mon", " Main Phase Started", UVM_NONE);
#100;
`uvm_info("mon", " Main Phase Ended", UVM_NONE);
phase.drop_objection(this);
endtask

function void build_phase(uvm_phase phase);

super.build_phase(phase);
endfunction

endclass

///////////////////////////////////////////////////////////////////////////
module tb;

initial begin

uvm_top.set_timeout(100ns, 0);
run_test("comp");
end
endmodule

Output:

You are using a version of the UVM library that has been compiled
with `UVM_NO_DEPRECATED undefined.
See http://www.eda.org/svdb/view.php?id=3313 for more details.

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test comp...

UVM_INFO testbench.sv(16) @ 0: uvm_test_top [comp] Reset Started
UVM_INFO testbench.sv(18) @ 10: uvm_test_top [comp] Reset Completed
UVM_INFO testbench.sv(24) @ 10: uvm_test_top [mon] Main Phase Started
UVM_FATAL /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1512) @ 100: reporter [PH_TIMEOUT]
Explicit timeout of 100 hit, indicating a probable testbench issue
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 100: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 5
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 1
** Report counts by id
[PH_TIMEOUT] 1
[RNTST] 1
[UVM/RELNOTES] 1

6] UVM Phase Page 252

[UVM/RELNOTES] 1
[comp] 2
[mon] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 135.

$finish at simulation time 100
VCS Simulation Report
Time: 100 ns
CPU Time: 0.820 seconds; Data structure size: 0.1Mb
Wed Dec 21 04:57:45 2022
Done

Ethe total time ha 110 hote aahe pan ethe timeout 100ns cha takla aahe tymule ethe fatal error yeto.

8] DRAIN TIME(mainly used in end_of _elaboration phase) No use

Ha time phase complete zale ki last packet che compelete honyasaathi dile jaate.

Another approach supported by UVM is setting the drain time for the simulation environment. Drain time concept is related
to the extra time allocated to the UVM environment to process the left over activities e.g. last packet analysis & comparison
etc after all the stimulus is applied & processed

While selecting the drain time value, some random time value may not be sufficient for all the Tests, hence it is necessary to
study the requirements in detail and have good understanding of the scenarios which require extra time to complete the
processing. Choosing the worst case time can be a good strategy so that all other scenarios could be covered with -in that
time frame.

Code :

`include "uvm_macros.svh"
import uvm_pkg::*;
/////Default Timeout = 9200sec

class comp extends uvm_component;

`uvm_component_utils(comp)

function new(string path = "comp", uvm_component parent = null);

super.new(path, parent);
endfunction

task reset_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("comp","Reset Started", UVM_NONE);
#10;
`uvm_info("comp","Reset Completed", UVM_NONE);
phase.drop_objection(this);
endtask

task main_phase(uvm_phase phase);

phase.phase_done.set_drain_time(this,200); ethe drain time define kela aahe.
phase.raise_objection(this);
`uvm_info("mon", " Main Phase Started", UVM_NONE);
#100;
`uvm_info("mon", " Main Phase Ended", UVM_NONE);

6] UVM Phase Page 253

 `uvm_info("mon", " Main Phase Ended", UVM_NONE);
phase.drop_objection(this);
endtask

task post_main_phase(uvm_phase phase);

`uvm_info("mon", " Post-Main Phase Started", UVM_NONE);
endtask

function void build_phase(uvm_phase phase);

super.build_phase(phase);
endfunction

endclass

///////////////////////////////////////////////////////////////////////////
module tb;

initial begin

run_test("comp");
end
endmodule

Output:

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test comp...

UVM_INFO testbench.sv(16) @ 0: uvm_test_top [comp] Reset Started
UVM_INFO testbench.sv(18) @ 10: uvm_test_top [comp] Reset Completed
UVM_INFO testbench.sv(25) @ 10: uvm_test_top [mon] Main Phase Started
UVM_INFO testbench.sv(27) @ 110: uvm_test_top [mon] Main Phase Ended
UVM_INFO testbench.sv(32) @ 310: uvm_test_top [mon] Post-Main Phase Started
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 310: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 7
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[UVM/RELNOTES] 1
[comp] 2
[mon] 3

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 310
VCS Simulation Report
Time: 310 ns
CPU Time: 0.540 seconds; Data structure size: 0.1Mb
Wed Dec 21 12:16:19 2022
Done

6] UVM Phase Page 254

Done

9] Phase Debug
In run option use the +UVM_PHASE_TRACE phase debug switch. Tenva aaplya te phase che serve kahi information bhetel and debug
saathi sope jail

Code :

`include "uvm_macros.svh"
import uvm_pkg::*;
///default : 9200sec

class comp extends uvm_component;

`uvm_component_utils(comp)

function new(string path = "comp", uvm_component parent = null);

super.new(path, parent);
endfunction

task reset_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("comp","Reset Started", UVM_NONE);
#10;
`uvm_info("comp","Reset Completed", UVM_NONE);
phase.drop_objection(this);
endtask

task main_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("mon", " Main Phase Started", UVM_NONE);
#100;
`uvm_info("mon", " Main Phase Ended", UVM_NONE);
phase.drop_objection(this);
endtask

function void build_phase(uvm_phase phase);

super.build_phase(phase);
endfunction

endclass

///////////////////////////////////////////////////////////////////////////
module tb;

initial begin

run_test("comp");
end
endmodule

Output:
You are using a version of the UVM library that has been compiled

6] UVM Phase Page 255

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test comp...

UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 0: reporter [PH/TRC/STRT] Phase 'common' (id=187) Starting
phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 0: reporter [PH/TRC/DONE] Phase 'common' (id=187)
Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.build' (id=
190) Scheduled from phase common
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 0: reporter [PH/TRC/STRT] Phase 'common.build' (id=190)
Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 0: reporter [PH/TRC/DONE] Phase 'common.build' (id=190)
Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.connect'
(id=193) Scheduled from phase common.build
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 0: reporter [PH/TRC/STRT] Phase 'common.connect' (id=193)
Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 0: reporter [PH/TRC/DONE] Phase 'common.connect' (id=193)
Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 0: reporter [PH/TRC/SCHEDULED] Phase
'common.end_of_elaboration' (id=196) Scheduled from phase common.connect
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 0: reporter [PH/TRC/STRT] Phase
'common.end_of_elaboration' (id=196) Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 0: reporter [PH/TRC/DONE] Phase
'common.end_of_elaboration' (id=196) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 0: reporter [PH/TRC/SCHEDULED] Phase
'common.start_of_simulation' (id=199) Scheduled from phase common.end_of_elaboration
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 0: reporter [PH/TRC/STRT] Phase
'common.start_of_simulation' (id=199) Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 0: reporter [PH/TRC/DONE] Phase
'common.start_of_simulation' (id=199) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.run' (id=
202) Scheduled from phase common.start_of_simulation
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm' (id=222)
Scheduled from phase common.start_of_simulation
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 0: reporter [PH/TRC/STRT] Phase 'common.run' (id=202)
Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 0: reporter [PH/TRC/STRT] Phase 'uvm' (id=222) Starting
phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 0: reporter [PH/TRC/DONE] Phase 'uvm' (id=222) Completed
phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_sched'
(id=224) Scheduled from phase uvm
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched' (id=224)
Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched' (id=224)
Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 0: reporter [PH/TRC/SCHEDULED] Phase
'uvm.uvm_sched.pre_reset' (id=227) Scheduled from phase uvm.uvm_sched
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.pre_reset'
(id=227) Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1445) @ 0: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.pre_reset'
(id=227) No objections raised, skipping phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1445) @ 0: reporter [PH/TRC/SKIP] Phase 'common.run' (id=202) No
objections raised, skipping phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched.pre_reset'
(id=227) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 0: reporter [PH/TRC/SCHEDULED] Phase
'uvm.uvm_sched.reset' (id=236) Scheduled from phase uvm.uvm_sched.pre_reset
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.reset' (id=
236) Starting phase
UVM_INFO testbench.sv(16) @ 0: uvm_test_top [comp] Reset Started
UVM_INFO testbench.sv(18) @ 10: uvm_test_top [comp] Reset Completed
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 10: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched.reset'
(id=236) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 10: reporter [PH/TRC/SCHEDULED] Phase
'uvm.uvm_sched.post_reset' (id=245) Scheduled from phase uvm.uvm_sched.reset
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 10: reporter [PH/TRC/STRT] Phase
'uvm.uvm_sched.post_reset' (id=245) Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1445) @ 10: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.post_reset'
(id=245) No objections raised, skipping phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 10: reporter [PH/TRC/DONE] Phase
'uvm.uvm_sched.post_reset' (id=245) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 10: reporter [PH/TRC/SCHEDULED] Phase
'uvm.uvm_sched.pre_configure' (id=254) Scheduled from phase uvm.uvm_sched.post_reset
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 10: reporter [PH/TRC/STRT] Phase
'uvm.uvm_sched.pre_configure' (id=254) Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1445) @ 10: reporter [PH/TRC/SKIP] Phase
'uvm.uvm_sched.pre_configure' (id=254) No objections raised, skipping phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 10: reporter [PH/TRC/DONE] Phase
'uvm.uvm_sched.pre_configure' (id=254) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 10: reporter [PH/TRC/SCHEDULED] Phase
'uvm.uvm_sched.configure' (id=263) Scheduled from phase uvm.uvm_sched.pre_configure
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 10: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.configure'

6] UVM Phase Page 256

UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 10: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.configure'
(id=263) Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1445) @ 10: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.configure'
(id=263) No objections raised, skipping phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 10: reporter [PH/TRC/DONE] Phase
'uvm.uvm_sched.configure' (id=263) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 10: reporter [PH/TRC/SCHEDULED] Phase
'uvm.uvm_sched.post_configure' (id=272) Scheduled from phase uvm.uvm_sched.configure
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 10: reporter [PH/TRC/STRT] Phase
'uvm.uvm_sched.post_configure' (id=272) Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1445) @ 10: reporter [PH/TRC/SKIP] Phase
'uvm.uvm_sched.post_configure' (id=272) No objections raised, skipping phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 10: reporter [PH/TRC/DONE] Phase
'uvm.uvm_sched.post_configure' (id=272) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 10: reporter [PH/TRC/SCHEDULED] Phase
'uvm.uvm_sched.pre_main' (id=281) Scheduled from phase uvm.uvm_sched.post_configure
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 10: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.pre_main'
(id=281) Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1445) @ 10: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.pre_main'
(id=281) No objections raised, skipping phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 10: reporter [PH/TRC/DONE] Phase
'uvm.uvm_sched.pre_main' (id=281) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 10: reporter [PH/TRC/SCHEDULED] Phase
'uvm.uvm_sched.main' (id=290) Scheduled from phase uvm.uvm_sched.pre_main
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 10: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.main' (id=
290) Starting phase
UVM_INFO testbench.sv(24) @ 10: uvm_test_top [mon] Main Phase Started
UVM_INFO testbench.sv(26) @ 110: uvm_test_top [mon] Main Phase Ended
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 110: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched.main'
(id=290) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 110: reporter [PH/TRC/SCHEDULED] Phase
'uvm.uvm_sched.post_main' (id=299) Scheduled from phase uvm.uvm_sched.main
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 110: reporter [PH/TRC/STRT] Phase
'uvm.uvm_sched.post_main' (id=299) Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1445) @ 110: reporter [PH/TRC/SKIP] Phase
'uvm.uvm_sched.post_main' (id=299) No objections raised, skipping phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 110: reporter [PH/TRC/DONE] Phase
'uvm.uvm_sched.post_main' (id=299) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 110: reporter [PH/TRC/SCHEDULED] Phase
'uvm.uvm_sched.pre_shutdown' (id=308) Scheduled from phase uvm.uvm_sched.post_main
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 110: reporter [PH/TRC/STRT] Phase
'uvm.uvm_sched.pre_shutdown' (id=308) Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1445) @ 110: reporter [PH/TRC/SKIP] Phase
'uvm.uvm_sched.pre_shutdown' (id=308) No objections raised, skipping phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 110: reporter [PH/TRC/DONE] Phase
'uvm.uvm_sched.pre_shutdown' (id=308) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 110: reporter [PH/TRC/SCHEDULED] Phase
'uvm.uvm_sched.shutdown' (id=317) Scheduled from phase uvm.uvm_sched.pre_shutdown
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 110: reporter [PH/TRC/STRT] Phase
'uvm.uvm_sched.shutdown' (id=317) Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1445) @ 110: reporter [PH/TRC/SKIP] Phase
'uvm.uvm_sched.shutdown' (id=317) No objections raised, skipping phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 110: reporter [PH/TRC/DONE] Phase
'uvm.uvm_sched.shutdown' (id=317) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 110: reporter [PH/TRC/SCHEDULED] Phase
'uvm.uvm_sched.post_shutdown' (id=326) Scheduled from phase uvm.uvm_sched.shutdown
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 110: reporter [PH/TRC/STRT] Phase
'uvm.uvm_sched.post_shutdown' (id=326) Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1445) @ 110: reporter [PH/TRC/SKIP] Phase
'uvm.uvm_sched.post_shutdown' (id=326) No objections raised, skipping phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 110: reporter [PH/TRC/DONE] Phase 'common.run' (id=202)
Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 110: reporter [PH/TRC/SCHEDULED] Phase 'common.extract'
(id=211) Scheduled from phase common.run
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 110: reporter [PH/TRC/DONE] Phase
'uvm.uvm_sched.post_shutdown' (id=326) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 110: reporter [PH/TRC/SCHEDULED] Phase
'uvm.uvm_sched_end' (id=225) Scheduled from phase uvm.uvm_sched.post_shutdown
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 110: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched_end'
(id=225) Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 110: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched_end'
(id=225) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 110: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_end'
(id=223) Scheduled from phase uvm.uvm_sched_end
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 110: reporter [PH/TRC/STRT] Phase 'uvm.uvm_end' (id=223)
Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 110: reporter [PH/TRC/DONE] Phase 'uvm.uvm_end' (id=223)
Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 110: reporter [PH/TRC/STRT] Phase 'common.extract' (id=211)
Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 110: reporter [PH/TRC/DONE] Phase 'common.extract' (id=
211) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 110: reporter [PH/TRC/SCHEDULED] Phase 'common.check'
(id=214) Scheduled from phase common.extract
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 110: reporter [PH/TRC/STRT] Phase 'common.check' (id=214)
Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 110: reporter [PH/TRC/DONE] Phase 'common.check' (id=214)
Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 110: reporter [PH/TRC/SCHEDULED] Phase 'common.report'

6] UVM Phase Page 257

UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 110: reporter [PH/TRC/SCHEDULED] Phase 'common.report'
(id=217) Scheduled from phase common.check
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 110: reporter [PH/TRC/STRT] Phase 'common.report' (id=217)
Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 110: reporter [PH/TRC/DONE] Phase 'common.report' (id=217)
Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 110: reporter [PH/TRC/SCHEDULED] Phase 'common.final'
(id=220) Scheduled from phase common.report
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 110: reporter [PH/TRC/STRT] Phase 'common.final' (id=220)
Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 110: reporter [PH/TRC/DONE] Phase 'common.final' (id=220)
Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1661) @ 110: reporter [PH/TRC/SCHEDULED] Phase
'common.common_end' (id=188) Scheduled from phase common.final
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1351) @ 110: reporter [PH/TRC/STRT] Phase 'common.common_end'
(id=188) Starting phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_phase.svh(1626) @ 110: reporter [PH/TRC/DONE] Phase 'common.common_end'
(id=188) Completed phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 110: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 97
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[PH/TRC/DONE] 27
[PH/TRC/SCHEDULED] 26
[PH/TRC/SKIP] 11
[PH/TRC/STRT] 27
[RNTST] 1
[UVM/RELNOTES] 1
[comp] 2
[mon] 2

$finish called from file "/apps/vcsmx/vcs/S -2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 110
VCS Simulation Report
Time: 110 ns
CPU Time: 0.700 seconds; Data structure size: 0.1Mb
Wed Dec 21 12:46:04 2022
Done

10] Objection la trace saathi +UVM_OBJECTION_PHASE cha use kela jaato.

Code :

`include "uvm_macros.svh"
import uvm_pkg::*;
///default : 9200sec

class comp extends uvm_component;

`uvm_component_utils(comp)

function new(string path = "comp", uvm_component parent = null);

super.new(path, parent);
endfunction

task reset_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("comp","Reset Started", UVM_NONE);
#10;
`uvm_info("comp","Reset Completed", UVM_NONE);
phase.drop_objection(this);
endtask

task main_phase(uvm_phase phase);

6] UVM Phase Page 258

 task main_phase(uvm_phase phase);
phase.raise_objection(this);
`uvm_info("mon", " Main Phase Started", UVM_NONE);
#100;
`uvm_info("mon", " Main Phase Ended", UVM_NONE);
phase.drop_objection(this);
endtask

function void build_phase(uvm_phase phase);

super.build_phase(phase);
endfunction

endclass

///////////////////////////////////////////////////////////////////////////
module tb;

initial begin

run_test("comp");
end
endmodule

Output:

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test comp...

UVM_INFO @ 0: reset_objection [OBJTN_TRC] Object uvm_test_top raised 1 objection(s): count=1 total=1
UVM_INFO @ 0: reset_objection [OBJTN_TRC] Object uvm_top added 1 objection(s) to its total (raised from source object uvm_tes t_top): count=0
total=1
UVM_INFO testbench.sv(16) @ 0: uvm_test_top [comp] Reset Started
UVM_INFO testbench.sv(18) @ 10: uvm_test_top [comp] Reset Completed
UVM_INFO @ 10: reset_objection [OBJTN_TRC] Object uvm_test_top dropped 1 objection(s): count=0 total=0
UVM_INFO @ 10: reset_objection [OBJTN_TRC] Object uvm_test_top all_dropped 1 objection(s): count=0 total=0
UVM_INFO @ 10: reset_objection [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (dropped from source objec t uvm_test_top):
count=0 total=0
UVM_INFO @ 10: reset_objection [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (all_dropped from source o bject uvm_test_top):
count=0 total=0
UVM_INFO @ 10: main_objection [OBJTN_TRC] Object uvm_test_top raised 1 objection(s): count=1 total=1
UVM_INFO @ 10: main_objection [OBJTN_TRC] Object uvm_top added 1 objection(s) to its total (raised from source object uvm_tes t_top): count=0
total=1
UVM_INFO testbench.sv(24) @ 10: uvm_test_top [mon] Main Phase Started
UVM_INFO testbench.sv(26) @ 110: uvm_test_top [mon] Main Phase Ended
UVM_INFO @ 110: main_objection [OBJTN_TRC] Object uvm_test_top dropped 1 objection(s): count=0 total=0
UVM_INFO @ 110: main_objection [OBJTN_TRC] Object uvm_test_top all_dropped 1 objection(s): count=0 total=0
UVM_INFO @ 110: main_objection [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (dropped from source objec t uvm_test_top):
count=0 total=0
UVM_INFO @ 110: main_objection [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (all_dropped from source o bject
uvm_test_top): count=0 total=0
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 110: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 18
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[OBJTN_TRC] 12
[RNTST] 1
[UVM/RELNOTES] 1
[comp] 2
[mon] 2

$finish called from file "/apps/vcsmx/vcs/S -2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 110
VCS Simulation Report

6] UVM Phase Page 259

 VCS Simulation Report
Time: 110 ns
CPU Time: 0.440 seconds; Data structure size: 0.1Mb
Wed Dec 21 12:49:52 2022
Done

6] UVM Phase Page 260

TLM
22 December 2022 15:13

1]

Put Port in TLM

Data flow and control flow direction is same here

7] TLM =IMP Page 261

Put Method (Port to Export)
7] TLM =IMP Page 262
Code 1 :

`include "uvm_macros.svh";
import uvm_pkg::*;

class producer extends uvm_component;

`uvm_component_utils(producer);

int data=12;
uvm_blocking_put_port#(int) send;

function new(string path="produ",uvm_component parent=null);

super.new(path,parent);
send=new("send",this);
endfunction
endclass

class consumer extends uvm_component;

`uvm_component_utils(consumer);

uvm_blocking_put_export#(int) recv;

function new(string path="consu",uvm_component parent=null);

super.new(path,parent);
recv=new("recv",this);
endfunction
endclass

class env extends uvm_env;

`uvm_component_utils(env);
producer p;
consumer c;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase (uvm_phase phase);

super.build_phase(phase);
p=producer::type_id::create("p",this);
c=consumer::type_id::create("c",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
p.send.connect(c.recv);
endfunction
endclass

class test extends uvm_test;

`uvm_component_utils(test);
env e;

function new(string path="test",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase (uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
endfunction
endclass

module tb;

7] TLM =IMP Page 263

 initial
begin
run_test("test");
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_ERROR @ 0: uvm_test_top.e.c.recv [Connection Error] connection count of 0 does not meet required minimum of 1
UVM_ERROR @ 0: uvm_test_top.e.p.send [Connection Error] connection count of 0 does not meet required minimum of 1
UVM_FATAL @ 0: reporter [BUILDERR] stopping due to build errors
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 2
UVM_WARNING : 0
UVM_ERROR : 2
UVM_FATAL : 1
** Report counts by id
[BUILDERR] 1
[Connection Error] 2
[RNTST] 1
[UVM/RELNOTES] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 135.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 1.100 seconds; Data structure size: 0.1Mb
Thu Dec 22 06:03:59 2022
Done

Ethe aapan port and export ghetale aahe fkt. Kenva communication cha end point ha export port nasto. Communication cha end point ha
implemention port assto. Tymule varti error aale aahe.

Using implementation port

Code 2:

`include "uvm_macros.svh";
import uvm_pkg::*;

class producer extends uvm_component;

7] TLM =IMP Page 264

class producer extends uvm_component;
`uvm_component_utils(producer);

int data=12;
uvm_blocking_put_port#(int) send;

function new(string path="produ",uvm_component parent=null);

super.new(path,parent);
send=new("send",this);
endfunction

task main_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("PROD", $sformatf("Data Sent : %0d", data), UVM_NONE);
send.put(data);
phase.drop_objection(this);
endtask
endclass

class consumer extends uvm_component;

`uvm_component_utils(consumer);

uvm_blocking_put_export#(int) recv;
uvm_blocking_put_imp #(int,consumer) implement;

function new(string path="consu",uvm_component parent=null);

super.new(path,parent);
recv=new("recv",this);
implement=new("implement",this);
endfunction

function void put(int datar);

`uvm_info("Cons", $sformatf("Data Rcvd : %0d", datar), UVM_NONE);
endfunction
endclass

class env extends uvm_env;

`uvm_component_utils(env);
producer p;
consumer c;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase (uvm_phase phase);

super.build_phase(phase);
p=producer::type_id::create("p",this);
c=consumer::type_id::create("c",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
p.send.connect(c.recv);
c.recv.connect(c.implement);
endfunction
endclass

class test extends uvm_test;

`uvm_component_utils(test);
env e;

7] TLM =IMP Page 265

 function new(string path="test",uvm_component parent=null);
super.new(path,parent);
endfunction

virtual function void build_phase (uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
endfunction
endclass

module tb;

initial
begin
run_test("test");
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(17) @ 0: uvm_test_top.e.p [PROD] Data Sent : 12
UVM_INFO testbench.sv(38) @ 0: uvm_test_top.e.c [Cons] Data Rcvd : 12
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 4
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[Cons] 1
[PROD] 1
[RNTST] 1
[UVM/RELNOTES] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.480 seconds; Data structure size: 0.1Mb
Thu Dec 22 11:49:52 2022
Done

From <https://www.edaplayground.com/x/JqH8>

3] PUT To IMP port method

7] TLM =IMP Page 266

Put Port: uvm_blocking_put_port#(data_type) class name;
Ex. uvm_blocking_put_port#(int) prod;

implementation Port : uvm_blocking_put_imp#(type of data communication, implementation of put method class name) class name ;
Ex. uvm_blocking_put_imp#(int,consumer) cons;

Code :

`include "uvm_macros.svh";
import uvm_pkg::*;

class producer extends uvm_component;

`uvm_component_utils(producer);
int data =12;

uvm_blocking_put_port#(int) prod;

function new(string path="producer",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
prod=new("producer",this);
endfunction

task main_phase(uvm_phase phase);

phase.raise_objection(this);
prod.put(data);
`uvm_info("producer",$sformatf("value of data send=%0d",data),UVM_NONE);
phase.drop_objection(this);
endtask

endclass

class consumer extends uvm_component;

`uvm_component_utils(consumer);

uvm_blocking_put_imp#(int,consumer) cons;

function new(string path="consumer",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
cons=new("consumer",this);

7] TLM =IMP Page 267

 cons=new("consumer",this);
endfunction

task put(int data2);

`uvm_info("consumer",$sformatf("value of data recived=%0d",data2),UVM_NONE);
endtask
endclass

class env extends uvm_env;

`uvm_component_utils(env);
producer p;
consumer c;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
p=producer::type_id::create("producer",this);
c=consumer::type_id::create("consumer",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
p.prod.connect(c.cons);
endfunction

endclass

class test extends uvm_test;

`uvm_component_utils(test);
env e;

function new(string path="test",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("env",this);

endfunction

endclass

module tb();

initial
begin
run_test("test");
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(44) @ 0: uvm_test_top.env.consumer [consumer] value of data recived=12
UVM_INFO testbench.sv(22) @ 0: uvm_test_top.env.producer [producer] value of data send=12
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

7] TLM =IMP Page 268

** Report counts by severity
UVM_INFO : 4
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[UVM/RELNOTES] 1
[consumer] 1
[producer] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.500 seconds; Data structure size: 0.1Mb
Thu Dec 22 12:52:38 2022
Done

Port - Port to IMP connection

Code :

`include "uvm_macros.svh";
import uvm_pkg::*;

class subproducer extends uvm_component;

`uvm_component_utils(subproducer);

int data1=15;

uvm_blocking_put_port #(int) subpro1;

function new(string path="subproducer",uvm_component parent=null);
super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
subpro1=new("subpro1",this);
endfunction

task main_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("pro",$sformatf("value of data send=%0d",data1),UVM_NONE);
subpro1.put(data1);
phase.drop_objection(this);
endtask

endclass

class producer extends uvm_component;

`uvm_component_utils(producer);
subproducer s1;
uvm_blocking_put_port#(int) prod1;

function new(string path="producer",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
s1=subproducer::type_id::create("s1",this);
prod1=new("prod1",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);

7] TLM =IMP Page 269

 super.connect_phase(phase);
s1.subpro1.connect(prod1);
endfunction

endclass

class consumer extends uvm_component;

`uvm_component_utils(consumer);

uvm_blocking_put_imp#(int,consumer)cons1;

function new(string path="consumer",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
cons1=new("cons1",this);
endfunction

task put(int data2);

`uvm_info("cons",$sformatf("value of data recived=%0d",data2),UVM_NONE);
endtask

endclass

class env extends uvm_env;

`uvm_component_utils(env);
producer p1;
consumer c1;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
p1=producer::type_id::create("p1",this);
c1=consumer::type_id::create("c1",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
p1.prod1.connect(c1.cons1);
endfunction

endclass

class test extends uvm_test;

`uvm_component_utils(test);
env e;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
endfunction

virtual function void end_of_elaboration_phase(uvm_phase phase);

super.end_of_elaboration_phase(phase);
uvm_top.print_topology();
endfunction

7] TLM =IMP Page 270

 endfunction

endclass

module tb();

initial
begin
run_test("test");
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh(589) @ 0: reporter [UVMTOP] UVM testbench topology:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
uvm_test_top test - @336
e env - @349
c1 consumer - @367
cons1 uvm_blocking_put_imp - @376
p1 producer - @358
prod1 uvm_blocking_put_port - @395
s1 subproducer - @386
subpro1 uvm_blocking_put_port - @405
---------------------------------------------------

UVM_INFO testbench.sv(21) @ 0: uvm_test_top.e.p1.s1 [pro] value of data send=15

UVM_INFO testbench.sv(67) @ 0: uvm_test_top.e.c1 [cons] value of data recived=15
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 5
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[UVM/RELNOTES] 1
[UVMTOP] 1
[cons] 1
[pro] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.520 seconds; Data structure size: 0.1Mb
Mon Dec 26 07:47:44 2022

7] TLM =IMP Page 271

Code :

`include "uvm_macros.svh";
import uvm_pkg::*;

class producer extends uvm_component;

`uvm_component_utils(producer);
int data1=20;

uvm_blocking_put_port#(int) prod1;

function new(string path="producer",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
prod1=new("prod1",this);
endfunction

task main_phase(uvm_phase phase);

phase.raise_objection(phase);
`uvm_info("producer",$sformatf("value of data send =%0d",data1),UVM_NONE);
prod1.put(data1);
phase.drop_objection(phase);
endtask
endclass

class subconsumer extends uvm_component;

`uvm_component_utils(subconsumer);

uvm_blocking_put_imp#(int,subconsumer) subcons1;

7] TLM =IMP Page 272

 uvm_blocking_put_imp#(int,subconsumer) subcons1;

function new(string path="subconsumer",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
subcons1=new("subcons1",this);
endfunction

task put(int data2);

`uvm_info("subconsumer",$sformatf("value of data recived =%0d",data2),UVM_NONE);
endtask
endclass

class consumer extends uvm_component;

`uvm_component_utils(consumer);
subconsumer sc1;

uvm_blocking_put_export#(int) cons1;

function new(string path="consumer",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
cons1=new("cons1",this);
sc1=subconsumer::type_id::create("sc1",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
cons1.connect(sc1.subcons1);
endfunction
endclass

class env extends uvm_env;

`uvm_component_utils(env);
producer p1;
consumer c1;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
p1=producer::type_id::create("p1",this);
c1=consumer::type_id::create("c1",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
p1.prod1.connect(c1.cons1);
endfunction

endclass

class test extends uvm_test;

`uvm_component_utils(test);

7] TLM =IMP Page 273

 env e;

function new(string path="test",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
endfunction

virtual function void end_of_elaboration_phase(uvm_phase phase);

super.end_of_elaboration_phase(phase);
uvm_top.print_topology();
endfunction

endclass

module tb();

initial
begin
run_test("test");
end
endmodule

Output:

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh(589) @ 0: reporter [UVMTOP] UVM testbench topology:
------------------------------------------------------
Name Type Size Value
------------------------------------------------------
uvm_test_top test - @336
e env - @349
c1 consumer - @367
cons1 uvm_blocking_put_export - @376
sc1 subconsumer - @386
subcons1 uvm_blocking_put_imp - @395
p1 producer - @358
prod1 uvm_blocking_put_port - @405
------------------------------------------------------

UVM_INFO testbench.sv(21) @ 0: uvm_test_top.e.p1 [producer] value of data send =20

UVM_INFO testbench.sv(45) @ 0: uvm_test_top.e.c1.sc1 [subconsumer] value of data recived =20
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 5
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[UVM/RELNOTES] 1
[UVMTOP] 1
[producer] 1
[subconsumer] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.520 seconds; Data structure size: 0.1Mb
Mon Dec 26 08:52:09 2022

7] TLM =IMP Page 274

Get Port
Put Port is send transition from producer ---------------> consumer

Get port is used to retrive the data from consumer producer <<------------------ consumer

Get method madhe aapan producer pasun request send hote pan ya time la consumer kadhun data ghyecha aasto tymule aapan get cha use
kela jaato

Code :

`include "uvm_macros.svh";
import uvm_pkg::*;

class producer extends uvm_component;

`uvm_component_utils(producer);

int data1=0;
uvm_blocking_get_port#(int) prod1;

function new(string path="producer",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
prod1=new("prod1",this);
endfunction

task main_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("producer",$sformatf(" value of beforedata recived=%0d",data1),UVM_NONE);
prod1.get(data1);
`uvm_info("producer",$sformatf(" value of after edata recived=%0d",data1),UVM_NONE);
phase.drop_objection(this);
endtask
endclass

class consumer extends uvm_component;

`uvm_component_utils(consumer);

int data2=30;

7] TLM =IMP Page 275

 int data2=30;

uvm_blocking_get_imp#(int,consumer) cons1;

function new(string path="consumer",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
cons1=new("cons1",this);
endfunction

task get(output int data);

data=data2;
`uvm_info("consumer",$sformatf("value of data send =%0d",data2),UVM_NONE);
endtask
endclass

class env extends uvm_env;

`uvm_component_utils(env);

consumer c1;
producer p1;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
p1=producer::type_id::create("p1",this);
c1=consumer::type_id::create("c1",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
p1.prod1.connect(c1.cons1);
endfunction

endclass

class test extends uvm_test;

`uvm_component_utils(test);
env e;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
endfunction

endclass

module tb();

initial
begin
run_test("test");
end
endmodule

7] TLM =IMP Page 276

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(21) @ 0: uvm_test_top.e.p1 [producer] value of beforedata recived=0
UVM_INFO testbench.sv(47) @ 0: uvm_test_top.e.c1 [consumer] value of data send=30
UVM_INFO testbench.sv(23) @ 0: uvm_test_top.e.p1 [producer] value of after edata recived=30
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 5
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[UVM/RELNOTES] 1
[consumer] 1
[producer] 2

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.440 seconds; Data structure size: 0.1Mb
Mon Dec 26 12:44:57 2022
Done

9] Transport Port

Ya madhe two side ne data transfer hoto. Two way communication is possible In transport port

Uvm_blocking_transport_port#(producer to conumser transfer data type , consumer to producer data type received ); --->
producer class

Uvm_blocking_transport_port#(producer to conumser transfer data type , consumer to producer data type received , class
name of consumer part ); ---> producer class

Code :

`include "uvm_macros.svh";
import uvm_pkg::*;

class producer extends uvm_component;

`uvm_component_utils(producer);

int datas=30;
int datar=0;

uvm_blocking_transport_port#(int,int) prod1;
int datas=30;
int datar=0;

7] TLM =IMP Page 277

 int datar=0;

function new(string path="producer",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
prod1=new("prod1",this);
endfunction

task main_phase(uvm_phase phase);

phase.raise_objection(this);

prod1.transport(datas,datar);
`uvm_info("prod",$sformatf("value of data send=%0d and data recived=%0d",datas,datar),UVM_NONE);
phase.drop_objection(this);
endtask
endclass

class consumer extends uvm_component;

`uvm_component_utils(consumer);

int datas=45;
int datar=0;
uvm_blocking_transport_imp#(int,int,consumer) cons1;

function new (string path="consumer",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
cons1=new("cons1",this);
endfunction

virtual task transport(input int datar,output int datas); /// ethe producer and consumer cha data name same aasla pahije
datas=this.datas;
`uvm_info("cons",$sformatf(" value of data send =%0d and received data =%0d",datas,datar),UVM_NONE);
endtask // first recived data la input consider kela aahe ethe manun datar la first lihale aahe
endclass

class env extends uvm_env;

`uvm_component_utils(env);

producer p1;
consumer c1;

function new(string path="env",uvm_component parent =null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
p1=producer::type_id::create("p1",this);
c1=consumer::type_id::create("c1",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
p1.prod1.connect(c1.cons1);
endfunction

7] TLM =IMP Page 278

endclass

class test extends uvm_test;

`uvm_component_utils(test);
env e;

function new(string path="test",uvm_component parent =null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
endfunction

endclass

module tb();

initial
begin
run_test("test");
end
endmodule

Output:

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(54) @ 0: uvm_test_top.e.c1 [cons] value of data send =45 and received data =30
UVM_INFO testbench.sv(27) @ 0: uvm_test_top.e.p1 [prod] value of data send=30 and data recived=45
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 4
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[UVM/RELNOTES] 1
[cons] 1
[prod] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.660 seconds; Data structure size: 0.1Mb
Tue Dec 27 08:54:15 2022
Done

From <https://www.edaplayground.com/>

9] Analysis Port

7] TLM =IMP Page 279

Uvm_analysis_port#(producer to consumer transfer data type) tlm class name;

Uvm_analysis_imp#(consumer to producer retrive data type, class name of consumer part) tlm class name;

7] TLM =IMP Page 280

1] TLM New
21 March 2023 18:21

1]
https://www.theartofverification.com/uvm-tlm-concepts/
Communication cha end point ha nehami implementation port aasto

Control flow ------> who initiate the transaction.

Data flow -------> how the data flow between two components

Put Port in TLM

Data flow and control flow direction is same here

7] TLM =IMP Page 281

7] TLM =IMP Page 282
1] Put Method (Port to Export)

Syntax of port in Put method

uvm_blocking_put_port #(type of data to be transferred ) class_name ;

Syntax of export in Put method

uvm_blocking_put_export #(type of data to be transferred ) class_name ;

Syntax of implementation in Put method

uvm_blocking_put_imp #(type of data to be transferred, class name where we received the
data ) class_name ;

7] TLM =IMP Page 283

Code :
import uvm_pkg::*;
`include "uvm_macros.svh";

class producer extends uvm_component;

`uvm_component_utils(producer);

int data=12;
uvm_blocking_put_port #(int) send;

function new(string path="producer",uvm_component parent=null);

super.new(path,parent);
send=new("send",this);
endfunction
endclass

class consumer extends uvm_component;

`uvm_component_utils(consumer);

uvm_blocking_put_export #(int) recv;

function new(string path="consumer",uvm_component parent=null);

super.new(path,parent);
recv=new("recv",this);
endfunction
endclass

class env extends uvm_env;

`uvm_component_utils(env);
consumer c1;
producer p1;
function new(string path="env",uvm_component parent=null);
super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
c1=consumer::type_id::create("c1",this);
p1=producer::type_id::create("p1",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
p1.send.connect(c1.recv);
endfunction
endclass

class test extends uvm_test;

`uvm_component_utils(test);

env e;
function new(string path="test",uvm_component parent=null);
super.new(path,parent);
endfunction

7] TLM =IMP Page 284

 endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
endfunction

endclass

module tb();

initial
begin
run_test("test");
end
endmodule

Output:
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM]
QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM]
questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test test...
# UVM_ERROR @ 0: uvm_test_top.e.c1.recv [Connection Error] connection count of 0 does not meet required
minimum of 1
# UVM_ERROR @ 0: uvm_test_top.e.p1.send [Connection Error] connection count of 0 does not meet required
minimum of 1
# UVM_FATAL @ 0: reporter [BUILDERR] stopping due to build errors
# UVM_INFO verilog_src/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 4
# UVM_WARNING : 0
# UVM_ERROR : 2
# UVM_FATAL : 1
# ** Report counts by id
# [BUILDERR] 1
# [Connection Error] 2
# [Questa UVM] 2
# [RNTST] 1
# [UVM/RELNOTES] 1

Note:

1] Ethe aapan port and export ghetale aahe fkt. Kenva communication cha end point ha export
port nasto. Communication cha end point ha implemention port assto. Tymule varti error aale
aahe.

Aatta Aapan implementation Port Cha use karu

7] TLM =IMP Page 285

Aatta Aapan implementation Port Cha use karu

2] Put ( PORT --> EXPORT --> IMPLEMENTATION)

Code :
import uvm_pkg::*;
`include "uvm_macros.svh";

class producer extends uvm_component;

`uvm_component_utils(producer);

int data=12;
uvm_blocking_put_port #(int) send;

function new(string path="producer",uvm_component parent=null);

7] TLM =IMP Page 286

function new(string path="producer",uvm_component parent=null);
super.new(path,parent);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
send=new("send",this);
endfunction

task main_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("PROD",$sformatf("inside the main phase of producer value of data send =%0d",data),UVM_NONE);
send.put(data); // put method la introduce kele aahe data send karayela
phase.drop_objection(this);
endtask

endclass

class consumer extends uvm_component;

`uvm_component_utils(consumer);

uvm_blocking_put_export #(int) recv;

uvm_blocking_put_imp #(int,consumer) imprecv;

function new(string path="consumer",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
recv=new("recv",this);
imprecv=new("imprecv",this);
endfunction

function void put(int datar); // receiver side la collect karat aahe put ne
`uvm_info("cons",$sformatf("value of data received =%0d",datar),UVM_NONE);
endfunction

endclass

class env extends uvm_env;

`uvm_component_utils(env);
consumer c1;
producer p1;
function new(string path="env",uvm_component parent=null);
super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
c1=consumer::type_id::create("c1",this);
p1=producer::type_id::create("p1",this);
endfunction

7] TLM =IMP Page 287

 endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
p1.send.connect(c1.recv);
c1.recv.connect(c1.imprecv);
endfunction
endclass

class test extends uvm_test;

`uvm_component_utils(test);

env e;
function new(string path="test",uvm_component parent=null);
super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
endfunction

endclass

module tb();

initial
begin
run_test("test");
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(17) @ 0: uvm_test_top.e.p1 [PROD] inside the main phase of producer value of data
send =12
UVM_INFO testbench.sv(37) @ 0: uvm_test_top.e.c1 [cons] value of data received =12
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 4
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[PROD] 1

7] TLM =IMP Page 288

[PROD] 1
[RNTST] 1
[UVM/RELNOTES] 1
[cons] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.480 seconds; Data structure size: 0.1Mb
Thu Mar 23 09:00:24 2023

Note:
1] Ethe jenva aapan producer madhe put cha use karto. Tenva consumer side la function ne define karava lagto

3] Port - Port to IMP connection

Code :
import uvm_pkg::*;
`include "uvm_macros.svh";

class subproducer extends uvm_component;

`uvm_component_utils(subproducer);
int data =12;
uvm_blocking_put_port #(int) subpro;

function new(string path="subpro",uvm_component parent =null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
subpro=new("subpro",this);
endfunction

task main_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("PROD",$sformatf("inside the main phase of producer value of data send =%0d",data),UVM_NONE);
subpro.put(data);
phase.drop_objection(this);
endtask

endclass

//////////////////////////////////

7] TLM =IMP Page 289

class producer extends uvm_component;
`uvm_component_utils(producer);

subproducer sp;
uvm_blocking_put_port #(int) send;

function new(string path="producer",uvm_component parent=null);

super.new(path,parent);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
send=new("send",this);
sp=subproducer::type_id::create("sp",this);
endfunction

endclass

class consumer extends uvm_component;

`uvm_component_utils(consumer);

uvm_blocking_put_imp #(int,consumer) imprecv;

function new(string path="consumer",uvm_component parent=null);

super.new(path,parent);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

imprecv=new("imprecv",this);
endfunction

function void put(int datar);

`uvm_info("cons",$sformatf("value of data received =%0d",datar),UVM_NONE);
endfunction

endclass

class env extends uvm_env;

`uvm_component_utils(env);
consumer c1;
producer p1;
function new(string path="env",uvm_component parent=null);
super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

7] TLM =IMP Page 290

 super.build_phase(phase);
c1=consumer::type_id::create("c1",this);
p1=producer::type_id::create("p1",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
p1.sp.subpro.connect(p1.send);
p1.send.connect(c1.imprecv);
endfunction
endclass

class test extends uvm_test;

`uvm_component_utils(test);

env e;
function new(string path="test",uvm_component parent=null);
super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
endfunction

endclass

module tb();

initial
begin
run_test("test");
end
endmodule

Output:
UVM_INFO @ 0: reporter [RNTST] Running test test...
UVM_INFO testbench.sv(21) @ 0: uvm_test_top.e.p1.sp [PROD] inside the main phase of producer value of data
send =12
UVM_INFO testbench.sv(71) @ 0: uvm_test_top.e.c1 [cons] value of data received =12
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 4
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[PROD] 1
[RNTST] 1
[UVM/RELNOTES] 1
[cons] 1

7] TLM =IMP Page 291

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.
$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.480 seconds; Data structure size: 0.1Mb
Thu Mar 23 09:47:27 2023

Same logic subconsumer side la pan lavava

2] Get Port
Put Port is send transition from producer ---------------> consumer

Get port is used to retrive the data from consumer producer <<------------------ consumer

Get method madhe aapan producer pasun request send hote pan ya time la consumer kadhun data ghyecha aasto tymule
aapan get cha use kela jaato

7] TLM =IMP Page 292

Code :

`include "uvm_macros.svh";
import uvm_pkg::*;

class producer extends uvm_component;

`uvm_component_utils(producer);

int data1=0;
uvm_blocking_get_port#(int) prod1;

function new(string path="producer",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
prod1=new("prod1",this);
endfunction

task main_phase(uvm_phase phase);

phase.raise_objection(this);
`uvm_info("producer",$sformatf(" value of beforedata recived=%0d",data1),UVM_NONE);
prod1.get(data1);
`uvm_info("producer",$sformatf(" value of after edata recived=%0d",data1),UVM_NONE);
phase.drop_objection(this);
endtask
endclass

class consumer extends uvm_component;

`uvm_component_utils(consumer);

int data2=30;

uvm_blocking_get_imp#(int,consumer) cons1;

function new(string path="consumer",uvm_component parent=null);

super.new(path,parent);
endfunction

7] TLM =IMP Page 293

 endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
cons1=new("cons1",this);
endfunction

task get(output int data);

data=data2;
`uvm_info("consumer",$sformatf("value of data send =%0d",data2),UVM_NONE);
endtask
endclass

class env extends uvm_env;

`uvm_component_utils(env);

consumer c1;
producer p1;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
p1=producer::type_id::create("p1",this);
c1=consumer::type_id::create("c1",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
p1.prod1.connect(c1.cons1);
endfunction

endclass

class test extends uvm_test;

`uvm_component_utils(test);
env e;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
endfunction

endclass

module tb();

initial
begin

7] TLM =IMP Page 294

 begin
run_test("test");
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(21) @ 0: uvm_test_top.e.p1 [producer] value of beforedata recived=0
UVM_INFO testbench.sv(47) @ 0: uvm_test_top.e.c1 [consumer] value of data send=30
UVM_INFO testbench.sv(23) @ 0: uvm_test_top.e.p1 [producer] value of after edata recived=30
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 5
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[UVM/RELNOTES] 1
[consumer] 1
[producer] 2

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.440 seconds; Data structure size: 0.1Mb
Mon Dec 26 12:44:57 2022
Done

7] TLM =IMP Page 295

2] TLM Analysis interface
19 April 2023 11:20

A] TLM analysis port

1] The uvm_analysis_port is a TLM-based class that provides a write method for communication. TLM analysis port
broadcasts transactions to one or multiple components.
2] uvm_analysis_port can be open without any implementation of uvm_analysis_imp or uvm_analysis_export.
3] Single uvm_analysis_port can have a connection with uvm_analysis_imp or uvm_analysis_export. No errors will be
reported.
4] Multiple uvm_analysis_port can be connected to a single uvm_analysis_imp or uvm_analysis_export.
5] uvm_subscriber already has analysis_export so that it can directly receive transactions from the connected analysis
port. Generally, it is useful to write a coverage collector that attaches to the monitor.

Valid Connections:
a. port to port
b. port to export
c. port to imp
d. export to export
e. export to imp

A] uvm_analysis_port example

7] TLM =IMP Page 296

Uvm_analysis_port#(producer to consumer transfer data type) tlm class name;
Example : uvm_analysis_port #(transaction) analysis_port;

Uvm_analysis_export#( consumer to producer retrive data type ) tlm class name;

Example : uvm_analysis_export #(transaction) analysis_export;

Uvm_analysis_imp#(consumer to producer retrive data type, class name of consumer part) tlm class name;
Example : uvm_analysis_imp #(transaction,consumer) analysis_imp;

Code :

7] TLM =IMP Page 297

`include "uvm_macros.svh"
import uvm_pkg::*;

class transaction extends uvm_sequence_item;

`uvm_object_utils(transaction)
rand bit [3:0] addr;

function new(string name = "transaction");

super.new(name);
endfunction

constraint val_c {addr > 0;}

endclass

//////// First Producer cha code ///////////

class producer extends uvm_component;

`uvm_component_utils(producer);
transaction trans;
uvm_analysis_port #(transaction) analysis_port;
function new(string path="producer",uvm_component parent=null);
super.new(path,parent);
analysis_port=new("port1",this);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
trans=transaction::type_id::create("trans",this);
endfunction

virtual task run_phase(uvm_phase phase);

super.run_phase(phase);
trans.randomize();
`uvm_info(get_type_name,$sformatf("send value of addr=%0d",trans.addr),UVM_NONE);
analysis_port.write(trans);
endtask
endclass:producer

class consumer extends uvm_component;

`uvm_component_utils(consumer);
transaction trans;
uvm_analysis_imp #(transaction,consumer) analysis_imp;
function new(string path="consumer",uvm_component parent=null);
super.new(path,parent);
analysis_imp=new("imp1",this);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
trans=transaction::type_id::create("trans",this);

7] TLM =IMP Page 298

endfunction

virtual function void write(transaction trans);

`uvm_info(get_type_name,$sformatf("received value of addr=%0d",trans.addr),UVM_NONE);
endfunction

endclass

class consumer1 extends uvm_component;

`uvm_component_utils(consumer1);
transaction trans;
uvm_analysis_imp #(transaction,consumer1) analysis_imp1;

function new(string path="consumer1",uvm_component parent=null);

super.new(path,parent);
analysis_imp1=new("imp1",this);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
trans=transaction::type_id::create("trans",this);
endfunction

virtual function void write(transaction trans);

`uvm_info(get_type_name,$sformatf("received value of addr=%0d",trans.addr),UVM_NONE);
endfunction

endclass

class env extends uvm_env;

`uvm_component_utils(env)
producer p;
consumer c;
consumer1 c1;
function new(string path="env",uvm_component parent=null);
super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
p=producer::type_id::create("p",this);
c1=consumer1::type_id::create("1c",this);
c=consumer::type_id::create("c",this);

endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
p.analysis_port.connect(c.analysis_imp);
p.analysis_port.connect(c1.analysis_imp1);
endfunction
endclass

7] TLM =IMP Page 299

class test extends uvm_test;
env e;
`uvm_component_utils(test)

function new(string name = "test", uvm_component parent = null);

super.new(name, parent);
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
e = env::type_id::create("e", this);
endfunction

task run_phase(uvm_phase phase);

phase.raise_objection(this);
#50;
phase.drop_objection(this);
endtask
endclass

module tb_top;
initial begin
run_test("test");
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(35) @ 0: uvm_test_top.e.p [producer] send value of addr=3
UVM_INFO testbench.sv(79) @ 0: uvm_test_top.e.1c [consumer1] received value of addr=3
UVM_INFO testbench.sv(57) @ 0: uvm_test_top.e.c [consumer] received value of addr=3
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_objection.svh(1276) @ 50: reporter
[TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 50: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 6
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[TEST_DONE] 1
[UVM/RELNOTES] 1
[consumer] 1

7] TLM =IMP Page 300

[consumer] 1
[consumer1] 1
[producer] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 50
VCS Simulation Report
Time: 50 ns
CPU Time: 0.640 seconds; Data structure size: 0.2Mb
Wed Apr 19 12:26:59 2023

Some Changes :

Code :
`include "uvm_macros.svh"
import uvm_pkg::*;

7] TLM =IMP Page 301

class transaction extends uvm_sequence_item;
`uvm_object_utils(transaction)
rand bit [3:0] addr;

function new(string name = "transaction");

super.new(name);
endfunction

constraint val_c {addr > 0;}

endclass

class producer extends uvm_component;

`uvm_component_utils(producer);
transaction trans;
uvm_analysis_port #(transaction) analysis_port;

function new(string path="producer",uvm_component parent=null);

super.new(path,parent);
analysis_port=new("port1",this); // allocation of memory
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
trans=transaction::type_id::create("trans",this);

endfunction

virtual task run_phase(uvm_phase phase);

super.run_phase(phase);
trans.randomize();
`uvm_info(get_type_name,$sformatf("send value of addr=%0d",trans.addr),UVM_NONE);
analysis_port.write(trans);
endtask
endclass:producer

class consumer extends uvm_component;

`uvm_component_utils(consumer);
transaction trans;
uvm_analysis_export #(transaction) analysis_imp;
function new(string path="consumer",uvm_component parent=null);
super.new(path,parent);
analysis_imp=new("imp1",this);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
trans=transaction::type_id::create("trans",this);

endfunction

/* no need to write the code for write method because we use the export port. Write method need to write in
implementation part
virtual function void write(transaction trans);

7] TLM =IMP Page 302

virtual function void write(transaction trans);
`uvm_info(get_type_name,$sformatf("received value of addr=%0d",trans.addr),UVM_NONE);
endfunction */

endclass

class consumer1 extends uvm_component;

`uvm_component_utils(consumer1);
transaction trans;
uvm_analysis_imp #(transaction,consumer1) analysis_imp1;
function new(string path="consumer1",uvm_component parent=null);
super.new(path,parent);
analysis_imp1=new("imp1",this);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
trans=transaction::type_id::create("trans",this);

endfunction

virtual function void write(transaction trans);

`uvm_info(get_type_name,$sformatf("received value of addr=%0d",trans.addr),UVM_NONE);
endfunction

endclass

class env extends uvm_env;

`uvm_component_utils(env)
producer p;
consumer c;
consumer1 c1;
function new(string path="env",uvm_component parent=null);
super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
p=producer::type_id::create("p",this);
c=consumer::type_id::create("c",this);
c1=consumer1::type_id::create("c1",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
p.analysis_port.connect(c.analysis_imp);
c.analysis_imp.connect(c1.analysis_imp1);
endfunction
endclass

class test extends uvm_test;

env e;
`uvm_component_utils(test)

7] TLM =IMP Page 303

 `uvm_component_utils(test)

function new(string name = "test", uvm_component parent = null);

super.new(name, parent);
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
e = env::type_id::create("e", this);
endfunction

task run_phase(uvm_phase phase);

phase.raise_objection(this);
#50;
phase.drop_objection(this);
endtask
endclass

module tb_top;
initial begin
run_test("test");
end
Endmodule

# You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM]
QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(216) @ 0: reporter [Questa UVM]
questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test test...
# UVM_INFO first.sv(25) @ 0: uvm_test_top.e.p [producer] send value of addr=8
# UVM_INFO first.sv(69) @ 0: uvm_test_top.e.c1 [consumer1] received value of addr=8
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1267) @ 50: reporter [TEST_DONE] 'run' phase is
ready to proceed to the 'extract' phase
#
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 6
# UVM_WARNING : 0
# UVM_ERROR : 0
# UVM_FATAL : 0
# ** Report counts by id
# [Questa UVM] 2
# [RNTST] 1
# [TEST_DONE] 1
# [consumer1] 1
# [producer] 1
# ** Note: $finish : C:/questasim64_10.7c/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430)
# Time: 50 ns Iteration: 54 Instance: /tb_top
#1

7] TLM =IMP Page 304

#1
# Break in Task uvm_pkg/uvm_root::run_test at C:/questasim64_
10.7c/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh line 430
# quit -sim
# End time: 22:10:49 on Apr 19,2023, Elapsed time: 0:01:05
# Errors: 0, Warnings: 0

Difference Between Put TLM Port and Analysis TLM Port.

1] Put and Get method in TLM Port

7] TLM =IMP Page 305

2] TLM Analysis Port

7] TLM =IMP Page 306

7] TLM =IMP Page 307
 3] TLM FIFO
02 June 2023 01:46

1] The TLM FIFO provides storage for the transactions between two independently running processes. We have seen
put and get methods to operate with only one outstanding transaction at a time i.e it is allowed to send the
transaction Only after consumption of the previously sent transaction, in this case, the sender and receiver must be
in sync else lead to blocking in one of the components. What if the case where the sender needs not wait for the
receiver acknowledgment, it just wants to store it in memory and the receiver can consume it whenever required.
Thus, sender and receiver needs not to be in sync. TLM FIFO makes it possible.

2] As we have seen in blocking methods, producers need to wait for acknowledgment from the consumer to send
the next item.

3] What if the producer is not a testbench component? Consider an example where DUT is sent information packets
through some protocol and TB can take more time to operate on that packet. So, there can be chances that DUT can
send multiple packets in the meantime. TLM FIFO stores such incoming transaction from DUT and testbench can
operate independently

Types of TLM FIFO

1. uvm_tlm_fifo
2. uvm_tlm_analysis_fifo

From <https://vlsiverify.com/uvm/tlm/tlm-fifo>

More Information
https://vlsiverify.com/uvm/tlm/tlm-fifo?expand_article=1

7] TLM =IMP Page 308

8] Sequence == need to learn more in practical testbench
28 December 2022 12:12

1]

UVM_Sequence -----------> it is derived from UVM_OBJECT

UVM_Sequencer -----------> it is derived from UVM_COMPONENT

UVM Sequencer
The sequencer is a mediator who establishes a connection between sequence and driver. Ultimately, it passes
transactions or sequence items to the driver so that they can be driven to the DUT.

8] Sequence Page 309

A user-defined sequencer is recommended to extend from the parameterized base class “uvm_sequencer” which is
parameterized by request (REQ) and response (RSP) item types. Response item usage is optional. So, mostly sequencer class
is extended from a base class that has only a REQ item.

class my_sequencer extends uvm_sequencer #(data_item, data_rsp); // with rsp

class my_sequencer extends uvm_sequencer #(data_item); // without rsp

TLM (Transaction Level Modelling) interface is used by sequencer and driver to pass transactions. seq_item_export and
seq_item_port TLM connect methods are defined in uvm_sequencer and uvm_driver class.

Sequence-Driver-Sequencer communication in
UVM

8] Sequence Page 310

https://vlsiverify.com/uvm/sequence-driver-sequencer-communication-in-uvm

https://www.chipverify.com/uvm/uvm-using-get-next-item

Based on the varieties of methods available with sequence and driver, all combinations are explained further.
Approach A: Using get_next_item and item_done methods in the driver
Approach B: Using get and put methods in driver

1] Using get_next_item and item_done methods in the driver

Without RSP packet

8] Sequence Page 311

1. Create a sequence item and register in the factory using the create_item function call.

2. The wait_for_grant issues request to the sequencer and wait for the grant from the sequencer. It returns when
the sequencer has granted the sequence.
3. Randomize the sequence item and send it to the sequencer using send_request call. There should not be any
simulation time delay between wait_for_grant and send_request method call. The sequencer forwards the
sequence item to the driver with the help of REQ FIFO. This unblocks the get_next_item() call and the driver
receives the sequence item.
4. The wait_for_item_done() call from sequence gets blocked until the driver responds back.
5. In the meantime, the driver drives the sequence item to the DUT using a virtual interface handle. Once it is
completed, the item_done method is called. This unblocks the wait_for_item_done method from the sequence.
6. If a response has to be sent from the driver to the sequence, item_done(RSP) is called with the RSP item as an
argument. The RSP item is communicated to the sequence by a sequencer with help of RSP FIFO. It is
important to call the get_response method to get the response. This step is optional and not required if the RSP
item is not sent by the DUT.

Uvm_sequncer is component data type

Default sequencer in uvm library

uvm_sequencer #(transaction) seqr;

Code :

`include "uvm_macros.svh";
import uvm_pkg::*;

class transaction extends uvm_sequence_item;

rand bit [3:0] a;
rand bit [3:0] b;
bit [4:0] y;

function new(string path="transaction");

super.new(path);
endfunction

`uvm_object_utils_begin(transaction)
`uvm_field_int(a,UVM_DEFAULT)
`uvm_field_int(b,UVM_DEFAULT)
`uvm_field_int(y,UVM_DEFAULT)
`uvm_object_utils_end

endclass

class sequence1 extends uvm_sequence #(transaction);

`uvm_object_utils(sequence1);

function new(string path="sequence1");

super.new(path);
endfunction

virtual task pre_body();

`uvm_info("seq1","pre_body task executed",UVM_NONE);
endtask

8] Sequence Page 312

 endtask

virtual task body();

`uvm_info("seq1","body task executed",UVM_NONE);
endtask

virtual task post_body();

`uvm_info("seq1","post_body task executed",UVM_NONE);
endtask

endclass

class driver extends uvm_driver#(transaction);

`uvm_component_utils(driver)
transaction t;

function new(string path="driver",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
t=transaction::type_id::create("t");
endfunction

virtual task run_phase(uvm_phase phase);

forever
begin
seq_item_port.get_next_item(t);
seq_item_port.item_done();
end
endtask
endclass

class agent extends uvm_agent;

`uvm_component_utils(agent);
driver d1;
uvm_sequencer #(transaction) seqr;

function new(string path="agent",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
d1=driver::type_id::create("d1",this);
seqr=uvm_sequencer #(transaction)::type_id::create("seqr",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
d1.seq_item_port.connect(seqr.seq_item_export);
endfunction
endclass

class env extends uvm_env;

`uvm_component_utils(env);
agent a1;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);

8] Sequence Page 313

 super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a1=agent::type_id::create("a",this);
endfunction

endclass

class test extends uvm_test;

`uvm_component_utils(test);

env e;
sequence1 seq1;

function new(string path="test",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
seq1=sequence1::type_id::create("seq1");
endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);
seq1.start(e.a1.seqr);
phase.drop_objection(this);
endtask

endclass

module tb();

initial
begin
run_test("test");
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(32) @ 0: uvm_test_top.e.a.seqr@@seq1 [seq1] pre_body task executed
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.seqr@@seq1 [seq1] body task executed
UVM_INFO testbench.sv(40) @ 0: uvm_test_top.e.a.seqr@@seq1 [seq1] post_body task executed
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_objection.svh(1276) @ 0: reporter [TEST_DONE] 'run' phase is ready
to proceed to the 'extract' phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 6
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[TEST_DONE] 1

8] Sequence Page 314

[TEST_DONE] 1
[UVM/RELNOTES] 1
[seq1] 3

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.560 seconds; Data structure size: 0.2Mb
Mon Jan 2 12:36:43 2023

3] Sending data to sequencer (IMP)

jenva aapan sequencer start hoto tenva che task body madhla code execute hoto.

Code :

`include "uvm_macros.svh";
import uvm_pkg::*;

class transaction extends uvm_sequence_item;

rand bit [3:0] a;

rand bit [3:0] b;
bit [4:0] y;

`uvm_object_utils_begin(transaction)
`uvm_field_int(a,UVM_DEFAULT)
`uvm_field_int(b,UVM_DEFAULT)
`uvm_field_int(y,UVM_DEFAULT)
`uvm_object_utils_end

function new(string path="transaction");

super.new(path);
endfunction
endclass

class sequence1 extends uvm_sequence; // ethe aapan uvm_phase cha use nahi karat karan ha UVM_object pasun derived
zale la aahe.
`uvm_object_utils(sequence1);
transaction trans;

function new(string path="sequence1");

super.new(path);
endfunction

8] Sequence Page 315

 virtual task body();
repeat(10)
begin
`uvm_do(trans);
`uvm_info("SEQ",$sformatf("value of send data a=%0d and b=%0d",trans.a,trans.b),UVM_NONE);
end
endtask
endclass

class driver extends uvm_driver#(transaction);

`uvm_component_utils(driver);
transaction trans;

function new(string path="driver",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
trans=transaction::type_id::create("trans",this);
endfunction

virtual task run_phase(uvm_phase phase);

forever
begin
seq_item_port.get_next_item(trans);
`uvm_info("drv",$sformatf(" value of recived data a=%0d and b=%0d",trans.a,trans.b),UVM_NONE);
seq_item_port.item_done();
end
endtask
endclass

class agent extends uvm_agent;

`uvm_component_utils(agent);

driver d;
uvm_sequencer#(transaction) vishal;

function new(string path="agent",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
d=driver::type_id::create("d",this);
vishal=uvm_sequencer#(transaction)::type_id::create("seqr",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
d.seq_item_port.connect(vishal.seq_item_export);
endfunction
endclass

class env extends uvm_env;

8] Sequence Page 316

class env extends uvm_env;
`uvm_component_utils(env);
agent a;
sequence1 seq1;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a=agent::type_id::create("a",this);
seq1=sequence1::type_id::create("seq1",this);
endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);
seq1.start(a.vishal); // start ha function sequence la start karnyasaathi aasto
// uvm_sequence cha handler.start( uvm_sequencer jo aahe define class aahe tycha path.
phase.drop_objection(this);
endtask
endclass

class test extends uvm_test;

`uvm_component_utils(test);
env e;

function new(string path="test",uvm_component parent =null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
endfunction
endclass

module tb();

initial
begin
run_test("test");
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(61) @ 0: uvm_test_top.e.a.d [drv] value of recived data a=1 and b=6
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.seqr@@seq1 [SEQ] value of send data a=1 and b=6
UVM_INFO testbench.sv(61) @ 0: uvm_test_top.e.a.d [drv] value of recived data a=11 and b=5
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.seqr@@seq1 [SEQ] value of send data a=11 and b=5
UVM_INFO testbench.sv(61) @ 0: uvm_test_top.e.a.d [drv] value of recived data a=10 and b=9
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.seqr@@seq1 [SEQ] value of send data a=10 and b=9
UVM_INFO testbench.sv(61) @ 0: uvm_test_top.e.a.d [drv] value of recived data a=6 and b=5
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.seqr@@seq1 [SEQ] value of send data a=6 and b=5
UVM_INFO testbench.sv(61) @ 0: uvm_test_top.e.a.d [drv] value of recived data a=9 and b=4

8] Sequence Page 317

UVM_INFO testbench.sv(61) @ 0: uvm_test_top.e.a.d [drv] value of recived data a=9 and b=4
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.seqr@@seq1 [SEQ] value of send data a=9 and b=4
UVM_INFO testbench.sv(61) @ 0: uvm_test_top.e.a.d [drv] value of recived data a=8 and b=15
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.seqr@@seq1 [SEQ] value of send data a=8 and b=15
UVM_INFO testbench.sv(61) @ 0: uvm_test_top.e.a.d [drv] value of recived data a=7 and b=3
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.seqr@@seq1 [SEQ] value of send data a=7 and b=3
UVM_INFO testbench.sv(61) @ 0: uvm_test_top.e.a.d [drv] value of recived data a=0 and b=0
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.seqr@@seq1 [SEQ] value of send data a=0 and b=0
UVM_INFO testbench.sv(61) @ 0: uvm_test_top.e.a.d [drv] value of recived data a=0 and b=14
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.seqr@@seq1 [SEQ] value of send data a=0 and b=14
UVM_INFO testbench.sv(61) @ 0: uvm_test_top.e.a.d [drv] value of recived data a=6 and b=10
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.seqr@@seq1 [SEQ] value of send data a=6 and b=10
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_objection.svh(1276) @ 0: reporter [TEST_DONE] 'run' phase is ready
to proceed to the 'extract' phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 23
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[SEQ] 10
[TEST_DONE] 1
[UVM/RELNOTES] 1
[drv] 10

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.500 seconds; Data structure size: 0.2Mb
Tue Jan 3 04:51:42 2023

1] uvm_sequence macros

1.1] UVM_DO

Syntax:
`uvm_do (uvm_sequence handle/uvm_sequence_item handle)

Generally we use the below steps in sequence class

Communication between the Sequence and driver involves below steps,

1.create_item() / create req.
2.wait_for_grant().
3.randomize the req.
4.send the req.
5.wait for item done.
6.get response.

This macro takes seq_item or sequence as argument. On calling `uvm_do() the above-defined 6 steps will be executed. On
calling this macro, create, randomize and send to the driver will be executed

Example :

class transaction extends uvm_sequence_item;

rand bit [3:0] a;

rand bit [3:0] b;
bit [4:0] y;

`uvm_object_utils_begin(transaction)
`uvm_field_int(a,UVM_DEFAULT)

8] Sequence Page 318

 `uvm_field_int(a,UVM_DEFAULT)
`uvm_field_int(b,UVM_DEFAULT)
`uvm_field_int(y,UVM_DEFAULT)
`uvm_object_utils_end

function new(string path="transaction");

super.new(path);
endfunction
endclass

class sequence1 extends uvm_sequence;

`uvm_object_utils(sequence1);
transaction trans;

function new(string path="sequence1");

super.new(path);
endfunction

virtual task body();

repeat(10)
begin
`uvm_do(trans);
`uvm_info("SEQ",$sformatf("value of send data a=%0d and b=%0d",trans.a,trans.b),UVM_NONE);
end
endtask
endclass

4] Start finish item method in uvm sequence data send

to driver

First method madhe aapan jo data randomized kela aahe tymadhe aapan changes nahi karu shakat.

Second method madhe aapan jo data randomized kela aahe tyla aapan change karu shakto.

8] Sequence Page 319

Third method madhe aapan khoop long way data transfer kele jaato

Code for send method

`include "uvm_macros.svh";
import uvm_pkg::*;

class transaction extends uvm_sequence_item;

rand bit [3:0] a;

rand bit [3:0] b;
bit [4:0] y;

`uvm_object_utils_begin(transaction)
`uvm_field_int(a,UVM_DEFAULT)
`uvm_field_int(b,UVM_DEFAULT)
`uvm_field_int(y,UVM_DEFAULT)
`uvm_object_utils_end

function new(string path="transaction");

super.new(path);
endfunction
endclass

class sequence1 extends uvm_sequence; // ethe aapan uvm_phase cha use nahi karat karan ha UVM_object pasun derived
zale la aahe.
`uvm_object_utils(sequence1);
transaction trans;

function new(string path="sequence1");

super.new(path);
endfunction

virtual task body();

repeat(2)
begin
trans=transaction::type_id::create("trans"); // create kela item
start_item(trans); // start method cha use
assert(trans.randomize); //randomize data la change karu shakto
finish_item(trans); //finish method cha use kela
`uvm_info("SEQ",$sformatf("value of send using start and finish method data a=%0d and b=%
0d",trans.a,trans.b),UVM_NONE);
end
endtask
endclass

class driver extends uvm_driver#(transaction);

`uvm_component_utils(driver);
transaction trans;

function new(string path="driver",uvm_component parent=null);

super.new(path,parent);
endfunction

8] Sequence Page 320

 virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
trans=transaction::type_id::create("trans",this);
endfunction

virtual task run_phase(uvm_phase phase);

forever
begin
seq_item_port.get_next_item(trans);
`uvm_info("drv",$sformatf(" value of recived in start and finish method data a=%0d and b=%
0d",trans.a,trans.b),UVM_NONE);
seq_item_port.item_done();
end
endtask
endclass

class agent extends uvm_agent;

`uvm_component_utils(agent);

driver d;
uvm_sequencer#(transaction) vishal;

function new(string path="agent",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
d=driver::type_id::create("d",this);
vishal=uvm_sequencer#(transaction)::type_id::create("seqr",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
d.seq_item_port.connect(vishal.seq_item_export);
endfunction
endclass

class env extends uvm_env;

`uvm_component_utils(env);
agent a;
sequence1 seq1;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a=agent::type_id::create("a",this);
seq1=sequence1::type_id::create("seq1",this);
endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);
seq1.start(a.vishal); // start ha function sequence la start karnyasaathi aasto
// uvm_sequence cha handler.start( uvm_sequencer jo aahe define class aahe tycha path.

8] Sequence Page 321

 // uvm_sequence cha handler.start( uvm_sequencer jo aahe define class aahe tycha path.
phase.drop_objection(this);
endtask
endclass

class test extends uvm_test;

`uvm_component_utils(test);
env e;

function new(string path="test",uvm_component parent =null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
endfunction
endclass

module tb();

initial
begin
run_test("test");
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(64) @ 0: uvm_test_top.e.a.d [drv] value of recived in start and finish method data a=15 and b=10
UVM_INFO testbench.sv(39) @ 0: uvm_test_top.e.a.seqr@@seq1 [SEQ] value of send using start and finish method data a=15 and b= 10
UVM_INFO testbench.sv(64) @ 0: uvm_test_top.e.a.d [drv] value of recived in start and finish method data a=1 and b=6
UVM_INFO testbench.sv(39) @ 0: uvm_test_top.e.a.seqr@@seq1 [SEQ] value of send using start and finish method data a=1 and b=6
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_objection.svh(1276) @ 0: reporter [TEST_DONE] 'run' phase is ready
to proceed to the 'extract' phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 7
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[SEQ] 2
[TEST_DONE] 1
[UVM/RELNOTES] 1
[drv] 2

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.500 seconds; Data structure size: 0.2Mb
Tue Jan 3 08:40:16 2023

5] Sequence Arbitration in UVM(run multiple sequence

8] Sequence Page 322
5] Sequence Arbitration in UVM(run multiple sequence
parallely

Default Sequence arbitration ( FIFO)

Code:
`include "uvm_macros.svh";
import uvm_pkg::*;

class transaction extends uvm_sequence_item;

rand bit [3:0] a;

rand bit [3:0] b;
bit [4:0] y;

`uvm_object_utils_begin(transaction)
`uvm_field_int(a,UVM_DEFAULT)
`uvm_field_int(b,UVM_DEFAULT)
`uvm_field_int(y,UVM_DEFAULT)
`uvm_object_utils_end

function new(string path="transaction");

super.new(path);
endfunction
endclass

class sequence1 extends uvm_sequence;

`uvm_object_utils(sequence1);
transaction trans;

function new(string path="sequence1");

super.new(path);
endfunction

virtual task body();

repeat(2)
begin

8] Sequence Page 323

 trans=transaction::type_id::create("trans");
`uvm_info("SEQ1","SEQ1 start",UVM_NONE);
start_item(trans);
assert(trans.randomize);
finish_item(trans);
`uvm_info("SEQ1","SEQ1 end",UVM_NONE);
end
endtask
endclass

class sequence2 extends uvm_sequence;

`uvm_object_utils(sequence2);
transaction trans;

function new(string path=-"sequence2");

super.new(path);
endfunction

virtual task body();

repeat(2)
begin
trans=transaction::type_id::create("trans");
`uvm_info("SEQ2","SEQ2 start",UVM_NONE);
start_item(trans);
trans.randomize();
finish_item(trans);
`uvm_info("SEQ2","SEQ2 end",UVM_NONE);
end
endtask
endclass

class driver extends uvm_driver#(transaction);

`uvm_component_utils(driver);
transaction trans;

function new(string path="driver",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
trans=transaction::type_id::create("trans",this);
endfunction

virtual task run_phase(uvm_phase phase);

forever
begin
seq_item_port.get_next_item(trans);
//`uvm_info("drv",$sformatf(" value of recived data a=%0d and b=%0d",trans.a,trans.b),UVM_NONE);
seq_item_port.item_done();
end
endtask
endclass

class agent extends uvm_agent;

`uvm_component_utils(agent);

8] Sequence Page 324

 driver d;
uvm_sequencer#(transaction) sequencerhandle;

function new(string path="agent",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
d=driver::type_id::create("d",this);
sequencerhandle=uvm_sequencer#(transaction)::type_id::create("sequencerhandle",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
d.seq_item_port.connect(sequencerhandle.seq_item_export);
endfunction
endclass

class env extends uvm_env;

`uvm_component_utils(env);
agent a;
sequence1 seq1;
sequence2 seq2;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a=agent::type_id::create("a",this);

endfunction

endclass

class test extends uvm_test;

`uvm_component_utils(test);
env e;
sequence1 seq1;
sequence2 seq2;

function new(string path="test",uvm_component parent =null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
seq1=sequence1::type_id::create("seq1");
seq2=sequence2::type_id::create("seq2");
endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);

8] Sequence Page 325

 phase.raise_objection(this);
fork
seq1.start(e.a.sequencerhandle); // fork join cha use kela aahe
seq2.start(e.a.sequencerhandle);
join
phase.drop_objection(this);
endtask

endclass

module tb();

initial
begin
run_test("test");
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(40) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(62) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(40) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO testbench.sv(62) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_objection.svh(1276) @ 0: reporter [TEST_DONE] 'run' phase is ready
to proceed to the 'extract' phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 11
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[SEQ1] 4
[SEQ2] 4
[TEST_DONE] 1
[UVM/RELNOTES] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.500 seconds; Data structure size: 0.2Mb
Thu Jan 5 01:33:24 2023

Note:
1] Ethe seq1 and seq2 start ekdache hotat. Pan te parally execute hotat. First seq1 end hoto nanater seq2 end hoto. Ethe
FIFO sarkhe kaam chalte.

8] Sequence Page 326

Default Sequence arbitration ( FIFO)

2] set_arbitration(UVM_SEQ_ARB_WEIGHTED);

Code :

`include "uvm_macros.svh";
import uvm_pkg::*;

class transaction extends uvm_sequence_item;

rand bit [3:0] a;

rand bit [3:0] b;
bit [4:0] y;

`uvm_object_utils_begin(transaction)
`uvm_field_int(a,UVM_DEFAULT)
`uvm_field_int(b,UVM_DEFAULT)
`uvm_field_int(y,UVM_DEFAULT)
`uvm_object_utils_end

function new(string path="transaction");

super.new(path);
endfunction
endclass

class sequence1 extends uvm_sequence;

`uvm_object_utils(sequence1);
transaction trans;

function new(string path="sequence1");

super.new(path);
endfunction

virtual task body();

repeat(3)
begin

trans=transaction::type_id::create("trans");
`uvm_info("SEQ1","SEQ1 start",UVM_NONE);
start_item(trans);
assert(trans.randomize);
finish_item(trans);
`uvm_info("SEQ1","SEQ1 end",UVM_NONE);
end
endtask
endclass

class sequence2 extends uvm_sequence;

`uvm_object_utils(sequence2);
transaction trans;

function new(string path=-"sequence2");

8] Sequence Page 327

 function new(string path=-"sequence2");
super.new(path);
endfunction

virtual task body();

repeat(3)
begin
trans=transaction::type_id::create("trans");
`uvm_info("SEQ2","SEQ2 start",UVM_NONE);
start_item(trans);
trans.randomize();
finish_item(trans);
`uvm_info("SEQ2","SEQ2 end",UVM_NONE);
end
endtask
endclass

class driver extends uvm_driver#(transaction);

`uvm_component_utils(driver);
transaction trans;

function new(string path="driver",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
trans=transaction::type_id::create("trans",this);
endfunction

virtual task run_phase(uvm_phase phase);

forever
begin
seq_item_port.get_next_item(trans);
//`uvm_info("drv",$sformatf(" value of recived data a=%0d and b=%0d",trans.a,trans.b),UVM_NONE);
seq_item_port.item_done();
end
endtask
endclass

class agent extends uvm_agent;

`uvm_component_utils(agent);

driver d;
uvm_sequencer#(transaction) sequencerhandle;

function new(string path="agent",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
d=driver::type_id::create("d",this);
sequencerhandle=uvm_sequencer#(transaction)::type_id::create("sequencerhandle",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
d.seq_item_port.connect(sequencerhandle.seq_item_export);

8] Sequence Page 328

 d.seq_item_port.connect(sequencerhandle.seq_item_export);
endfunction
endclass

class env extends uvm_env;

`uvm_component_utils(env);
agent a;
sequence1 seq1;
sequence2 seq2;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a=agent::type_id::create("a",this);

endfunction

endclass

class test extends uvm_test;

`uvm_component_utils(test);
env e;
sequence1 seq1;
sequence2 seq2;

function new(string path="test",uvm_component parent =null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
seq1=sequence1::type_id::create("seq1");
seq2=sequence2::type_id::create("seq2");
endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);

e.a.sequencerhandle.set_arbitration(UVM_SEQ_ARB_WEIGHTED);
fork
seq1.start(e.a.sequencerhandle,null,100); ///(sequencer,parent sequence value, priority )
seq2.start(e.a.sequencerhandle,null,200);
join
phase.drop_objection(this);
endtask

endclass

module tb();

initial
begin

8] Sequence Page 329

 begin
run_test("test");
end
endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(62) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(40) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(40) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(62) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(40) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO testbench.sv(62) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_objection.svh(1276) @ 0: reporter [TEST_DONE] 'run' phase is ready
to proceed to the 'extract' phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 15
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[SEQ1] 6
[SEQ2] 6
[TEST_DONE] 1
[UVM/RELNOTES] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.520 seconds; Data structure size: 0.2Mb
Thu Jan 5 08:03:51 2023

Some changes:

1] Use of UVM_SEQ_ARB_RANDOM ethe randomly sequence end hoto.Weight la importance dile nahi det

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);

e.a.sequencerhandle.set_arbitration(UVM_SEQ_ARB_RANDOM);
fork
seq1.start(e.a.sequencerhandle,null,100); ///sequencer,parent sequence value, priority
seq2.start(e.a.sequencerhandle,null,200);
join
phase.drop_objection(this);
endtask

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

8] Sequence Page 330

 See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(40) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(40) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(62) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(40) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO testbench.sv(62) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(62) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_objection.svh(1276) @ 0: reporter [TEST_DONE] 'run' phase is ready
to proceed to the 'extract' phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 15
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[SEQ1] 6
[SEQ2] 6
[TEST_DONE] 1
[UVM/RELNOTES] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.760 seconds; Data structure size: 0.2Mb
Thu Jan 5 08:23:42 2023

2] use of UVM_SEQ_ARB_STRICT_FIFO. Ethe weighted la importance dile jaate

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);

e.a.sequencerhandle.set_arbitration(UVM_SEQ_ARB_STRICT_FIFO);
fork
seq1.start(e.a.sequencerhandle,null,100); ///sequencer,parent sequence value, priority
seq2.start(e.a.sequencerhandle,null,200);
join
phase.drop_objection(this);
endtask

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(62) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(62) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(62) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO testbench.sv(40) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(40) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start

8] Sequence Page 331

UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(40) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_objection.svh(1276) @ 0: reporter [TEST_DONE] 'run' phase is ready
to proceed to the 'extract' phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 15
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[SEQ1] 6
[SEQ2] 6
[TEST_DONE] 1
[UVM/RELNOTES] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.760 seconds; Data structure size: 0.2Mb
Thu Jan 5 08:25:43 2023

Note:
1] Ethe first weight la importance dile jaate. Jar weight same asel tar fifo method cha use kela jaato

2] use of UVM_SEQ_ARB_STRICT_RANDOM. Ethe weighted la importance dile jaate

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);

e.a.sequencerhandle.set_arbitration(UVM_SEQ_ARB_STRICT_RANDOM);
fork
seq1.start(e.a.sequencerhandle,null,100); ///sequencer,parent sequence value, priority
seq2.start(e.a.sequencerhandle,null,200);
join
phase.drop_objection(this);
endtask

Output:

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(62) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(62) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(62) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO testbench.sv(40) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(40) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(40) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_objection.svh(1276) @ 0: reporter [TEST_DONE] 'run' phase is ready
to proceed to the 'extract' phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

8] Sequence Page 332

** Report counts by severity
UVM_INFO : 15
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[SEQ1] 6
[SEQ2] 6
[TEST_DONE] 1
[UVM/RELNOTES] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.500 seconds; Data structure size: 0.2Mb
Thu Jan 5 08:33:00 2023

Note:
1] Ethe first weight la importance dile jaate. Jar weight same asel tar random method cha use kela jaato

9] Lock and Grab Methods in UVM sequencer

The UVM sequencer provides the facility to have exclusive access for the sequence to a driver via a sequencer using a
locking mechanism. This locking mechanism is implemented using lock and grab methods.

Example: In controller or microprocessor, internal core services interrupt handling along with other operations. Sometimes,
if a particular interrupt is raised by the device which needs immediate attention and stops ongoing process execution. Once
this high-priority interrupt is serviced by the core, the previous process can be resumed.

Lock method
On calling the lock method from a sequence, the sequencer will grant the sequence exclusive access to the
driver when the sequence gets the next available slot via a sequencer arbitration mechanism. Until the
sequence calls the unlock method, no other sequence will have access to the driver. On calling unlock method,

8] Sequence Page 333

sequence calls the unlock method, no other sequence will have access to the driver. On calling unlock method,
the lock will be released. The lock is a blocking method and returns once the lock has been granted.

Ethe : lock(m_sequencer) unlock(m_sequencer) -------->ethe jar m_sequencer sodun dusara konta pan variable
ghetala tar error yeto

Code :

`include "uvm_macros.svh";
import uvm_pkg::*;

class transaction extends uvm_sequence_item;

rand bit [3:0] a;

rand bit [3:0] b;
bit [4:0] y;

`uvm_object_utils_begin(transaction)
`uvm_field_int(a,UVM_DEFAULT)
`uvm_field_int(b,UVM_DEFAULT)
`uvm_field_int(y,UVM_DEFAULT)
`uvm_object_utils_end

function new(string path="transaction");

super.new(path);
endfunction
endclass

class sequence1 extends uvm_sequence;

`uvm_object_utils(sequence1);
transaction trans;

function new(string path="sequence1");

super.new(path);
endfunction

virtual task body();

lock(m_sequencer);
repeat(3)
begin

trans=transaction::type_id::create("trans");
`uvm_info("SEQ1","SEQ1 start",UVM_NONE);
start_item(trans);
assert(trans.randomize);
finish_item(trans);
`uvm_info("SEQ1","SEQ1 end",UVM_NONE);
end
unlock(m_sequencer);
endtask
endclass

class sequence2 extends uvm_sequence;

`uvm_object_utils(sequence2);
transaction trans;

function new(string path=-"sequence2");

super.new(path);
endfunction

8] Sequence Page 334

 endfunction

virtual task body();

lock(m_sequencer);
repeat(3)
begin
trans=transaction::type_id::create("trans");
`uvm_info("SEQ2","SEQ2 start",UVM_NONE);
start_item(trans);
trans.randomize();
finish_item(trans);
`uvm_info("SEQ2","SEQ2 end",UVM_NONE);
end
unlock(m_sequencer);
endtask
endclass

class driver extends uvm_driver#(transaction);

`uvm_component_utils(driver);
transaction trans;

function new(string path="driver",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
trans=transaction::type_id::create("trans",this);
endfunction

virtual task run_phase(uvm_phase phase);

forever
begin
seq_item_port.get_next_item(trans);
//`uvm_info("drv",$sformatf(" value of recived data a=%0d and b=%0d",trans.a,trans.b),UVM_NONE);
seq_item_port.item_done();
end
endtask
endclass

class agent extends uvm_agent;

`uvm_component_utils(agent);

driver d;
uvm_sequencer#(transaction) sequencerhandle;

function new(string path="agent",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
d=driver::type_id::create("d",this);
sequencerhandle=uvm_sequencer#(transaction)::type_id::create("sequencerhandle",this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
d.seq_item_port.connect(sequencerhandle.seq_item_export);

8] Sequence Page 335

 d.seq_item_port.connect(sequencerhandle.seq_item_export);
endfunction
endclass

class env extends uvm_env;

`uvm_component_utils(env);
agent a;
sequence1 seq1;
sequence2 seq2;

function new(string path="env",uvm_component parent=null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a=agent::type_id::create("a",this);

endfunction

endclass

class test extends uvm_test;

`uvm_component_utils(test);
env e;
sequence1 seq1;
sequence2 seq2;

function new(string path="test",uvm_component parent =null);

super.new(path,parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
seq1=sequence1::type_id::create("seq1");
seq2=sequence2::type_id::create("seq2");
endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);

fork
seq1.start(e.a.sequencerhandle,null,100); ///sequencer,parent sequence value, priority
seq2.start(e.a.sequencerhandle,null,200);
join
phase.drop_objection(this);
endtask

endclass

module tb();

initial
begin

8] Sequence Page 336

 begin
run_test("test");
end
endmodule

Output :

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(37) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(41) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO testbench.sv(37) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(41) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO testbench.sv(37) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 start
UVM_INFO testbench.sv(41) @ 0: uvm_test_top.e.a.sequencerhandle@@seq1 [SEQ1] SEQ1 end
UVM_INFO testbench.sv(61) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(65) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO testbench.sv(61) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(65) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO testbench.sv(61) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 start
UVM_INFO testbench.sv(65) @ 0: uvm_test_top.e.a.sequencerhandle@@seq2 [SEQ2] SEQ2 end
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_objection.svh(1276) @ 0: reporter [TEST_DONE] 'run' phase is ready
to proceed to the 'extract' phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 15
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[SEQ1] 6
[SEQ2] 6
[TEST_DONE] 1
[UVM/RELNOTES] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.560 seconds; Data structure size: 0.2Mb
Thu Jan 5 13:27:41 2023

Note: 1] lock kele ko toche ek sequence driver kadhe jaato

Some changes:
Ethe : lock(m_sequencer) unlock(m_sequencer) -------->ethe jar m_sequencer sodun dusara konta pan variable
ghetala tar error yeto

Code :

class sequence1 extends uvm_sequence;

`uvm_object_utils(sequence1);
transaction trans;

function new(string path="sequence1");

super.new(path);
endfunction

virtual task body();

lock(kshetry);
repeat(3)

8] Sequence Page 337

 repeat(3)
begin

trans=transaction::type_id::create("trans");
`uvm_info("SEQ1","SEQ1 start",UVM_NONE);
start_item(trans);
assert(trans.randomize);
finish_item(trans);
`uvm_info("SEQ1","SEQ1 end",UVM_NONE);
end
unlock(kshetry);
endtask
endclass

class sequence2 extends uvm_sequence;

`uvm_object_utils(sequence2);
transaction trans;

function new(string path=-"sequence2");

super.new(path);
endfunction

virtual task body();

lock(kshetry);
repeat(3)
begin
trans=transaction::type_id::create("trans");
`uvm_info("SEQ2","SEQ2 start",UVM_NONE);
start_item(trans);
trans.randomize();
finish_item(trans);
`uvm_info("SEQ2","SEQ2 end",UVM_NONE);
end
unlock(kshetry);
endtask
endclass

Output:

Top Level Modules:

tb
TimeScale is 1 ns / 1 ns

Error-[IND] Identifier not declared

testbench.sv, 32
Identifier 'kshetry' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.
Instance stack trace:
$unit /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/uvm.sv, 1

Error-[IND] Identifier not declared

testbench.sv, 43
Identifier 'kshetry' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.
Instance stack trace:
$unit /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/uvm.sv, 1

Error-[IND] Identifier not declared

testbench.sv, 57
Identifier 'kshetry' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.

8] Sequence Page 338

 expected, please check if you have set `default_nettype to none.
Instance stack trace:
$unit /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/uvm.sv, 1

Error-[IND] Identifier not declared

testbench.sv, 67
Identifier 'kshetry' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.
Instance stack trace:
$unit /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/uvm.sv, 1

4 errors
CPU time: 2.433 seconds to compile
Exit code expected: 0, received: 1
Done

class my_driver extends uvm_driver #(my_data); `uvm_component_utils (my_driver) virtual task run_phase(uvm_phase
phase); super.run_phase(phase); // 1. This task will get an item from the sequencer using get_next_item() `uvm_info
("DRIVER", $sformatf ("Waiting for data from sequencer"), UVM_MEDIUM) seq_item_port.get_next_item(req); // 2. For
simplicity, lets just assume the driver drives the received packet // during this time and consumes 20ns to complete driving
the transaction `uvm_info ("DRIVER", $sformatf ("Start driving tx addr=0x%0h data=0x%0h", req.addr, req.data), #20; // 3.
After driver has finished the transaction, it has to let the sequencer know // by calling item_done() `uvm_info ("DRIVER",
$sformatf ("Finish driving tx addr=0x%0h data=0x%0h", req.addr, req.data) seq_item_port.item_done(); endtask

8] Sequence Page 339

Sequence Updated
15 April 2023 13:03

1]

https://verificationguide.com/uvm/uvm-sequence/

Basic Diagram of sequence .multiple sequences are present in Testbench.

8] Sequence Page 340

UVM_Sequence -----------> it is derived from UVM_OBJECT

UVM_Sequencer -----------> it is derived from UVM_COMPONENT

UVM Sequencer
The sequencer is a mediator who establishes a connection between sequence and driver. Ultimately, it passes
transactions or sequence items to the driver so that they can be driven to the DUT.

A user-defined sequencer is recommended to extend from the parameterized base class “uvm_sequencer” which is
parameterized by request (REQ) and response (RSP) item types. Response item usage is optional. So, mostly
sequencer class is extended from a base class that has only a REQ item.

8] Sequence Page 341

class my_sequencer extends uvm_sequencer #(data_item, data_rsp); // with rsp
class my_sequencer extends uvm_sequencer #(data_item); // without rsp

TLM (Transaction Level Modelling) interface is used by sequencer and driver to pass transactions. seq_item_export
and seq_item_port TLM connect methods are defined in uvm_sequencer and uvm_driver class.

8] Sequence Page 342

To understand above transaction we need to analysis below code line by line.

4] Sequence -----------> Driver data send Three(3) Methods

1] First method madhe aapan jo data randomized kela aahe tymadhe aapan changes nahi karu shakat.

2] Second method madhe aapan jo data randomized kela aahe tyla aapan change karu shakto.

3] Third method madhe aapan khoop long way data transfer kele jaato

8] Sequence Page 343

3] Third method madhe aapan khoop long way data transfer kele jaato

Start_item(tr) is similar to wait_for_grant

Finish_item(tr) is similar to send_request

Second method madhe third method madhla wait_for_item_done ha remove kela aahe. Second method madhe
finish_item(tr) zale ki te tr ha data driver kadhe send kela jaato. Aata te next item saathi ready hoto.

1] First Method : `uvm_do Method

Code :
`include "uvm_macros.svh"
import uvm_pkg::*;
////////////////////////////////////////////

class transaction extends uvm_sequence_item;

rand bit [3:0] a;
rand bit [3:0] b;
bit [4:0] y;

function new(input string inst = "transaction");

super.new(inst);
endfunction

`uvm_object_utils_begin(transaction)
`uvm_field_int(a,UVM_DEFAULT)
`uvm_field_int(b,UVM_DEFAULT)
`uvm_field_int(y,UVM_DEFAULT)
`uvm_object_utils_end

endclass

////////////////////////////////////////////
class sequence1 extends uvm_sequence#(transaction);
`uvm_object_utils(sequence1)
transaction trans;

function new(string path = "sequence1");

super.new(path);
endfunction

virtual task body();

repeat(5) begin
`uvm_do(trans);
`uvm_info("SEQ", $sformatf("a : %0d b:%0d", trans.a, trans.b), UVM_NONE);
end
endtask
endclass
///////////////////////////////////////////////

8] Sequence Page 344

///////////////////////////////////////////////

class driver extends uvm_driver#(transaction);

`uvm_component_utils(driver)
transaction trans;

function new(input string inst = "DRV", uvm_component c);

super.new(inst,c);
endfunction

virtual task run_phase(uvm_phase phase);

trans = transaction::type_id::create("trans");
forever begin
seq_item_port.get_next_item(trans);
`uvm_info("DRV", $sformatf("a : %0d b:%0d", trans.a, trans.b), UVM_NONE);
seq_item_port.item_done();
end

endtask

endclass

//////////////////////////////////////////////////////

class agent extends uvm_agent;

`uvm_component_utils(agent)

uvm_sequencer#(transaction) seqr;
driver d;

function new(string path = "agent", uvm_component parent = null);

super.new(path, parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
d = driver::type_id::create("DRV",this);
seqr = uvm_sequencer#(transaction)::type_id::create("seqr", this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
d.seq_item_port.connect(seqr.seq_item_export);
endfunction

endclass

//////////////////////////////////////////////////////
//////////////////////running sequence with start method approach 1

class env extends uvm_env;

`uvm_component_utils(env)

agent a;
sequence1 s1;

function new(string path = "env", uvm_component parent = null);

8] Sequence Page 345

 function new(string path = "env", uvm_component parent = null);
super.new(path, parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a = agent::type_id::create("a", this);
s1= sequence1::type_id::create("s1");
endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);
s1.start(a.seqr);
phase.drop_objection(this);
endtask

endclass

///////////////////////////////////////////////

class test extends uvm_test;

`uvm_component_utils(test)

env e;

function new(string path = "test", uvm_component parent = null);

super.new(path, parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e = env::type_id::create("e", this);
endfunction

endclass

//////////////////////////////////////////////////////////////

module tb;

initial begin
run_test("test");
end

endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

8] Sequence Page 346

 See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(65) @ 0: uvm_test_top.e.a.DRV [DRV] a : 14 b:4
UVM_INFO testbench.sv(38) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ] a : 14 b:4
UVM_INFO testbench.sv(65) @ 0: uvm_test_top.e.a.DRV [DRV] a : 13 b:3
UVM_INFO testbench.sv(38) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ] a : 13 b:3
UVM_INFO testbench.sv(65) @ 0: uvm_test_top.e.a.DRV [DRV] a : 1 b:15
UVM_INFO testbench.sv(38) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ] a : 1 b:15
UVM_INFO testbench.sv(65) @ 0: uvm_test_top.e.a.DRV [DRV] a : 6 b:2
UVM_INFO testbench.sv(38) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ] a : 6 b:2
UVM_INFO testbench.sv(65) @ 0: uvm_test_top.e.a.DRV [DRV] a : 12 b:14
UVM_INFO testbench.sv(38) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ] a : 12 b:14
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_objection.svh(1276) @ 0: reporter [TEST_DONE]
'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 13
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[DRV] 5
[RNTST] 1
[SEQ] 5
[TEST_DONE] 1
[UVM/RELNOTES] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.580 seconds; Data structure size: 0.2Mb
Sat Apr 15 07:08:10 2023
Done

2] Second Method: start_item and finish_item

Code :
`include "uvm_macros.svh"
import uvm_pkg::*;
////////////////////////////////////////////

8] Sequence Page 347

class transaction extends uvm_sequence_item;
rand bit [3:0] a;
rand bit [3:0] b;
bit [4:0] y;

function new(input string inst = "transaction");

super.new(inst);
endfunction

`uvm_object_utils_begin(transaction)
`uvm_field_int(a,UVM_DEFAULT)
`uvm_field_int(b,UVM_DEFAULT)
`uvm_field_int(y,UVM_DEFAULT)
`uvm_object_utils_end

endclass

////////////////////////////////////////////
class sequence1 extends uvm_sequence#(transaction);
`uvm_object_utils(sequence1)
transaction trans;

function new(string path = "sequence1");

super.new(path);
endfunction

virtual task body();

repeat(5) begin
trans = transaction::type_id::create("trans");
start_item(trans);
assert(trans.randomize);
finish_item(trans);
`uvm_info("SEQ", $sformatf("a : %0d b:%0d", trans.a, trans.b), UVM_NONE);
end

endtask

endclass
///////////////////////////////////////////////

class driver extends uvm_driver#(transaction);

`uvm_component_utils(driver)
transaction trans;

function new(input string inst = "DRV", uvm_component c);

super.new(inst,c);
endfunction

virtual task run_phase(uvm_phase phase);

trans = transaction::type_id::create("trans");
forever begin

8] Sequence Page 348

 forever begin
seq_item_port.get_next_item(trans);
`uvm_info("DRV", $sformatf("a : %0d b:%0d", trans.a, trans.b), UVM_NONE);
seq_item_port.item_done();
end

endtask

endclass

//////////////////////////////////////////////////////

class agent extends uvm_agent;

`uvm_component_utils(agent)

uvm_sequencer#(transaction) seqr;
driver d;

function new(string path = "agent", uvm_component parent = null);

super.new(path, parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
d = driver::type_id::create("DRV",this);
seqr = uvm_sequencer#(transaction)::type_id::create("seqr", this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
d.seq_item_port.connect(seqr.seq_item_export);
endfunction

endclass

//////////////////////////////////////////////////////
//////////////////////running sequence with start method approach 1

class env extends uvm_env;

`uvm_component_utils(env)

agent a;
sequence1 s1;

function new(string path = "env", uvm_component parent = null);

super.new(path, parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a = agent::type_id::create("a", this);
s1= sequence1::type_id::create("s1");
endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);
s1.start(a.seqr);

8] Sequence Page 349

 s1.start(a.seqr);
phase.drop_objection(this);
endtask

endclass

///////////////////////////////////////////////

class test extends uvm_test;

`uvm_component_utils(test)

env e;

function new(string path = "test", uvm_component parent = null);

super.new(path, parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e = env::type_id::create("e", this);
endfunction

endclass

//////////////////////////////////////////////////////////////

module tb;

initial begin
run_test("test");
end

endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_NO_DEPRECATED undefined.
See http://www.eda.org/svdb/view.php?id=3313 for more details.

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(73) @ 0: uvm_test_top.e.a.DRV [DRV] a : 9 b:5
UVM_INFO testbench.sv(49) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ] a : 9 b:5
UVM_INFO testbench.sv(73) @ 0: uvm_test_top.e.a.DRV [DRV] a : 14 b:4
UVM_INFO testbench.sv(49) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ] a : 14 b:4

8] Sequence Page 350

UVM_INFO testbench.sv(49) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ] a : 14 b:4
UVM_INFO testbench.sv(73) @ 0: uvm_test_top.e.a.DRV [DRV] a : 8 b:12
UVM_INFO testbench.sv(49) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ] a : 8 b:12
UVM_INFO testbench.sv(73) @ 0: uvm_test_top.e.a.DRV [DRV] a : 13 b:3
UVM_INFO testbench.sv(49) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ] a : 13 b:3
UVM_INFO testbench.sv(73) @ 0: uvm_test_top.e.a.DRV [DRV] a : 5 b:6
UVM_INFO testbench.sv(49) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ] a : 5 b:6
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_objection.svh(1276) @ 0: reporter [TEST_DONE]
'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 13
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[DRV] 5
[RNTST] 1
[SEQ] 5
[TEST_DONE] 1
[UVM/RELNOTES] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.500 seconds; Data structure size: 0.2Mb
Sat Apr 15 07:05:49 2023
Done

3] Third Method : wait for grant

Code :
`include "uvm_macros.svh"
import uvm_pkg::*;
////////////////////////////////////////////

class transaction extends uvm_sequence_item;

rand bit [3:0] a;
rand bit [3:0] b;
bit [4:0] y;

function new(input string inst = "transaction");

super.new(inst);

8] Sequence Page 351

 super.new(inst);
endfunction

`uvm_object_utils_begin(transaction)
`uvm_field_int(a,UVM_DEFAULT)
`uvm_field_int(b,UVM_DEFAULT)
`uvm_field_int(y,UVM_DEFAULT)
`uvm_object_utils_end

endclass

////////////////////////////////////////////
class sequence1 extends uvm_sequence#(transaction);
`uvm_object_utils(sequence1)
transaction trans;

function new(string path = "sequence1");

super.new(path);
endfunction

virtual task body();

`uvm_info("SEQ1", "Trans obj Created" , UVM_NONE);

trans = transaction::type_id::create("trans");
`uvm_info("SEQ1", "Waiting for Grant from Driver" , UVM_NONE);
wait_for_grant();
`uvm_info("SEQ1", "Rcvd Grant..Randomizing Data" , UVM_NONE);
assert(trans.randomize());
`uvm_info("SEQ1", "Randomization Done -> Sent Req to Drv" , UVM_NONE);
send_request(trans);
`uvm_info("SEQ1", "Waiting for Item Done Resp from Driver" , UVM_NONE);
wait_for_item_done();
`uvm_info("SEQ1", "SEQ1 Ended" , UVM_NONE);
`uvm_info("SEQ", $sformatf("a : %0d b:%0d", trans.a, trans.b), UVM_NONE);
endtask

endclass
///////////////////////////////////////////////

class driver extends uvm_driver#(transaction);

`uvm_component_utils(driver)
transaction trans;

function new(input string inst = "DRV", uvm_component c);

super.new(inst,c);
endfunction

virtual task run_phase(uvm_phase phase);

trans = transaction::type_id::create("trans");
forever begin

8] Sequence Page 352

 forever begin
seq_item_port.get_next_item(trans);
`uvm_info("DRV", $sformatf("a : %0d b:%0d", trans.a, trans.b), UVM_NONE);
seq_item_port.item_done();
end

endtask

endclass

//////////////////////////////////////////////////////

class agent extends uvm_agent;

`uvm_component_utils(agent)

uvm_sequencer#(transaction) seqr;
driver d;

function new(string path = "agent", uvm_component parent = null);

super.new(path, parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
d = driver::type_id::create("DRV",this);
seqr = uvm_sequencer#(transaction)::type_id::create("seqr", this);
endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
d.seq_item_port.connect(seqr.seq_item_export);
endfunction

endclass

//////////////////////////////////////////////////////
//////////////////////running sequence with start method approach 1

class env extends uvm_env;

`uvm_component_utils(env)

agent a;
sequence1 s1;

function new(string path = "env", uvm_component parent = null);

super.new(path, parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
a = agent::type_id::create("a", this);
s1= sequence1::type_id::create("s1");
endfunction

virtual task run_phase(uvm_phase phase);

phase.raise_objection(this);
s1.start(a.seqr);

8] Sequence Page 353

 s1.start(a.seqr);
phase.drop_objection(this);
endtask

endclass

///////////////////////////////////////////////

class test extends uvm_test;

`uvm_component_utils(test)

env e;

function new(string path = "test", uvm_component parent = null);

super.new(path, parent);
endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);
e = env::type_id::create("e", this);
endfunction

endclass

//////////////////////////////////////////////////////////////

module tb;

initial begin
run_test("test");
end

endmodule

Output:
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test...

UVM_INFO testbench.sv(38) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ1] Trans obj Created
UVM_INFO testbench.sv(41) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ1] Waiting for Grant from Driver
UVM_INFO testbench.sv(43) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ1] Rcvd Grant..Randomizing Data
UVM_INFO testbench.sv(45) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ1] Randomization Done -> Sent Req to Drv
UVM_INFO testbench.sv(47) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ1] Waiting for Item Done Resp from Driver
UVM_INFO testbench.sv(73) @ 0: uvm_test_top.e.a.DRV [DRV] a : 14 b:7
UVM_INFO testbench.sv(49) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ1] SEQ1 Ended
UVM_INFO testbench.sv(50) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ] a : 14 b:7

8] Sequence Page 354

UVM_INFO testbench.sv(50) @ 0: uvm_test_top.e.a.seqr@@s1 [SEQ] a : 14 b:7
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_objection.svh(1276) @ 0: reporter [TEST_DONE]
'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter
[UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 11
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[DRV] 1
[RNTST] 1
[SEQ] 1
[SEQ1] 6
[TEST_DONE] 1
[UVM/RELNOTES] 1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.560 seconds; Data structure size: 0.2Mb
Sat Apr 15 07:12:46 2023

3] Using get_next_item()
https://www.chipverify.com/uvm/uvm-using-get-next-item

1] uvm_driver is a child of uvm_component that has a TLM port to communicate with the sequencer.

2] The driver is a parameterized class with the type of request and response sequence items. This allows the driver to
send back a different sequence_item type back to the sequencer as the response.

3] However, most drivers use a response object of the same type as the request sequence item. The uvm_driver gets
request sequence items (REQ) from the sequencer FIFO using a handshake mechanism and optionally returns a
response sequence item (RSP) back to the sequencer response FIFO.

8] Sequence Page 355

 ⚫ Using get_next_item method

1] in a driver In this case, the driver requests for a sequence item from the sequencer using the get_next_item
method through the seq_item_port TLM handle.

2] Since the implementation of this port is defined in the sequencer, the function call makes the sequencer to pop an
item from its internal FIFO and provide it to the driver via the argument provided in get_next_item method

Driver code :

class my_driver extends uvm_driver #(my_data);

`uvm_component_utils (my_driver)

virtual task run_phase(uvm_phase phase);

super.run_phase(phase);

// 1. Get the next available item from the sequencer. If none exists, then wait until
next item is available -> this is blocking in nature. This task will get an item from the sequencer using get_next_item()
`uvm_info ("DRIVER", $sformatf ("Waiting for data from sequencer"), UVM_MEDIUM)
seq_item_port.get_next_item(req);

// 2. For simplicity, lets just assume the driver drives the received packet
// during this time and consumes 20ns to complete driving the transaction
`uvm_info ("DRIVER", $sformatf ("Start driving tx addr=0x%0h data=0x%0h", req.addr, req.data),;
#20;

// 3. After driver has finished the transaction, it has to let the sequencer know
// by calling item_done()
`uvm_info ("DRIVER", $sformatf ("Finish driving tx addr=0x%0h data=0x%0h", req.addr, req.data)

8] Sequence Page 356

`uvm_info ("DRIVER", $sformatf ("Finish driving tx addr=0x%0h data=0x%0h", req.addr, req.data)
seq_item_port.item_done();
endtask

Once driver gets the next item, it can drive the data in the received sequence item to the DUT via a virtual interface
handle. After the driver has finished driving the item, it has to let the sequencer know that the process has finished
using item_done method.

How does the sequencer get these sequence items ?

A uvm_sequence is started on a sequencer which pushes the sequence item onto the sequencer's FIFO

Sequence code :
class my_sequence extends uvm_sequence;
`uvm_object_utils (my_sequence)

virtual task body();

// 1. Create an item the connected sequencer can accept

my_data tx = my_data::type_id::create("tx");
`uvm_info ("SEQ", $sformatf("About to call start_item"), UVM_MEDIUM)

// 2. Call the start_item() task which will send this object to the driver
start_item(tx);
`uvm_info ("SEQ", $sformatf("start_item() fn call done"), UVM_MEDIUM)

// 3. Because the class handle passed to the driver points to the same object,
// we can do late randomization
tx.randomize();
`uvm_info ("SEQ", $sformatf("tx randomized with addr=0x%0h data=0x%0h", tx.addr, tx.data), UVM_ MEDIUM)

// 4. Call finish_item method so that the sequence waits until the driver lets the
// sequencer know that this item has finished
finish_item(tx);
`uvm_info ("SEQ", $sformatf("finish_item() fn call done"), UVM_MEDIUM)

endtask
endclass

Driver and Sequencer should be instantiated inside an agent. An agent is instantiated in

an environment and the the environment in turn should be created in the test

4] UVM Driver and Sequencer Communication

8] Sequence Page 357
4] UVM Driver and Sequencer Communication
https://learnuvmverification.com/index.php/2015/07/07/uvm-driver-and-sequencer-communication/

1] In UVM, there is a mechanism to be followed when we want to send the transactions from the sequencer to the
Driver in order to provide stimulus to the DUT. Since we know that the whole intelligence of different type of
transactions is imbibed into the sequences and Sequencers are being used as the physical component to execute
those Sequences.

2] A particular Sequence is directed to run on a Sequencer which in turns further breaks down into a series of
transaction items and these transaction items are needs to be transferred to the Driver where these transaction items
are converted into cycle based signal/pin level transitions.

Note: Transaction is a class of data members to be sent to the DUT, control knobs & constraints information.
Transaction item is the object of type Transaction class.

Having said that, sending a transaction/sequence_item from a Sequencer to a Driver is a 4 step process which is listed
below:

Sequencer side operation:

1] Creating the “transaction item” with the declared handle using factory mechanism.

2] Calling “start_item(<transaction_item_handle>)“. This call blocks the Sequencer till it grants the Sequence and
transaction access to the Driver.

3] Randomizing the transaction OR randomizing the transaction with in-line constraints. Now the transaction is ready
to be used by the Driver.

4] Calling “finish_item(<transaction_item_handle>)“. This call which is blocking in nature waits till Driver transfer the
protocol related transaction data.
These are the operational steps from a Sequence which we want to execute using a Sequencer that is connected to a
Driver inside an “Agent”. Whole of this process is shown in the Figure 1 & Figure 2 below:

Figure 1: Driver & Sequencer Interaction for Transaction Exchange

8] Sequence Page 358

Figure 2: Transaction Execution Flow Between a Sequencer , Driver & Virtual
Interface

If we talk about the actions taken by the Driver, then the following steps are made by the Driver in order to
complete the communication with Sequencer(Sequence):

Driver side operation:

1] Declaring the “transaction item” with a handle.

2] Calling the “get_next_item(<transaction_item_handle>)“. Default transaction_handle is “req”. “get_next_item()”

blocks the processing until the “req” transaction object is available in the sequencer request FIFO & later
“get_next_item” returns with the pointer of the “req” object.

3] Next, Driver completes its side protocol transfer while working with the virtual interface.

4] Calling the “item_done()” OR “item_done(rsp)“. It indicates to the sequencer the completion of the
process. “item_done” is a non-blocking call & can be processed with an argument or without an argument. If a
response is expected by the Sequencer/Sequence then item_done(rsp) is called. It results in Sequencer response FIFO
is updated with the “rsp” object handle.

5] How to create and use a sequence

1] Sequences are made up of several data items, which may form an interesting scenario. For example, you can have
a sequence that performs register read/writes to all the registers within the design, a sequence to perform reset, or
another one to apply some stimulus to the DUT. So, you'll end up having a number of different sequences that
perform different tasks to verify different aspects of the design. Remember that a sequence item refers to a packet of
data, while a sequence is just a container for an arrangement of items/sub-sequences.

8] Sequence Page 359

Now, you have a few options

1] Use existing sequences to drive stimulus to the DUT individually

2] Combine existing sequences to create new ones - perform reset sequence followed by register read/writes followed
by FSM state change sequence

3] Pull random sequences from the sequence library and execute them on the DUT

Sequences can do operations on sequence items, or kick-off new sub-subsequences:

8] Sequence Page 360

Need to be read when get time .

UVM Sequences and Transactions Application

Why do we use Sequences and Transactions in UVM..?
https://learnuvmverification.com/index.php/2015/07/29/uvm-sequences-and-transactions-application/
1] I believe, most of us agree that the “Sequence” is the lifeline of UVM based constrained random verification
methodology. Sequences defines the pattern of the stimulus to be applied to the DUT & plays a very significant role in
stimulus generation. But importantly, before diving deep into the “Sequence” concept, one more another very
fundamental item needs attention and that is called “Transaction“. Now, first lets discuss:
What is meant by a “Transaction”?
What is the role/application of a “Transaction”?
What is the relationship of a “Sequence” with the “Transactions”?

2] “Transaction” is a primitive level unit (OOPs Class) in a UVM based Verification Environment ‘Testbench’ which
defines following items as part of it:

A] The data members which stimulates the DUT ports. Pass the values to the DUT ports & receive the response values
from the DUT ports.

B] Some items which controls the temporal behavior & control the dependencies of these data members on each
other to create required verification scenarios. These items we may call as the ‘control knobs’.

3] Constraints applied on the data members & control knobs are also used to be part of a “Transactions”. These
constraints act as the default constraints which anyways can be over-written, if required, by the in-line constraints
defined during Sequence activation and Transaction randomization. Most of the data members & control knobs
(declared using ‘rand’ or ‘randc’ type) are defined as of random in nature to apply the SystemVerilog randomization
capability to the Testbench.
Lets have a look at the example of a “Transaction”.

An Example “Transaction” Code:

/////////////// Transaction Declaration //////////////////

class my_txn extends uvm_sequence_item;
`uvm_object_utils(my_txn)

8] Sequence Page 361

 `uvm_object_utils(my_txn)
/// Data Members towards DUT (rand type)
rand logic [31:0] addr;
rand logic [31:0] wdata;
rand enum {WRITE, READ} kind;
rand int delay;
/// Data Members from DUT (NOT rand type)
logic [31:0] rdata;
bit error;
/// Constructor
function new (string name = “my_txn”);
super.new(name);
endfunction: new
/// Constraint Section
// Delay Between 1 and 20
constraint delay_1_20 {delay inside {(1:20)};}
// 32-bit Aligned Address
constraint 32bit_align {addr[1:0]==0;}
// Write Data Condition
constraint wdata_c {wdata < 32’h2000_0000;}
endclass: my_txn

8] Sequence Page 362

3] Virtual sequencer & Virtual sequence in uvm
03 June 2023 17:43

1]

Implementation of Virtual sequencer & Virtual sequence w.r.p.t svuvm

8] Sequence Page 363

17 July 2023 01:14

m sequencer and P sequencer

https://www.linkedin.com/pulse/difference-between-psequnecer-msequencer-uvm-raghuraj-s-
bhat/

https://verificationguide.com/uvm/m_sequencer-and-p_sequencer/

https://www.theartofverification.com/m_sequencer-vs-p_sequencer/

https://asic4u.wordpress.com/2015/12/31/m_sequencer-p_sequencer-difference/

https://www.quora.com/What-is-a-p_sequencer-and-an-m_sequencer-in-UVM

https://vlsiverify.com/uvm/uvm-sequencer

http://verificationexcellence.in/uvm_sequence-m_sequencer-p_sequencer/

8] Sequence Page 364