BSIM6.1.

1 MOSFET Compact Model

Technical Manual

Authors:
Harshit Agarwal, Chetan Gupta, Sourabh Khandelwal
Juan Pablo Duarte, Yogesh Singh Chauhan
Sayeef Salahuddin and Chenming Hu

Project Director:
Prof. Sayeef Salahuddin and Prof. Chenming Hu

Department of Electrical Engineering and Computer Sciences

University of California, Berkeley, CA 94720

Copyright 2015
The Regents of University of California
All Right Reserved
Past Developers :

Navid Paydavosi, UC Berkeley

Sriramkumar Venugopalan, UC Berkeley
Pankaj Thakur, UC Berkeley
Mohammed A. Karim, UC Berkeley
Contents
1 RELEASE NOTES 9
1.1 Updates made in BSIM6.1.1 . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 BSIM6 Model Equations 11

2.1 Physical constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Effective Channel Length & Width . . . . . . . . . . . . . . . . . . . . . 12
2.3 Binning Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Global geomertical scaling . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 Terminal Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6 Pinch-off Potential and Normalized Charge Calculation . . . . . . . . . . 19
2.6.1 Pinch-off Potential with Poly Depletion . . . . . . . . . . . . . . . 19
2.6.2 Normalized Charge Density . . . . . . . . . . . . . . . . . . . . . 21
2.7 Short Channel Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.8 Drain Saturation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.9 Mobility degradation with vertical field . . . . . . . . . . . . . . . . . . . 28
2.10 Subthreshold hump module . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.11 Parasitic series resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.11.1 Bias Independent External Series Resistance, Bias Dependent In-
ternal Resistance (RDSMOD=0) . . . . . . . . . . . . . . . . . . 30
2.11.2 Bias Dependent External Series Resistance (Rs (V ) & Rd (V )) . . . 30
2.11.3 Bias Dependent Internal Resistance (RDSMOD=2) . . . . . . . . 31
2.11.4 Sheet resistance model . . . . . . . . . . . . . . . . . . . . . . . . 31
2.12 Output Conductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.13 Velocity Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.14 Effective Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.15 Drain Current Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.15.1 Without Velocity Saturation . . . . . . . . . . . . . . . . . . . . . 34

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 2.15.2 Including Velocity Saturation . . . . . . . . . . . . . . . . . . . . 35
2.16 Threshold Voltage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.16.1 Long Channel Threshold Voltage . . . . . . . . . . . . . . . . . . 37
2.17 Impact Ionization Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.18 GIDL/GISL Current Model . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.19 Gate Tunneling Current Model . . . . . . . . . . . . . . . . . . . . . . . 40
2.19.1 Model Selectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.19.2 Equations for Tunneling Currents . . . . . . . . . . . . . . . . . . 41
2.20 Gate resistance and Body resistance network Model . . . . . . . . . . . . 44
2.20.1 Gate Electrode Electrode and Intrinsic-Input Resistance (IIR)
Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.20.2 Substrate Resistance Network . . . . . . . . . . . . . . . . . . . . 46
2.21 Noise Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.21.1 Flicker Noise Models . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.21.2 Channel Thermal Noise . . . . . . . . . . . . . . . . . . . . . . . 50
2.21.3 Gate Current Shot Noise . . . . . . . . . . . . . . . . . . . . . . . 52
2.21.4 Resistor Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.22 Self Heating Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3 Asymmetric MOS Junction Diode Models 54

3.1 Junction Diode IV Model . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.2 Junction Diode CV Model . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4 Layout dependent Parasitics Models 59

4.1 Layout-Dependent Parasitics Models . . . . . . . . . . . . . . . . . . . . 59
4.1.1 Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.1.2 Model Formulation and Options . . . . . . . . . . . . . . . . . . . 60

4
5 Temperature dependence Models 62
5.1 Temperature Dependence Model . . . . . . . . . . . . . . . . . . . . . . . 62
5.1.1 Length Scaling of Temperature parameters . . . . . . . . . . . . . 63
5.1.2 Temperature Dependence of Threshold Voltage . . . . . . . . . . 63
5.1.3 Temperature Dependence of Mobility . . . . . . . . . . . . . . . . 64
5.1.4 Temperature Dependence of Saturation Velocity . . . . . . . . . . 64
5.1.5 Temperature Dependence of LDD Resistance . . . . . . . . . . . . 64
5.1.6 Temperature Dependence of Junction Diode IV . . . . . . . . . . 65
5.1.7 Temperature Dependence of Junction Diode CV . . . . . . . . . . 66
5.1.8 Temperature Dependences of Eg and ni . . . . . . . . . . . . . . . 68

6 Stress effect Model Development 68

6.1 Stress Effect Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.1.1 Stress Effect Model Development . . . . . . . . . . . . . . . . . . 69
6.1.2 Effective SA and SB for Irregular LOD . . . . . . . . . . . . . . . 72

7 Well Proximity Effect Model 73

8 Well Proximity Effect Model 73

8.1 Well Proximity Effect Model . . . . . . . . . . . . . . . . . . . . . . . . . 74

9 C-V Model 76

10 Parameter Extraction Procedure 81

10.1 Extraction of Geometry Independent Parameters . . . . . . . . . . . . . 82
10.1.1 Gate Capacitance CGG vs. VG Analysis @ VS = 0 V , VD = 0 V &
VB = 0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.1.2 Drain Current ID vs. VG Analysis @ VD = [VD,lin , VD,sat ], VS = 0 V
& VB = 0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.1.3 Gate Current IG vs. VG Analysis @ various VD , VS = 0 V & VB = 0 V 84

5
 10.1.4 Drain Current ID vs. VD Analysis @ various VG , VS = 0 V &
VB = 0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.1.5 Gate Capacitance CGG vs. VG Analysis @ VDS 6= 0 V & VB = 0 V 85
10.1.6 Drain Current ID vs. VG Analysis @ VD = [VD,lin , VD,sat ] & various
VB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.1.7 Fitting Verification . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.2 Extraction of Short Channel Effects & Length Scaling Parameters . . . . 86
10.2.1 Gate Capacitance CGG vs. VG Analysis @ VS = 0 V , VD = 0 V &
VB = 0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.2.2 Drain Current ID vs. VG Analysis @ VD = [VD,lin , VD,sat ], VS = 0 V
& VB = 0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.2.3 IG vs. VG Analysis @ various VD , VS = 0 V & VB = 0 V . . . . . 89
10.2.4 ID vs. VD Analysis @ various VG , VS = 0 V & VB = 0 V . . . . . 89
10.2.5 CGG vs. VG Analysis @ VDS 6= 0 V & VB = 0 V . . . . . . . . . . 89
10.2.6 ID vs. VG Analysis @ VD = [VD,lin , VD,sat ] & various VB (or various
VS ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.2.7 Fitting Verification . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.3 Extraction of Narrow Channel Effects & Width Scaling Parameters . . . 91
10.3.1 Gate Capacitance CGG vs. VG Analysis @ VS = 0 V , VD = 0 V &
VB = 0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
10.3.2 Drain Current ID vs. VG Analysis @ VD = [VD,lin , VD,sat ], VS = 0 V
& VB = 0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
10.3.3 Gate Current IG vs. VG Analysis @ various VD , VS = 0 V & VB = 0 V 92
10.3.4 Gate Capacitance CGG vs. VG Analysis @ VDS 6= 0 V & VB = 0 V 93
10.3.5 Drain Current ID vs. VG Analysis @ VD = [VD,lin , VD,sat ] & various
VB (or various VS ) . . . . . . . . . . . . . . . . . . . . . . . . . . 93
10.3.6 Fitting Verification . . . . . . . . . . . . . . . . . . . . . . . . . . 93
10.4 Extraction of Parameters for Narrow/Short Channel Devices . . . . . . . 93
10.4.1 Gate Capacitance CGG vs. VG Analysis @ VS = 0 V , VD = 0 V &
VB = 0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

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 10.4.2 Drain Current ID vs. VG Analysis @ VD = [VD,lin , VD,sat ], VS = 0 V
& VB = 0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.4.3 CGG vs. VG Analysis @ VDS 6= 0 V & VB = 0 V . . . . . . . . . . 95
10.4.4 Drain Current ID vs. VG Analysis @ VD = [VD,lin , VD,sat ] & various
VB (or various VS ) . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.4.5 Fitting Verification . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.5 Extraction of Temperature Dependence Parameters . . . . . . . . . . . . 96
10.5.1 Wide & Long Channel Devices . . . . . . . . . . . . . . . . . . . 96
10.5.2 Length Scaling of Wide Channel Devices . . . . . . . . . . . . . . 98

11 Instance Parameters 100

12 Model Controllers and Process Parameters 101

13 Basic Model Parameters 104

14 High-Speed/RF Model Parameters 111

15 Flicker and Thermal Noise Model Parameters 114

16 Layout-Dependent Parasitic Model Parameters 115

17 Asymmetric Source/Drain Junction Diode Model Parameters 116

18 Temperature Dependence and Self Heating Parameters 119

19 Stress Effect Model Parameters 121

20 Well-Proximity Effect Parameters 123

21 Edge FET Device Parameters 124

22 Parameter equivalence between BSIM6 & BSIM4 126

7
23 Appendix A : Smoothing Function 130
23.1 Polynomial Smoothing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

24 Ackowledgements 136

8
1 RELEASE NOTES

1.1 Updates made in BSIM6.1.1

• Threshold voltage model for operating point information added.

• EDGE FET model (Subthreshold hump module) is added.

• Added an ’External Thermal node’

• Mobility scaling model similar to BSIM4 added, which is accessible through MOB-
SCALE=1.

• Asymmetry Mode is added, similar to BSIM-CMG. Accessible through Assymetry

mode=0/1

• Parameters DELVT0 and MULU0 are added for process variation.

• Parameters A1 and A2 are added for better capturing of velocity saturation effect.

• Parameter K1 is added for improved body effect model.

• Mobility parameters are limited from going negative.

• Protection on parameters K2 and CDSCB removed.

• GMIN is removed.

• Well proximity effect similar to BSIM4.

• Multiplied NF with the effective width in the thermal noise model.

9
• Removed Clamping of UC.

• Removed Clamping of TNOIA, TNOIB, TNOIC.

• Protection on Vth shift due to DIBL.

10
2 BSIM6 Model Equations

2.1 Physical constants

Physical quantities are in M.K.S units unless specified otherwise.

q = 1.6 × 10−19 C (2.1)

F
0 = 8.8542 × 10−12 (2.2)
m
F
sub = EP SRSU B · 0 (2.3)
m
F
ox = EP SROX · 0 (2.4)
m
3.9 · 0 F
Cox = (2.5)
T OXE m2
EP SRSU B
ratio = (2.6)
3.9
(2.7)

11
2.2 Effective Channel Length & Width

LL LW LW L
∆L =LIN T + + + (2.8)
(Lnew )LLN (Wnew )LW N (Lnew )LLN · (Wnew )LW N
WL WW WWL
∆W =W IN T + W LN
+ W W N
+ W LN (2.9)
(Lnew ) (Wnew ) Lnew · (Wnew )W W N
LL LW
∆L1 =LIN T + LLN
+ + (2.10)
(Lnew + DLBIN ) (Wnew + DW BIN )LW N
LW L
LLN
(2.11)
(Lnew + DLBIN ) · (Wnew + DW BIN )LW N
WL WW
∆W1 =W IN T + + + (2.12)
(Lnew + DLBIN )W LN (Wnew + DW BIN )W W N
WWL
W LN
(2.13)
(Lnew + DLBIN ) · (Wnew + DW BIN )W W N
Lnew =L ∗ LM LT + XL; (2.14)
W
Wnew = ∗ W M LT + XW ; (2.15)
NF
∆LCV =DLC (2.16)
∆WCV =DW C (2.17)
Lef f =L ∗ LM LT + XL − 2∆L (2.18)
Wef f =W ∗ W M LT + XW − 2∆W (2.19)
Lef f,CV =L ∗ LM LT + XL − 2∆LCV (2.20)
Wef f,CV =W ∗ W M LT + XW − 2∆WCV (2.21)
Lef f,Bin =L ∗ LM LT + XL − 2∆L1 (2.22)
Wef f,Bin =W ∗ W M LT + XW − 2∆W1 (2.23)

2.3 Binning Calculations

For a given L and W, each model parameter P ARAMi is calculated as a function of

PARAM, and length dependent term, LPARAM, width dependent term, WPARAM, area

12
dependent term, PPARAM:

P ARAMi = P ARAM + LP ARAM · BIN L + W P ARAM · BIN W + P P ARAM · BIN W L

(2.24)

BINUNIT is the binning unit selector. When BINUNIT=1,

1e−6
BIN L = (2.25)
Lef f + DLBIN
1e−6
BIN W = (2.26)
Wef f + DW BIN

when BINUNIT=0,
1.0
BIN L = (2.27)
Lef f + DLBIN
1.0
BIN W = (2.28)
Wef f + DW BIN

and

BIN W L = BIN L · BIN W (2.29)

For the list of binable parameters, please refer to the complete parameter list at the end
of this technical note.

2.4 Global geomertical scaling

Following scaling formulation is used in global scaling -

" !
1 1
P ARAM [L] = P ARAM · 1 + P ARAM L · −
LPefARAM
f
LEXP LLON GP ARAM LEXP
!
1 1
+ P ARAM W · P ARAM W EXP
−
Wef f
W W IDE P ARAM W EXP
!#
1
+ P ARAM W L · P ARAM W LEXP
(2.30)
(Lef f · Wef f )

13
 LLONG is the length of extracted long channel device and WWIDE is the width for
extracted wide device. They are used to ensure that scaling parameters do not affect long-
wide fitting. We will not mention LLONG and WWIDE part again but all of the following
scaling equation use above kind of formulation.

"
1 1
N DEP [L] = N DEP · 1 + N DEP L1 · + N DEP L2 ·
LN DEP LEXP 1
ef f LN DEP LEXP 2
ef f
#
1 1
+ N DEP W · N DEP W EXP
+ N DEP W L ·
Wef f (Lef f · Wef f )N DEP W LEXP
(2.31)

14
 "
1
N F ACT OR[L] = N F ACT OR · 1 + N F ACT ORL ·
LN F ACT ORLEXP
ef f
#
1 1
+ N F ACT ORW · N F ACT ORW EXP
+ N F ACT ORW L ·
Wef f (Lef f · Wef f )N F ACT ORW LEXP
(2.32)
" #
1
CDSCD[L] = CDSCD · 1 + CDSCDL · (2.33)
LCDSCDLEXP
ef f
" #
1
CDSCB[L] = CDSCB · 1 + CDSCBL · (2.34)
LCDSCBLEXP
ef f

if (MOBSCALE=0) (2.35)
  
U 0 · 1 − U 0L · 1

LU 0LEXP U 0LEXP > 0
U 0[L] = ef f (2.36)
U 0 · [1 − U 0L]

Otherwise

else (2.37)
−Le f f −Le f f
U0 [L] = U0 · [1 − U P 1 · exp LP 1 −U P 2 · exp LP 2 ] (2.38)
" #
1 1 1
U A[L] = U A · 1 + U AL · + U AW · + U AW L ·
LU ALEXP
ef f
U AW EXP
Wef f (Lef f · Wef f )U AW LEXP
(2.39)
" #
1 1 1
EU [L] = EU · 1 + EU L · + EU W · + EU W L ·
LEU
ef f
LEXP EU W EXP
Wef f (Lef f · Wef f )EU W LEXP
(2.40)
" #
1
U D[L] = U D · 1 + U DL · (2.41)
LU DLEXP
ef f
" #
1 1 1
U C[L] = U C · 1 + U CL · + U CW · + U CW L ·
LU CLEXP
ef f
U CW EXP
Wef f (Lef f · Wef f )U CW LEXP
(2.42)
" #
1
ET A0[L] = ET A0 · (2.43)
LDSU
ef f
B
" #
1
ET AB[L] = ET AB · (2.44)
LET
ef f
ABEXP
" 15 #
1
P DIBLC[L] = P DIBLC · 1 + P DIBLCL · (2.45)
LPefDIBLCLEXP
f
" #
1
DELT A[L] = DELT A · 1 + DELT AL · (2.46)
LDELT
ef f
ALEXP
 " #
1
F P ROU T [L] = F P ROU T · 1 + F P ROU T L · (2.47)
LFefPfROU T LEXP
" #
1
P CLM [L] = P CLM · 1 + P CLM L · (2.48)
LPefCLM
f
LEXP
"
1 1
V SAT [L] = V SAT · 1 + V SAT L · + V SAT W ·
LVefSAT
f
LEXP V SAT W EXP
Wef f
#
1
+ V SAT W L · (2.49)
(Lef f · Wef f )V SAT W LEXP
" #
1
P SAT [L] = P SAT · 1 + P SAT L · (2.50)
LPefSAT
f
LEXP
" #
1
P T W G[L] = P T W G · 1 + P T W GL · (2.51)
LPefTfW GLEXP
" #
1
ALP HA0[L] = ALP HA0 · 1 + ALP HA0L · (2.52)
LALP
ef f
HA0LEXP
" #
1 1
AGIDL[L] = AGIDL · 1 + AGIDLL · + AGIDLW · (2.53)
Lef f Wef f
" #
1 1
AGISL[L] = AGISL · 1 + AGISLL · + AGISLW · (2.54)
Lef f Wef f
" #
1 1
AIGC[L] = AIGC · 1 + AIGCL · + AIGCW · (2.55)
Lef f Wef f
" #
1 1
AIGS[L] = AIGS · 1 + AIGSL · + AIGSW · (2.56)
Lef f Wef f
" #
1 1
AIGD[L] = AIGD · 1 + AIGDL · + AIGDW · (2.57)
Lef f Wef f
" #
1
P IGCD[L] = P IGCD · 1 + P IGCDL · (2.58)
Lef f
"
1
N DEP CV [L] = N DEP CV · 1 + N DEP CV L1 · N DEP CV LEXP 1
Lef f
1 1
+ N DEP CV L2 · + N DEP CV W ·
LN DEP CV LEXP 2
ef f
N DEP CV W EXP
Wef f
#
161
+ N DEP CV W L · (2.59)
(Lef f · Wef f )N DEP CV W LEXP
 "
1
V F BCV [L] = V F BCV · 1 + V F BCV L ·
LVefFf BCV LEXP
#
1 1
+ V F BCV W · V F BCV W EXP
+ V F BCV W L ·
Wef f (Lef f · Wef f )V F BCV W LEXP
(2.60)
"
1
V SAT CV [L] = V SAT CV · 1 + V SAT CV L ·
LVefSAT
f
CV LEXP
#
1 1
+ V SAT CV W · V SAT CV W EXP
+ V SAT CV W L ·
Wef f (Lef f · Wef f )V SAT CV W LEXP
(2.61)
" #
1
P CLM CV [L] = P CLM CV · 1 + P CLM CV L · (2.62)
LPefCLM
f
CV LEXP
" #
1 1 1
K2[L] = K2 · 1 + K2L · + K2W · + K2W L ·
LK2LEXP
ef f
K2W EXP
Wef f (Lef f · Wef f )K2W LEXP
(2.63)
" #
1
P RW B[L] = P RW B · 1 + P RW BL · (2.64)
LPefRW
f
BLEXP
" #
1
RSW [L] = RSW · 1 + RSW L · (2.65)
LRSW
ef f
LEXP
" #
1
RDW [L] = RDW · 1 + RDW L · (2.66)
LRDW
ef f
LEXP
" #
1
RDSW [L] = RDSW · 1 + RDSW L · (2.67)
LRDSW
ef f
LEXP

17
2.5 Terminal Voltages

BSIM6 is a body referenced model.

K.T
Vt = (2.68)
q
Vg = Vg − Vb (2.69)
Vd = Vd − Vb (2.70)
Vs = Vs − Vb (2.71)
Vgs = Vg − Vs (2.72)
Vgd = Vg − Vd (2.73)
Vgb = Vg − Vb (2.74)
Vds = Vd − Vs (2.75)
q
Vdsx = Vds 2 + 0.01 − 0.1 (2.76)
 
1
Vbsx = − Vs + (Vds − Vdsx ) (2.77)
2

18
2.6 Pinch-off Potential and Normalized Charge Calculation

2.6.1 Pinch-off Potential with Poly Depletion

 
nbody
φb = ln (2.78)
ni
√
2 · q · si · N DEP
γ0 = √ (2.79)
Cox nVt
√
2 · q · si · N GAT E
γg = √ (2.80)
Cox nVt
0 p
γ = γ0 · nVt (2.81)
0 p
γg = γg · nVt (2.82)
N DEP
δP D = (2.83)
N GAT√E
!2 2·q·si√·N DEP !2
γ0 C nVt N DEP
= √ ox = = δP D (2.84)
γg 2·q·si√·N GAT E N GAT E
Cox nVt
γ0
γ= (2.85)
1 + δP D
In accumulation and inversion under depletion approximation, the bulk charge is given as [1]
q
0 − ψs
Qb = −sign(ψs ) · γ · Cox · Vt .(e Vt − 1) + ψs (2.86)

From potential balance equation including poly depletion,

!2
Qi + Qb Qi + Qb
VG = VF B + ψS − + (2.87)
Cox γg0 .Cox

At pinch off,ψS = ψP and Qi = 0. Substituting in (2.86) and (2.87),

q 0
!
0
ψ
− VP γ 2 ψ
− VP
VG − VF B = ψP + γ · Vt .(e t − 1) + ψP + ( 0 ) Vt .(e t − 1) + ψP (2.88)
γg
q !
ψ ψ
0 − VP − VP
= ψP + γ · Vt .(e t − 1) + ψP + δP D Vt .(e t − 1) + ψP (2.89)

19
Normalizing it,
q !
−ψ
vg − vf b = ψp + γ0 · e−ψp + ψp − 1 + δP D e p − 1 + ψp (2.90)

Explicit expression for ψp can be derived from above relation in the asymptotic form by
inspecting the behavior in three different regions. First consider the depletion and inversion
region of operation where ψp >> 0 so that e−ψp is very small. Let ζ1 = e−ψp
!
p
vg − vf b = ψp + γ0 · ψp + ζ1 − 1 + δP D ζ1 − 1 + ψp (2.91)

Let
p
ψp + ζ1 − 1 = x (2.92)

or

ψp = x2 + 1 − ζ1 (2.93)

Thus

vg − vf b = x2 + 1 − ζ1 + γ0 .x + δP D .x2 (2.94)

or
γ0 1 − ζ1 vg − vf b
x2 + ·x+ − =0 (2.95)
1 + δP D 1 + δP D 1 + δP D
This gives
"v
u !2 #
u v g − v − 1 + ζ1 γ0 γ0
fb
x= t + − (2.96)
1 + δP D 2 · (1 + δP D ) 2 · (1 + δP D )

"v
u !2 #2
u vg − v − 1 + ζ1 γ0 γ0
2 fb
ψp = x + 1 − ζ1 = t + − + 1 − ζ1
1 + δP D 2 · (1 + δP D ) 2 · (1 + δP D )
(2.97)
"v
u !2 #2
u vg − v − 1 + ζ1 γ γ
fb
= t + − + 1 − ζ1 (2.98)
1 + δP D 2 2

20
 γ0
where γ = 1+δP D
Similarly,
when ψp is close to 0
" #v" #2
u
vg − vf b γ u vg − v
f b γ
ψp0 = − 3(1 + √ ) + t − 3(1 + √ ) + 6(vg − vf b ) (2.99)
2 2 2 2

and in accumulation where ψp << 0 (ζ2 = ψp ),

" !2 #
vg − vf b − ζ2
ψp = − ln 1 − ζ2 + (2.100)
γ

Thus the pinch off potential is expressed as

   
vg −vf b −ψp0 2

− ln 1 − ψp0 + if vg − vf b < 0


γ
ψp = q 2 (2.101)
γ
2 γ
1 − e−ψp0 + vg − vf b − 1 + e−ψp0 + − otherwise


2 2

Note : Derivatives of ψp are continuous in all regions.

2.6.2 Normalized Charge Density

Inversion Charge [2], [3] : Normalized inversion charge density at source/drain is newly
derived for BSIM6 and can be obtained as follows.
Charge sheet model approximates inversion charge density as
"r r #
ψS −2.φF −Vch
0 p ψS ψS
Qi = −γ .Cox . Vt +e Vt − (2.102)
Vt Vt

Using inversion charge linearization [3],

Qi = nq .Cox · (ψS − ψP ) (2.103)

or
Qi
ψS = ψP + (2.104)
nq .Cox

21
Substituting ψS from (2.104) in (2.102),
"s Qi Qi
s
ψP + nqQ
ψP + −2.φF −Vch i
#
Qi ψ P + nq .Cox
nq .Cox
.C ox
− 0 √ = +e Vt − (2.105)
γ .Cox . Vt Vt Vt

rearranging,
" s
Qi #2 "s Qi ψP +
Qi
−2.φF −Vch
#2
Qi ψP + nq .Cox ψP + nq .Cox
nq .Cox
− 0 √ + = +e Vt (2.106)
γ .Cox . Vt Vt Vt
ψP +
Qi
−2.φF −Vch
!2 ! s Qi
nq .Cox
Qi Qi ψP + nq .Cox
e Vt = − 0 √ − 2. √ · (2.107)
γ .Cox . Vt γ.Cox . Vt Vt

This reduces to
Qi " !2 ! s Qi #
ψP + nq .Cox − 2.φF − Vch Qi Qi ψP + nq .Cox
= ln − 0 √ − 2. 0 √ ·
Vt γ .Cox . Vt γ .Cox . Vt Vt
(2.108)
s
" Qi !#
Qi Qi ψP + nq .Cox
= ln − 0 √ − 0 √ +2·
γ .Cox . Vt γ .Cox . Vt Vt
(2.109)

Normalizing inversion charge to −2Vt .nq .Cox , all voltages to Vt ,

" !#
2nq .qi 2.nq .qi p
ψp −2.qi − 2.φf − vch = ln + 2 · ψp − 2qi (2.110)
γ0 γ0

which gives
 
2nq 2nq p
ln (qi ) + ln (qi + 2 ψp − 2qi ) + 2qi = ψp − 2φf − vch (2.111)
γ0 γ0

This is a general equation which can be solved to give normalized inversion charge density.
The procedure of obtaining initial guess for the solution of above equation for weak inversion
is described below [4]. Note that to generalized the process, subscript ”i” is dropped from the
term qi

22
 √
4nq ψp
Let v = ψp − 2φf − vch − ln( γ ) = ln q + 2q

v = ln q + 2q (2.112)
= ln q + 2eln q (2.113)
1
= ln q + (2.114)
F (ln q)

Here in second term q has been used as ln(eq ). The function F is defined as
1
F = (2.115)
2eln q
1
= (2.116)
2e( ln q + ln qt − ln qt )
1
= ln q (2.117)
2qt e qt
1 −∆
= e (2.118)
2qt

Where ∆ = ln qqt . Expanding (2.118) around ∆ = 0 using Taylor series expansion (as |2q| <<
| ln q| ),
1
F = .[1 − e−0 .∆]] (2.119)
2qt
1 q
= (1 − ln ) (2.120)
2qt qt

substituting in (2.114),
2qt
v = ln q + (2.121)
1 − ln q + ln qt
This equation is solved for q. Let,

ln q = x (2.122)
2qt
v =x+ (2.123)
1 + ln qt − x
v(1 + ln qt ) − vx − x(1 + ln qt ) + x2 − 2qt = 0 (2.124)
p
v + (1 + ln qt ) − (v + (1 + ln qt )2 − 4v(1 + ln qt ) + 8qt
x= (2.125)
2

23
For subthreshold region, normalized inversion charge density will be |q| << 1 and | ln q| >>
|2q|. The initial value is taken at a point where | ln q| = 2.|2q| which gives

qt = 0.301 (2.126)
1 + ln qt = −0.201491 (2.127)

substituting in (2.125),
p
v − 0.201491 − (v − 0.201491)2 − 4v(−0.201491) + 8(0.301)
x= (2.128)
p 2
v − 0.201491 − (v + 0.402982)v + 2.446562
x = ln q = (2.129)
2
Once the initial guess is known, the final value is obtained by using analytical method as shown
below
γ
nq0 = 1 + p (2.130)
2 ψp
 
nq0 p
v = ψp − 2φ − vch − ln 4.0 · · ψp (2.131)
γ
1h p i
lnq0 = v − 0.201491 − v · (v + 0.402982) + 2.446562 (2.132)
2
lnq0
q0 = e (2.133)
if lnq0 <= −80.0
   
nq0 nq0 p
qs/d = f = q0 · 1 + ψp − 2φ − vch − lnq0 − ln 2 · 2 · q0 · + 2 · ψp
γ γ
(2.134)

In this equation, if ln q0 becomes very large and negative then q0 = eln q0 may be out of range
of precision limit of the simulator. Therefore it is approximated as follows
if ln q0 < −110 , q0 = e−100
if ln q0 > −90 , q0 = eln q0
5 z
else q0 = exp(−100 + 20( 64 + 2 + z 2 ( 15 2 2
16 − z (1.25 − z ))))
ln q0 +100
where z = 20 .
The above polynomial provides smooth derivatives for q. For the derivation of polynomial
coefficients, refer to Appendix A.

24
For ln q0 > −80
nq nq p
f = 2q0 + ln (2q0(2q0 + 2 ψp ) − (vp − 2φf − vch ) (2.135)
γ γ
nq0
γ −
√1
0 1 ψp
f =2+ + nq0 p (2.136)
q0 γ · q0 + ψp
f
q1 = q0 − (2.137)
f0
The accuracy of this initial guess is further improved by following procedure
nq nq p
f = 2q1 + ln (2q1(2q1 + 2 ψp ) − (vp − 2φf − vch ) (2.138)
γ γ
nq1 1
γ − √
0 1 ψp
f =2+ + nq1 p (2.139)
q1 γ · q1 + ψp

Applying Halley’s method,

nq0 2
− √1

00 1 1 γ ψp
f =− 2 −h 3
i h p i −  nq0 p  (2.140)
q1 2
n q0
(ψp ) · γ · q1 + ψp γ · q1 + ψp
00
!
f f ·f
qs/d = q1 − 0 · 1 + 2 (2.141)
f 2 · f0

2.7 Short Channel Effects

Asymmetry Mode
There are some devices with asymmetric drain and source structures. This is modeled as
follows:
Weighting Function for forward and reverse modes

25
 T0 = tanh(0.6 ∗ q ∗ V dsnoswap /K · T ); (2.142)
wf = 0.5 + 0.5 ∗ T0 ; (2.143)
wr = 1.0 − wf ; (2.144)
if (ASY M M OD! = 0) (2.145)
P ARAMA = P ARAMI ∗ wr + P ARAMI ∗ wf (2.146)
else (2.147)
P ARAMA = P ARAMI (2.148)
(2.149)

Asymmetry mode affect following parameters: CDSCD, ETA0, PDIBLC, PCLM, PSAT,
VSAT, PTWG, U0, UA, UC, UD, UCS

26
Vt Roll-off, DIBL, and Subthreshold Slope Degradation (Ref.: BSIM4 Model)

kT N DEP
ψst = 0.4 + P HIN + · ln (2.150)
q ni
P histV bs = ψst − Vbsx (2.151)
s
2 · sub · P histV bs
Xdep = (2.152)
q · N DEP
CIT + N F ACT OR + CDSCD · Vdsx − CDSCB · Vbsx
n=1+ (2.153)
Cox
kb · T
Vt = (2.154)
q
nVt = n · Vt (2.155)
p p
∆Vth,V DN U D = K1 · ( φst − Vbs − φst ) − K2 · Vbsx (2.156)
∆Vth,DIBL = −(ET A0 + ET AB · Vbsx ) · Vdsx (2.157)
 
KT Lef f
∆Vth,DIT S = −n · ln
q Lef f + DV T P 0 · (1 + exp(−DV T P 1 · Vds )
!
DV T P 2
− DV T P 5 + DV T P 3 · tanh (DV T P 4 · Vdsx ) (2.158)
Lef f

∆Vth,all = ∆Vth,V N U D + ∆Vth,DIBL + ∆Vth,DIT S (2.159)

Vgf b = Vg − Vf b − ∆Vth,all (2.160)

Note: Short channel effect and Reverse short channel effect are modeled using NDEPL1,
NDELEXP1, NDEPL2 and NDEPLEXP2 parameters. Width scaling of Vth is modeled using
NDEPW and NDEPWEXP parameters.

2.8 Drain Saturation Voltage

The drain saturation voltage model is calculated after the source-side charge (qs ) has
been calculated. Vdsef f is subsequently used to compute the drain-side charge (qd ).
Electric Field Calculations

Electric Field is in M V /cm

27
 
 1 · ET AM OB for NMOS
η= 2 (2.161)
 1 · ET AM OB for PMOS
3
 
qbs + η · qis
Eef f s = 10−8 · (2.162)
ratio · T OXE

Drain Saturation Voltage (Vdsat ) Calculations (Ref. BSIM4 & EKV Model)
UD
Dmobs = 1 + (U A + U C · Vbsx ) · (Eef f s )EU + h  iU CS (2.163)
1 qis
2 · 1+ qbs


1

1+P SAT B·Vbsx Vbs≥0
T0 = (2.164)
1 − P SAT B · V Vbs < 0
bsx

2 · U 0 · nVt 10 · P SAT X · qs · T0
λC = · [1 + P T W G · ] (2.165)
(Dmobs )P SAT · V SAT · Lef f 10 · P SAT X + qs · T0
λC qs2 + qs
qdsat = · (2.166)
2 1 + λ2C · (1 + qs )
  
2φb 2qdsat · nq 2qdsat · nq gam
vdsat = ψp − − 2qdsat − ln · + (2.167)
n gam gam nq − 1
Vdsat = vdsat · nVt (2.168)
Vdssat = Vdsat − Vs (2.169)

Vds
Vdsef f =   1/DELT A DELT A (2.170)
Vds
1 + Vdssat
Vdsef f + Vs
vdef f = (2.171)
nVt

2.9 Mobility degradation with vertical field

(Ref. BSIM4 Model)

 
−8 qba + η · qia
Eef f m = 10 · (2.172)
ratio · T OXE

28
Where qia and qba are the average inversion charge and bulk charge densities respectively.
UD
Dmob = 1 + (U A + U C · Vbsx ) · (Eef f m )EU + h  iU CS (2.173)
1 qia
2 · 1+ qba

The Dmob goes into denominator of mobility expression.

2.10 Subthreshold hump module

The Edge FET Model current is added to the main current Ids , when the parameter
EDGEFET is 1.

IdsEDGE = 2 · N F · nq · µef f · W EDGE/Lef f · Cox · nVt · ((qs − qdef f ) · (1 + qs + qdef f )) · Moc

(2.174)

Now the total current will be IT otal = IdsEDGE + Ids . The parameters associated with
subthreshold hump model are: WEDGE, DGAMMA, DGAMMAL, DGAMMALEXP,
DVTEDGE, NFACTOREDGE, CITEDGE, CDSCDEDGE, CDSCBEDGE, ETA0EDGE,
ETABEDGE, KT1EDGE, KT1LEDGE, KT2EDGE, KT1EXPEDGE, TNFACTOREDGE,
TETA0EDGE, DVT0EDGE, DVT1EDGE, DVT2EDGE.

2.11 Parasitic series resistance

BSIM6 offers three ways to model parasitic resistance of the MOSFET as shown
below
(a) RDSMOD=0, External resistance are bias independent while internal resistance is
bias dependent.
(b) RDSMOD=1, No internal resistance. Both bias dependent and independent resistor
are kept externally.
(c) RDSMOD=2, No external resistance. Both bias dependent and independent resistor
are kept internally.

29
2.11.1 Bias Independent External Series Resistance, Bias Dependent Inter-
nal Resistance (RDSMOD=0)

T0 = 1 + P RW G · qia (2.175)
p p
T1 = P RW B · ( φs − Vbs − φs ) (2.176)
1
T2 = + T1 (2.177)
T0
1
q 
T3 = T2 + T22 + 0.01 (2.178)
2 " #!
WR
Rds (V ) = N F · Wef f RDSW M IN + RDSW · T3 (2.179)

µ0 Wef f
Dr = 1.0 + · Cox · · qia · Rds (2.180)
Dmob .Dvsat Lef f
Rsource = Rs,geo (2.181)
Rdrain = Rd,geo (2.182)

Rs,geo and Rd,geo are the source and drain diffusion resistances, which are described later.
And, Dr goes into the denominator of the final Ids expression.

2.11.2 Bias Dependent External Series Resistance (Rs (V ) & Rd (V ))

The bias-dependent external resistance model is adopted from BSIM4 and can be
invoked by setting model selector RDSMOD=1. BSIM4 and BSIM6 allow the source
extension resistance Rs (V ) and the drain extension resistance Rd (V ) to be external and
asymmetric (i.e. Rs (V ) and Rd (V ) can be connected between the external and internal
source and drain nodes, respectively; furthermore, Rs (V ) does not have to be equal to
Rd (V )). This feature makes accurate RF CMOS simulation possible.
The source/drain series resistance is the sum of a bias-independent component and a

30
bias-dependent component.
 
1
q
Vgs,ef f = 2
Vgs − Vf bsdr + (Vgs − Vf bsdr ) + 10 −2
2
 
1
q
Vgd,ef f = 2
Vgd − Vf bsdr + (Vgd − Vf bsdr ) + 10 −2 (2.183)
2
  
1 1
Rsource = W R · RSW M IN + RSW · −P RW B · Vbs +
Wef f · N F 1 + P RW Gi · Vgs,ef f
+ Rs,geo (2.184)
  
1 1
Rdrain = WR
· RDW M IN + RDW · −P RW B · Vbd +
Wef f · NF 1 + P RW Gi · Vgd,ef f
+ Rd,geo (2.185)

Rs,geo and Rd,geo are the source and drain diffusion resistances.

2.11.3 Bias Dependent Internal Resistance (RDSMOD=2)

" #!
WR
Rds (V ) = Rs,geo + N F · Wef f RDSW M IN + RDSW · T3 + Rd,geo (2.186)

µ0 Wef f
Dr = 1.0 + · Cox · · qia · Rds (2.187)
Dmob .Dvsat Lef f

where T3 is given by (2.178).

2.11.4 Sheet resistance model

The resistances Rs,geo and Rd,geo are simply calculated as the sheet resistances (RSHS,RSHD)
times the number of squares (N RS,N RD):

Rs,geo = N RS · RSHS
Rd,geo = N RD · RSHD (2.188)

31
2.12 Output Conductance
The Output conductance model is taken from BSIM4 [5]
Channel Length Modulation (CLM)
2 · V SAT
Esat = U0
(2.189)
Dmob

1

 for F P ROU T ≤ 0
F = 1 √ (2.190)
 for F P ROU T > 0
 1+ F P ROU T · Lef f

qia+2·nVt
  
qia 1


 P CLM · 1 + P CLM G · Esat ·Lef f F for P CLM G > 0
Cclm =  P CLM  1
(2.191)
 F for P CLM G < 0
 · 1−P CLM G· qia

Esat ·Lef f

Vasat = Vdssat + EsatL (2.192)

 
Vds − Vdsef f 1
MCLM = 1 + Cclm ln 1 + · (2.193)
Vasat Cclm
Drain Induced Barrier Lowering (DIBL)

1 + P V AG · E qim
 for P V AG > 0
sat Lef f
P V AGf actor = (2.194)
 1−P V AG·1 qim
 for P V AG < 0
Esat Lef f

θrout = P DIBLC (2.195)

 
qia + 2kT /q Vdssat 1
VADIBL = · 1− · P V AGf actor ·
θrout Vdssat + qia + 2kT /q 1 + P DIBLCB · Vbsx
(2.196)
 
Vds − Vdsef f
MDIBL = 1 + (2.197)
VADIBL
Note: Length scaling parameters for PDIBLC are PDIBLCL and PDIBLCLEXP.
Drain Induced Threshold Shift (DITS)
1
VADIT S = · F · [1 + (1 + P DIT SL · Lef f ) exp(P DIT SD · Vds )] (2.198)
P DIT S 
Vds − Vdsef f
MDIT S = 1 + (2.199)
VADIT S

32
Substrate Current induced Body Effect (SCBE)
p
litl = (sub /ox ) · T OXE · XJ (2.200)
 
Lef f P SCBE1 · litl
VASCBE = · exp (2.201)
P SCBE2 Vds − Vdsef f
 
Vds − Vdsef f
MSCBE = 1 + (2.202)
VASCBE

Moc = MDIBL · MCLM · MDIT S · MSCBE (2.203)

Moc is multiplied to Ids in the final drain current expression.

2.13 Velocity Saturation

Current Degradation Due to Velocity Saturation

T1 = 2 · λC · (qs − qdef f ) (2.204)

2 · U 0 · nVt 10 · P SAT X · qs · T0
λC = 1 · [1 + P T W G · ] (2.205)
(Dmobs )P SAT· V SAT · Lef f 10 · P SAT X + qs · T0
q 
1 1
q
Dvsat = 2
1 + T1 + 2
· ln(T1 + 1 + T1 ) (2.206)
2 T1
Dptwg = Dvsat (2.207)
Dtot = Dmob · Dvsat · Dr (2.208)

where Dr is the effect of internal resistance (Rdsi ) on current, defined as


1 if RDSM OD = 1
Dr = (2.209)
1 + U 0 · C · Wef f · q · R
ox Lef f ia dsi if RDSM OD = 0

33
Non-Saturation Effect Some devices do not exhibit prominent or abrupt velocity satu-
ration. The parameters A1 and A2 are used to tune this non-saturation effect to better the
Id,sat or gm,sat fitting.

T0 = A1 + A2 /(qia + 2.0 ∗ n ∗ Vtm ); (2.210)

dqi = qs − qdef f ; (2.211)
T1 = T0 ∗ dqi ∗ dqi; (2.212)
T2 = T1 + 1.0 − 0.001; (2.213)
p
T3 = −1.0 + 0.5 ∗ (T2 + T2 ∗ T2 + 0.004); (2.214)
p
Nsat = 0.5 ∗ (1.0 + 1.0 + T3 ); (2.215)
Ids = Ids /Nsat ; (2.216)

2.14 Effective Mobility

U0
µef f = (2.217)
Dtot

2.15 Drain Current Model

2.15.1 Without Velocity Saturation

The drain current expression is derived as follows,

Ids =Idrif t + Idif f (2.218)

dψs dQi
Ids = − Wef f .Qi · µef f + W · µef f · Vt (2.219)
dx dx
from charge linearization, ψs = ψp + nqQ i
.Cox . Thus
" #
Qi dQi
Ids =µef f .Wef f · − + Vt (2.220)
nq .Cox dx

34
normalizing inversion charge to −2nq Cox Vt and using ξ = Lx ,
" #
Wef f (−2.nq .Cox .Vt .q) d(−2.nq .Cox .Vt .q)
Ids = µef f . · − + Vt (2.221)
Lef f nq .Cox dξ
Wef f dq
= −2 · nq · µef f · · Cox · nVt2 · (2q + 1) (2.222)
Lef f dξ

Total drain current,

Z 1 Z qd
Wef f 2
IDS = Ids dξ = −2 · nq · µef f · · Cox · nVt · (2q + 1)dq (2.223)
0 Lef f qs

which gives
Wef f
IDS = 2 · nq · µef f · · Cox · nVt2 · [(qs − qdef f )(qs + qdef f + 1)] (2.224)
Lef f

nq is the slope factor in charge based model and nVt is n. KT

q with n given by (2.153).

2.15.2 Including Velocity Saturation

As the device is getting smaller and smaller, the lateral electric field strength and
therefore kinetic energy of the carriers increases. On reaching optical phonon energy
levels, they releases optical phonon by virtue of reduction in kinetic energy and therefore
loses velocity [6]. The effect of velocity saturation on mobility is captured as follows
µef f
µ= q (2.225)
1 + ( EEc )2
µef f
=q (2.226)
1 + ( E1c · dψ
dx
s 2
)

from (2.222) and (2.226),

µef f Wef f dq
Ids = −2 · nq · q · · Cox · nVt2 · (2q + 1) (2.227)
1 + ( E1c · dψs 2
) Lef f dξ
dx

(2q + 1) dq
dξ
=z·q (2.228)
dψs 2
1 + ( E1c · dx
)

35
 Wef f
with z = −2µef f · nq · Lef f
· Cox · nVt2
Total current,
qd
Z
Z 1
(2q + 1)
IDS = Ids dξ = z · q dq (2.229)
0
qs 1 + ( E1c · dψ
dx
s 2
)

v
1
Z u !2 Z qd
u 1 dψs
IDS t1 + · dξ = z · (2q + 1)dq (2.230)
Ec dx qs
0

from (2.224),
Z qd
(2q + 1)dq = −(qs − qdef f )(qs + qdef f + 1) (2.231)
qs

Qi
Now consider the LHS of (2.230). Using charge linearization, ψs = ψp + nq .Cox
,

1 dψs 1 Qi 2Vt dq dq
= =− = −λc · (2.232)
Ec dx Ec .nq .Cox dx Ec .L dξ dξ
Let
Z v !2
u
u 1 dψs
Dvsat = t1 + · dξ
Ec dx

It is evaluated by assuming that lateral electric field (− dψ

dξ
s
) increases linearly from 0 at
!
ψs,D −ψs,S
source to 2 · L
at drain [7] i.e.

dψs ψs,D − ψs,S x ψs,D − ψs,S

− =2· · =2· ·ξ (2.233)
dx L L L
From charge linearization (2.104),
QS
ψs,S = ψP + = ψP − 2Vt .qs (2.234)
nq .Cox
QD
ψs,D = ψP + = ψP − 2Vt .qd (2.235)
nq .Cox
ψs,D − ψs,S = 2.Vt (qs − qd ) (2.236)

36
substituting in (2.233),
dψs 2.Vt (qs − qd ) 2.Vt (qs − qd )
− =2· 2
·x=2· ·ξ (2.237)
dx L L
1 dψs 2.Vt
− =2· · (qs − qd )ξ = 2λc (qs − qd )ξ (2.238)
Ec dx Ec L
2Vt
where λc = .
Thus Dvsat can be given as
Ec .L
v !2
Z u
u 1 dψ s
Dvsat = t1 + · dξ (2.239)
Ec dx
Z p Z p
= 2
1 + (2λc (qs − qd )ξ) dξ = 1 + (2λc .∆q · ξ)2 dξ (2.240)
!#
1 hp 1 p
= 1 + (2.λc .∆q)2 + . ln 2.λc .∆q + 1 + (2.λc .∆q)2
2 2.λc .∆q
(2.241)

with ∆q = qs − qd . From (2.230), (2.231) and (2.241),

Wef f
IDS = 2 · nq · µef f · · Cox · nVt2 · [(qs − qdef f )(qs + qdef f + 1)].Moc (2.242)
Lef f
U0
where µef f = Dtot
and Dtot = Dmod .Dvsat .Dr

2.16 Threshold Voltage Model

2.16.1 Long Channel Threshold Voltage

The drain current under the standard drift-diffusion formalism can be represented
as

Ids =Idrif t + Idif f (2.243)

dψs dQi
Ids = − W.Qi · µ + W · µ · Vt (2.244)
dx dx
Defining threshold voltage as the gate voltage at which Idrif t = Idif f , which leads to
qi = 21 . Here, we define threshold voltage as the gate voltage at which normalized

37
inversion charge density at the source is qs = 21 . Pinch-off potential corresponding to
qs = 12 , ψp,th , is calculated using qs = 12 in (2.111) leading to
" #  
2nq nq p
ψp,th = ln (0.5) + 1 + ln ( + 2 ψp,th − 1) + 2φf + vs (2.245)
γ0 γ0

To obtain ψp,th in explicit form, we make an assumption that at threshold voltage,

ψp,th − 1 = 2φf + vs (2.246)

The other bias dependent term nq is also approximated by

γ
nq = 1 + p (2.247)
2 2φf

This gives,
" #  
2nq nq p
ψp,th = ln (0.5) + 1 + ln ( + 2 2φf − vb ) + 2φf
γ0 γ0
+ vs (2.248)

After ψp,th is obtained, next step is to calculate threshold voltage. The potential
balance equation in conjunction with Poisson’s equation and Gauss law for the MOSFET
is given as ()

Qin + Qdep
VG = VF B + ψS − (2.249)
Cox
At pinch-off, ψS = ψP , and Qin = 0
p
VG = VF B + ψP + γ ψP (2.250)

Thus
p
VT H,long = VF B + ψp,th .Vt − γ ψp,th .Vt (2.251)

Short Channel Threshold Voltage

VT H = VT H,long − ∆Vth,all (2.252)

38
2.17 Impact Ionization Model
The impact ionization current model in BSIM6 is the same as that in BSIM4, and
is modeled by
 BET A0  Ids
Iii = ALP HA0 · (Vds − Vdsef f ) · exp − · (2.253)
Vds − Vdsef f MSCBE
where parameters ALP HA0 and BET A0 are impact ionization coefficients. ALPHA0L
and ALPHA0LEXP are length scaling parameters for ALPHA0.
Note: The order of ALPHA0 in BSIM6 = 106 X order of ALPHA0 in BSIM4

2.18 GIDL/GISL Current Model

GIDL/GISL currents are set using model selector GIDLMOD=1. The GIDL/GISL
current and its body bias effect are modeled by

Vds − Vgse − EGIDL

IGIDL = AGIDL · Wef f · N F ·
3 · Toxe
!
3 · Toxe · BGIDL Vdb3
·exp − · (2.254)
Vds − Vgse − EGIDL CGIDL + Vdb3

−Vds − Vgde − EGISL

IGISL = AGISL · Wef f · N F ·
3 · Toxe
!
3 · Toxe · BGISL Vsb3
·exp − · (2.255)
−Vds − Vgde − EGISL CGISL + Vsb3

where AGIDL, BGIDL, CGIDL and EGIDL are model parameters for the drain side
and AGISL, BGISL, CGISL and EGISL are the model parameters for the source
side. CGIDL and CGISL account for the body-bias dependence of IGIDL and IGISL
respectively.Wef f and N F are the effective width of the source/drain diffusions and the
number of fingers. Further explanation of Wef f and N F can be found in the chapter of
the layout-dependence model. Check scaling parameters in the parameter list at the end.

IGIDL /IGISL can be switched off by setting GIDLM OD = 0.

39
 Figure 1: Schematic gate current components flowing between MOSFET terminals.

2.19 Gate Tunneling Current Model

As the gate oxide thickness is scaled down to 3nm and below, gate leakage current due
to carrier direct tunneling becomes important. This tunneling happens between the gate
and silicon beneath the gate oxide. To reduce the tunneling current, high-k dielectrics are
being used in place of gate oxide. In order to maintain a good interface with substrate,
multi-layer dielectric stacks are being used. The BSIM6 gate tunneling model (taken
from BSIM4) has been shown to work for multi-layer gate stacks as well. The tunneling
carriers can be either electrons or holes, or both, either from the conduction band or
valence band, depending on (the type of the gate and) the bias regime. In BSIM6,
the gate tunneling current components include the tunneling current between gate and
substrate (Igb ), and the current between gate and channel (Igc ), which is partitioned
between the source and drain terminals by Igc = Igcs + Igcd . The third component
happens between gate and source/drain diffusion regions (Igs and Igd ). Figure 1 shows
the schematic gate tunneling current flows.

2.19.1 Model Selectors

Two global selectors are provided to turn on or off the tunneling components.
IGCMOD = 1 turns on Igc , Igs , and Igd ; IGBMOD = 1 turns on Igb . When the

40
selectors are set to zero, no gate tunneling currents are modeled.

Vox = nV t · (vg − vf b − ψp + qs + qdef f ) (2.256)

1 p
2 + 10−4

Voxacc = −Vox + Vox (2.257)
2
1 p
2 + 10−4

Voxdepinv = Vox + Vox (2.258)
2

Eq. (2.257) and (2.258) are valid and continuous from accumulation through deple-
tion to inversion.

2.19.2 Equations for Tunneling Currents

Note: All gate tunneling current equations use operating temperature in the calcu-
lations.

Gate-to-Substrate Current (Igb = Igbacc + Igbinv ): Igbacc , determined by ECB (Elec-

tron tunneling from Conduction Band), is significant in accumulation and given by

Igbacc = N F · Wef f Lef f · A · ToxRatio · Vgb · Vaux · igtemp

·exp[−B · T OXE(AIGBACC − BIGBACC · Voxacc ) · (1 + CIGBAC · Voxacc )]
(2.259)

where the physical constants A = 4.97232e − 7 A/V 2 , B = 7.45669e11(g/F − s2 )0.5 ,

and
!N T OX
T OXREF 1
ToxRatio = · (2.260)
T OXE T OXE 2
!!
Voxacc
Vaux = N IGBACC · Vt · log 1 + exp − (2.261)
N IGBACC · Vt

41
Igbinv , determined by EVB (Electron tunneling from Valence Band), is significant in
inversion and given by

Igbinv = N F · Wef f Lef f · A · ToxRatio · Vgb · Vaux · igtemp

·exp[−B · T OXE(AIGBIN V − BIGBIN V · Voxdepinv ) · (1 + CIGBIN V Voxdepinv )]

(2.262)

where A = 3.75956e-7 A/V 2 , B = 9.82222e11 (g/F − s2 )0.5 , and

!!
Voxdepinv − EIGBIN V
Vaux = N IGBIN V · Vt · log 1 + exp (2.263)
N IGBIN V · Vt

Igb = Igbacc + Igbinv (2.264)

Gate-to-Channel Current (Igc0 ) and Gate-to-S/D (Igs and Igd ): Igc0 , deter-
mined by ECB for NMOS and HVB (Hole tunneling from Valence Band) for PMOS at
Vds = 0, is formulated as

Igc0 = N F · Wef f Lef f · A · ToxRatio · Vgse · Vaux · igtemp

·exp[−B · T OXE(AIGC − BIGC · Voxdepinv ) · (1 + CIGCVoxdepinv )]
(2.265)

where A = 4.97232 A/V 2 for NMOS and 3.42537 A/V 2 for PMOS, B = 7.45669e11
(g/F − s2 )0 .5 for NMOS and 1.16645e12 (g/F − s2 )0.5 for PMOS.
Vaux = nq · nV t · (qs + qdef f ) (2.266)

Partition of Igc : To consider the drain bias effect, Igc is split into two components,
Igcs and Igcd , that is Igc = Igcs + Igcd , and
P IGCD · Vdsef f x + exp(−P IGCD · Vdsef f x ) − 1 + 10−4
Igcs = Igc0 · (2.267)
P IGCD · Vdsef f x 2 + 2 · 10−4
and
1 − (P IGCD · Vdsef f x + 1) · exp(−P IGCD · Vdsef f x ) + 10−4
Igcd = Igc0 · (2.268)
P IGCD · Vdsef f x 2 + 2 · 10−4

42
 where
p
Vdsef f x = Vdsef f + 0.01 − 0.1 (2.269)
1
At Vds = 0, Igcs = Igcd = I .
2 gc0
Thus Igc0 is the gate to channel current Igc at
Vds = 0.

Igs and Igd : Igs represents the gate tunneling current between the gate and the source
diffusion region, while Igd represents the gate tunneling current between the gate and
the drain diffusion region. Igs and Igd are determined by ECB for NMOS and HVB for
PMOS, respectively.
0
Igs = N F · Wef f DLCIG · A · ToxRatioEdge · Vgs · Vgs · igtemp
0 0
·exp[−B · T OXE · P OXEDGE · (AIGS − BIGS · Vgs ) · (1 + CIGSVgs )]
(2.270)

and
0
Igd = N F · Wef f DLCIGD · A · ToxRatioEdge · Vgd · Vgd · igtemp
0 0
·exp[−B · T OXE · P OXEDGE · (AIGD − BIGD · Vgd ) · (1 + CIGDVgd )]
(2.271)

where A = 4.97232 A/V 2 for NMOS and 3.42537 A/V 2 for PMOS, B = 7.45669e11
(g/F − s2 )0.5 for NMOS and 1.16645e12 (g/F − s2 )0.5 for PMOS, and
!N T OX
T OXREF 1
ToxRatioEdge = · (2.272)
T OXE · P OXEDGE (T OXE · P OXEDGE)2
q
0
Vgs = (Vgs − Vf bsd )2 + 10−4 (2.273)
q
0
Vgd = (Vgd − Vf bsd )2 + 10−4 (2.274)

Vfbsd is the flat-band voltage between gate and S/D diffusions calculated as
If N GAT E > 0.0
!
kB T N GAT E
Vf bsd = −devsign · log + V F BSDOF F (2.275)
q N SD
Else Vf bsd = 0.0.

43
2.20 Gate resistance and Body resistance network Model

2.20.1 Gate Electrode Electrode and Intrinsic-Input Resistance (IIR) Model

General Description: BSIM6 provides four options for modeling gate electrode re-
sistance (bias-independent) and intrinsic-input resistance (IIR, bias-dependent). The
IIR model considers the relaxation-time effect due to the distributive RC nature of the
channel region, and therefore describes the first-order non-quasi-static effect. Thus, the
IIR model should not be used together with the charge-deficit NQS model at the same
time. The model selector RGATEMOD is used to choose different options.

Model Option and Schematic: There are four model selectors for gate resistance
network.
RGATEMOD = 0 (zero-resistance): In this case, no gate resistance is generated
(see Figure 2).
RGATEMOD = 1 (constant-resistance): In this case, only the electrode gate resis-
tance (bias-independent) is generated by adding an internal gate node. Rgeltd is given
by
W
ef f ci
RSHG · (XGW + 3·N GCON )
Rgeltd = (2.276)
N GCON · (Ldrawn − XGL) · N F
RGATEMOD = 2 (IIR model with variable resistance): In this case, the gate
resistance is the sum of the electrode gate resistance Rgeltd (2.276) and the intrinsic-
input resistance Rii as given by (2.277). An internal gate node will be generated.
 
1 Ids Wef f µef f Coxef f Vt
= XRCRG1.N F · + XRCRG2 ·
Rii Vdsef f Lef f
or
   
1 Wef f Wef f µef f Coxef f Vt
≈ XRCRG1.N F · µef f Cox · qia + XRCRG2 ·
Rii Lef f Lef f
(2.277)

RGATEMOD = 3 (IIR model with two nodes): In this case, the gate electrode
resistance Rgeltd is in series with the intrinsic-input resistance Rii through two internal
gate nodes, so that the overlap capacitance current will not pass through the intrinsic-
input resistance.

44
 (a) (b)

(c) (d)

Figure 2: Gate resistance network for (a) RGAT EM OD = 0 (b) RGAT EM OD = 1

(b) RGAT EM OD = 2 (d) RGAT EM OD = 3 .

45
2.20.2 Substrate Resistance Network

General Description: For CMOS RF circuit simulation, it is essential to consider

the high frequency coupling through the substrate. BSIM6 offers a flexible built-in
substrate resistance network. This network is constructed such that little simulation
efficiency penalty will result. Note that the substrate resistance parameters should be
extracted for the total device, not on a per-finger basis.

Model Selector and Topology The model selector RBODYMOD can be used to
turn on or turn off the resistance network.
RBODYMOD = 0 (Off):
No substrate resistance network is generated at all.
RBODYMOD = 1 (On):
All five resistances RBP S, RBP D, RBP B, RBSB, and RBDB in the substrate
network as shown schematically below are present simultaneously.
A minimum conductance, GBMIN, is introduced in parallel with each resistance
and therefore to prevent infinite resistance values, which would otherwise cause poor
convergence. GBMIN is merged into each resistance to simplify the representation of
the model topology. Note that the intrinsic model substrate reference point in this case
is the internal body node bNodePrime, into which the impact ionization current Iii
and the GIDL current IGIDL flow.
RBODYMOD = 2 (On : Scalable Substrate Network):
The schematic is similar to RBODYMOD = 1 but all the five resistors in the
substrate network are now scalable with a possibility of choosing either five resistors,
three resistors or one resistor as the substrate network.
The resistors of the substrate network are scalable with respect to channel length (L),
channel width (W) and number of fingers (NF). The scalable model allows to account
for both horizontal and vertical contacts.
The scalable resistors RBPS and RBPD are evaluated through
!RBP SL !RBP SW
L W
RBP S = RBP S0 · · · N F RBP SN F (2.278)
10−6 10−6
!RBP DL !RBP DW
L W
RBP D = RBP D0 · · · N F RBP DN F (2.279)
10−6 10−6

46
 Figure 3: Topology with the substrate resistance network turned on.

The resistor RBPB consists of two parallel resistor paths, one to the horizontal contacts
and other to the vertical contacts. These two resistances are scalable and RBPB is given
by a parallel combination of these two resistances.
!RBP BXL !RBP BXW
L W
RBP BX = RBP BX0 · · · N F RBP DN(2.280)
F
10−6 10−6
!RBP BY L !RBP BY W
L W
RBP BY = RBP BY 0 · −6
· −6
· N F RBP DN(2.281)
F
10 10
RBP BX · RBP BY
RBP B = (2.282)
RBP BX + RBP BY

The resistors RBSB and RBDB share the same scaling parameters but have different
scaling prefactors. These resistors are modeled in the same way as RBPB. The equations

47
for RBSB are shown below. The calculation for RBDB follows RBSB.
!RBSBXL !RBSBXW
L W
RBSBX = RBSBX0 · · · N F RBSDN F(2.283)
10−6 10−6
!RBSBY L !RBSBY W
L W
RBSBY = RBSBY 0 · · · N F RBSDN F(2.284)
10−6 10−6
RBSBX · RBSBY
RBSB = (2.285)
RBSBX + RBSBY
Similarly, the equations for RBDB is as follows
 RBDBXL  RBDBXW
L L
RBDBX = RBDBX0 · −6
· −6
· (N F )RBDBXN F
10 10
(2.286)

 RBDBY L  RBDBY W
L L
RBDBY = RBDBY 0 · · · (N F )RBDBY N F
10−6 10−6

(2.287)

RBDBX × RBDBY
RBDB = (2.288)
RBDBX + RBDBY
The implementation of RBODYMOD = 2 allows the user to chose between the
5-R network (with all five resistors), 3-R network (with RBPS, RBPD and RBPB) and
1-R network (with only RBPB).
If the user does not provide both the scaling parameters RBSBX0 and RBSBY0
for RBSB or both the scaling parameters RBDBX0 and RBDBY0 for RBDB, then the
conductances for both RBSB and RBDB are set to GBMIN. This converts the 5-R
schematic to 3-R schematic where the substrate network consists of the resistors RBPS,
RBPD and RBPB. RBPS, RBPD and RBPB are then calculated using (2.278), (2.279),
and (2.282).
If the user chooses not to provide either of RBPS0 or RBPD0, then the 5-R schematic
is converted to 1-R network with only one resistor RBPB. The conductances for RBSB
and RBDB are set to GBMIN. The resistances RBPS and RBPD are set to 1e-3 Ohm.
The resistor RBPB is then calculated using (2.282).
In all other situations, 5-R network is used with the resistor values calculated from
the equations aforementioned.

48
2.21 Noise Modeling
The following noise sources in MOSFETs are modeled in BSIM6 for SPICE noise
ananlysis: flicker noise (also known as 1/f noise), channel thermal noise and induced
gate noise and their correlation, thermal noise due to physical resistances such as the
source/ drain, gate electrode, and substrate resistances, and shot noise due to the gate
dielectric tunneling current.
Noise models in BSIM 6.0.0 Origin
Flicker noise model BSIM4 Unified Model (FNOIMOD=1)
Thermal noise(TNOIMOD=0) BSIM4 (TNOIMOD=0)
Thermal noise (TNOIMOD=1) BSIM4 (TNOIMOD=2)
Gate current shot noise BSIM4 gate current noise
Noise associated with parasitic resistances BSIM4 parasitic resistance noise

2.21.1 Flicker Noise Models

BSIM6’s flicker noise model is same as FNOIMOD=1 in BSIM4. The unified physical
flicker noise model is smooth over all bias regions.
The physical mechanism for the flicker noise is trapping/detrapping-related charge
fluctuation in oxide traps, which results in fluctuations of both mobile carrier numbers
and mobilities in the channel. The unified flicker noise model captures this physical
process. In the inversion region, the noise density is expressed as [8]

kT q 2 µef f Ids N0 + N ∗
 
Sid,inv (f ) = N OIA · log
Coxe L2ef f N OI f EF · 1010 Nl + N ∗
!
N OIC 2
N OIB · (N0 − Nl ) + (N0 − Nl2 )
2
!
2
kT Ids ∆Lclm N OIA + N OIB · Nl + N OIC · Nl2
2
(2.289)
Wef f Lef f N OI f EF · 1010 (Nl + N ∗ )2

where Lef f N OI = Lef f − 2 · LIN T N OI, µef f is the effective mobility at the given bias
condition, and Lef f and Wef f are the effective channel length and width, respectively.

49
The parameter N0 is the charge density at the source side given by
2nq Cox Vt qs
N0 = (2.290)
q
The parameter Nl is the charge density at the drain end given by
2nq Cox Vt qdef f
Nl = (2.291)
q

and N* is given by
Vt Cox + Cd + CIT )
N∗ = (2.292)
q
where CIT is a model parameter from DC IV and Cd is the depletion capacitance.
∆Lclm is the channel length reduction due to channel length modulation and given
by
Vds −Vdsef f
!
litl
+ EM
∆Lclm = litl · log
Esat
2V SAT
Esat = (2.293)
µef f

In the subthreshold region, the noise density is written as

2
N OIA · k · T · Ids
Sid,subV t (f ) = (2.294)
Wef f Lef f f EF N ∗2 · 1010

The total flicker noise density is

Sid,inv · Sid,subV t
Sid (f ) = (2.295)
Sid,inv + Sid,subV t

2.21.2 Channel Thermal Noise

There are two channel thermal noise models in BSIM6. One is a charge-based model
(default model) similar to that used in BSIM3v3.2 and BSIM4.7.0 (TNOIMOD=0). The
other is the holistic model similar to BSIM4.7.0 (TNOIMOD=2). These two models can
be selected through the model selector TNOIMOD.

50
TNOIMOD = 0 (Charge based Model): The noise current is given by

Qinv = |Qs,intrinsic + Qd,intrinsic | × N F INtotal (2.296)


4kT ∆f
N T N OI ·
 L2
if RDSMOD = 0
2 Rds + µ efQf
id = ef f inv (2.297)
N T N OI · 4kT2 ∆f · µef f Qinv if RDSMOD = 1

L
ef f

where Rds (V ) is the bias-dependent LDD source/drain resistance, and the parameter
NTNOI is introduced for more accurate fitting of short-channel devices. Qinv is the total
inversion charge in the channel.

TNOIMOD = 1 (Holistic Model): In this thermal noise model (similar to TNOIMOD

= 2 in BSIM4.7.0), all the short-channel effects and velocity saturation effect incorpo-
rated in the IV model are automatically included, hence the name ”holistic thermal
noise model”. In this thermal noise model both the gate and the drain noise are im-
plemented as current noise sources. The drain current noise flows from drain to source;
whereas the induced gate current noise flows from the gate to the source. The corre-
lation between the two noise sources is independently controllable and can be tuned
using the parameter RNOIC, although the use of default value 0.395 is recommended
when measured data is not available. As illustrated in Fig. 4, TNOIMOD=1 shows
good physical behavior in both the weak and strong inversion regions. The white noise
SId
gamma factor γW N = 4kT gd0
shows a value of 1 at low Vds , as expected. At high Vds ,
it correctly goes to 2/3 for strong inversion and 1/2 in sub-threshold [9]. The relevant
formulations of TNOIMOD=2 are given below. For more details, see Ph.D. thesis of
Darsen Lu and BSIM4 manual.
"  2 #
qia
βtnoi = RN OIA · 1.0 + T N OIA · Lef f · (2.298)
Esat,noi Lef f
"  2 #
qia
θtnoi = RN OIB · 1.0 + T N OIB · Lef f · (2.299)
Esat,noi Lef f
"  2 #
qia
ctnoi = RN OIC · 1.0 + T N OIC · Lef f · (2.300)
Esat,noi Lef f
(2.301)

51
  
2
Wef f qs + qdef f (qs − qdef f )  2
Sid = 4KT · µCox Vt Dptwg Moc  +   · (3 · βtnoi )
Lvsat 2 12
1+qs +qdef f
2
(2.302)

" q +q
s
1 L3vsat 2
def f

mig = · 2
12 · N F · Wef f µef f · Dptwg Moc Cox · Vt L2ef f

1+qs +qdef f
2
   
q +q
6 s 2def f + 12 (qs − qdef f )2
#
(qs − qdef f )4 15 2
− 4 + 5 · ( · θtnoi ) (2.303)
4
 
1+qs +qdef f 1+qs +qdef f
60 2
144 2

4KT · [ω · Cox · W · N F · L]2 · mig

Sig = (2.304)
1 + (ω · C0x · L · W · N F · mig)2

" #
Lvsat (qs − qdef f ) (qs − qdef f )3 ctnoi
Sig,id = −jω · 4KT · µCox Dptwg Moc Vt ( )·  − 3 ·
Lef f 1+qs +qdef f 0.395
 
1+qs +qdef f
12 2 144 2
(2.305)
Sig,id
c= p √ (2.306)
Sig · Sid

2.21.3 Gate Current Shot Noise

i2gs = 2q(Igcs + Igs ) (2.307)

i2gd = 2q(Igcd + Igd ) (2.308)
i2gb = 2qIgbinv (2.309)

52
Figure 4: TNOIMOD=1 shows good physical behavior at high and low Vds from sub-
threshold to strong inversion regions.

2.21.4 Resistor Noise

The noise associated with each parasitic resistors in BSIM6 are calculated
If RDSM OD = 1 then

i2RS 1
= 4kT · (2.310)
∆f Rsource
i2RD 1
= 4kT · (2.311)
∆f Rdrain

If RGAT EM OD = 1 then

i2RG 1
= 4kT · (2.312)
∆f Rgeltd

2.22 Self Heating Model

Effect of self heating is modeled by employing a thermal network consisting of ther-
mal resistance (Rth ) and capacitance (Cth ) as shown in Fig.5 . The voltage at thermal
node T gives the rise in temperature, which is added to the ambient temperature and

53
 Figure 5: Thermal Network for Self Heating Model.

all the temperature sensitive variables in the model are updated accordingly.
RT H0
Rth =
(W T H0 + W ef f ) · N F

Cth = CT H0 ∗ (W T H0 + W ef f ) · N F

3 Asymmetric MOS Junction Diode Models

3.1 Junction Diode IV Model

In BSIM6, there is only one diode model (DIOMOD=2 from BSIM4), which includes
resistance and breakdown. BSIM6 models the diode breakdown with current limiting
in both forward IJTHSFWD or IJTHDFWD and reverse operations XJBVS, XJBVD,
BVS, and BVD.

54
Source/Body Junction Diode The equations for the source-side diode are as fol-
lows:

h  Vbs  i
Ibs = Isbs exp − 1 · fbreakdown + Vbs · Gmin (3.1)
N JS · Vt
where Isbs is the total saturation current consisting of the components through the
gate-edge (Jsswgs) and isolation-edge sidewalls (Jssws) and the bottom junction (Jss),
Isbs = Asef f Jss (T ) + Psef f Jssws (T ) + Wef f cj · N F · Jsswgs (T ) (3.2)
where the calculation of the junction area and perimeter is discussed in section Layout-
Dependent Parasitics Models, and the temperature-dependent current density model is
given in Section Temperature Dependence of Junction Diode IV. The exponential term
in equation given below is linearized at both the limiting current IJTHSFWD in the
forward-bias mode and the limiting current IJTHSREV in the reverse-bias mode. In
(3.1), fbreakdown is given by
 (BV S + V ) 
bs
fbreakdown = 1 + XJBV S · exp − (3.3)
N JS · Vt
if XJBV S ≤ 0.0, it is reset to 1.0.

Drain/Body Junction Diode The equations for the drain-side diode are as follows:

h Vbd 
 i
Ibd = Isbd exp − 1 · fbreakdown + Vbd · Gmin (3.4)
N JD · Vt
where Isbs is the total saturation current consisting of the components through the
gate-edge (Jsswgs) and isolation-edge sidewalls (Jssws) and the bottom junction (Jss),
Isbd = Adef f Jsd (T ) + Pdef f Jsswd (T ) + Wef f cj · N F · Jsswgd (T ) (3.5)
where the calculation of the junction area and perimeter is discussed in Section Layout-
Dependent Parasitics Models, and the temperature-dependent current density model is
given in Section Temperature Dependence of Junction Diode IV. The exponential term
in (3.6) is linearized at both the limiting current IJTHDFWD in the forward-bias mode
and the limiting current IJTHDREV in the reverse-bias mode. In (3.1), fbreakdown is
given by
 ·(BV D + V ) 
bd
fbreakdown = 1 + XJBV D · exp − (3.6)
N JD · Vt
if XJBV D ≤ 0.0, it is reset to 1.0.

55
Total Junction Source/Drain Diode Including Tunneling Total diode current
including the carrier recombination and trap-assisted tunneling current in the space-
charge region is modeled by:

Ibs totle = Ibs

h  −Vbs V T SSW GS i
− Wef f cj · N F · Jtsswgs (T ) · exp ·
N JT SSW G(T ) · V tm0 V T SSW GS − Vbs
h  −Vbs V T SSW S  i
− Ps,def f Jtssws (T ) exp · −1
N JT SSW (T ) · V tm0 V T SSW S − Vbs
h  −Vbs V T SS  i
− As,def f Jtss (T ) exp − 1 + gmin · Vbs (3.7)
N JT S(T ) · V tm0 V T SS − Vbs

Ibd totle = Ibd

h  −Vbd V T SSW GD i
− Wef f cj · N F · Jtsswgd (T ) · exp ·
N JT SSW GD(T ) · V tm0 V T SSW GD − Vbd
h  −Vbd V T SSW D  i
− Pd,def f Jtsswd (T ) exp · −1
N JT SSW D(T ) · V tm0 V T SSW D − Vbd
h  −Vbd V T SD  i
− Ad,def f Jtsd (T ) exp − 1 + gmin · Vbd (3.8)
N JT D(T ) · V tm0 V T SD − Vbd

3.2 Junction Diode CV Model

Source and drain junction capacitances consist of three components: the bottom
junction capacitance, sidewall junction capacitance along the isolation edge, and sidewall
junction capacitance along the gate edge. An analogous set of equations are used for
both sides but each side has a separate set of model parameters.

Source/Body Junction Diode The source-side junction capacitance can be calcu-

lated by

Cbs = Asef f Cjbs + Psef f Cjbssw + Wef f cj · N F · Cjbsswg (3.9)

where Cjbs is the unit-area bottom S/B junciton capacitance, Cjbssw is the unit-length
S/B junction sidewall capacitance along the isolation edge, and Cjbsswg is the unit-length
S/B junction sidewall capacitance along the gate edge. The effective area and perimeters
in (3.9) are given in Section Layout-Dependent Parasitics Models.

56
Cjbs is calculated by
 !−M JS

Vbs Vbs
CJS(T ) · 1− if ≤ x0


P BS(T ) P BS(T )

Cjbs = " !# (3.10)
Vbs
−1

1
CJS(T ) · · 1 + M JS 1 + otherwise

 P BS
(1−x0 )M JS 1−x0


where the value of x0 is taken as 0.9.

Cjbssw is calculated by
 !−M JSW S

Vbs Vbs
CJSW S(T ) · 1− if ≤ x0


P BSW S(T ) P BSW S(T )

Cjbssw = " !#
Vbs

1 P BSW S(T )
−1
CJSW S(T ) · · 1 + M JSW S 1 + otherwise


(1−x0 )M JSW S 1−x0


(3.11)

where the value of x0 is taken as 0.9.

Cjbsswg is calculated by
 !−M JSW GS

Vbs Vbs
CJSW GS(T ) · 1− if ≤


P BSW GS(T ) P BSW GS(T )

Cjbsswg = " !#
Vbs

1 P BSW GS(T )
−1
CJSW GS(T ) · · 1 + M JSW GS 1 + otherwise


 (1−x0 )M JSW GS 1−x0

(3.12)

where the value of x0 is taken as 0.9.

Drain/Body Junction Diode The drain-side junction capacitance can be calculated

by

Cbd = Adef f Cjbd + Pdef f Cjbdsw + Wef f cj · N F · Cjbdswg (3.13)

57
where Cjbd is the unit-area bottom D/B junciton capacitance, Cjbdsw is the unit-length
D/B junction sidewall capacitance along the isolation edge, and Cjbdswg is the unit-
length D/B junction sidewall capacitance along the gate edge. The effective area and
perimeters in (3.13) are given in Section Layout-Dependent Parasitics Models.

Cjbd is calculated by
 !−M JD

Vbs Vbs
CJD(T ) · 1− if ≤ x0


P BD(T ) P BD(T )

Cjbd = " !# (3.14)
Vbs
−1

1
CJD(T ) · · 1 + M JD 1 + otherwise

 P BD
(1−x0 )M JD 1−x0


where the value of x0 is taken as 0.9.

Cjbdsw is calculated by
 !−M JSW S

Vbs Vbs
CJSW D(T ) · 1− if ≤ x0


P BSW D(T ) P BSW D(T )

Cjbdsw = " !#
Vbs

1 P BSW D(T )
−1
CJSW D(T ) · · 1 + M JSW D 1 + otherwise


(1−x0 )M JSW D 1−x0


(3.15)

where the value of x0 is taken as 0.9.

Cjbdswg is calculated by
 !−M JSW GD

Vbs Vbs
CJSW GD(T ) · 1− if ≤


P BSW GD(T ) P BSW GD(T )

Cjbdswg = " !#
Vbs

1 P BSW GD(T )
−1
CJSW GD(T ) · · 1 + M JSW GD 1 + otherwise


 (1−x0 )M JSW GD 1−x0

(3.16)

where the value of x0 is taken as 0.9.

58
 Figure 6: Definition for layout parameters.

4 Layout dependent Parasitics Models

4.1 Layout-Dependent Parasitics Models

BSIM6 provides a comprehensive and versatile geometry/layout-dependent parasitcs
model taken from BSIM4. It supports modeling of series (such as isolated, shared, or
merged source/ drain) and multi-finger device layout, or a combination of these two
configurations. This model has impact on every BSIM6 sub-models except the substrate
resistance network model. Note that the narrow-width effect in the per-finger device
with multi-finger configuration is accounted for by this model. A complete list of model
parameters and selectors can be found at the end.

4.1.1 Geometry Definition

Figure 6 schematically shows the geometry definition for various source/drain con-
nections and source/drain/gate contacts. The layout parameters shown in this figure
will be used to calculate resistances and source/drain perimeters and areas.

59
4.1.2 Model Formulation and Options

Effective Junction Perimeter and Area: In the following, only the source-side
case is illustrated. The same approach is used for the drain side. The effective junction
perimeter on the source side is calculated by
If (PS is given)
if (perMod=0)
Psef f =PS
else
Else
Psef f computed from NF, DWJ, geoMod, DMCG, DMCI, DMDG, DMCGT,
RSH, and MIN.
The effective junction area on the source side is calculated by
If (AS is given)
Asef f = AS
Else
Asef f computed from NF, DWJ, geoMod, DMCG, DMCI, DMDG, DMCGT,
RSH, and MIN.
In the above, Psef f and Asef f will be used to calculate junction diode IV and CV.
Psef f does not include the gate-edge perimeter.

Source/Drain Diffusion Resistance: The source diffusion resistance is calculated

by
If (number of sources NRS is given)
ELSE if (rgeoMod=0)
Source diffusion resistance Rsdif f is not generated.
Else
Rsdif f computed from NF, DWJ, geoMod, DMCG, DMCI, DMDG, DMCGT,
RSH, and MIN.
where the number of source squares NRS is an instance parameter. Similarly, the
drain diffusion resistance is calculated by
If (number of sources NRD is given)
ELSE if (rgeoMod=0)
Drain diffusion resistance Rddif f is not generated.
Else

60
 geomod End Source End drain Note
0 isolated isolated NF=Odd
1 isolated shared NF=Odd, Even
2 shared shared NF=Odd, Even
3 shared isolated NF=Odd, Even
4 isolated merged NF=Odd
5 shared merged NF=Odd, Even
6 merged isolated NF=Odd
7 merged shared NF=Odd, Even
8 merged merged NF=Odd
9 sha/iso shared NF=Even
10 shared sha/iso NF=Even

Table 1: geoMod options.

Rddif f computed from NF, DWJ, geoMod, DMCG, DMCI, DMDG, DMCGT,
RSH, and MIN.

Gate Electrode Resistance: The gate electrode resistance with multi-finger config-
uration is modeled by
 
Wef f ci
RSHG · XGW + 3N GCON
Rgeltd =   (4.1)
N GCON · Ldrawn − XGL · N F

Option for Source/Drain Connections: Table 1 lists the options for source/drain
connections through the model selector geoMod. For multi-finger devices, all inside
S/D diffusions are assumed shared.

Option for Source/Drain Contacts: Table 2 lists the options for source/drain
contacts through the model selector rgeoMod.

61
 rgeoMod End-source contact End-drain contact
0 No Rsdif f No Rddif f
1 wide wide
2 wide point
3 point wide
4 point point
5 wide merged
6 point merged
7 merged wide
8 merged point

Table 2: rgeoMod options.

5 Temperature dependence Models

5.1 Temperature Dependence Model

Accurate modeling of the temperature effects on MOSFET characteristics is impor-
tant to predict circuit behavior over a range of operating temperatures (T). The oper-
ating temperature might be different from the nominal temperature (TNOM) at which
the BSIM6 model parameters are extracted. This chapter presents the BSIM6 tempera-
ture dependence models for threshold voltage, mobility, saturation velocity, source/drain
resistance, and junction diode IV and CV.

62
5.1.1 Length Scaling of Temperature parameters

 
1
UT E = U T E · 1 + U T EL (5.1)
Lef f
 
1
U A1 = U A1 · 1 + U A1L (5.2)
Lef f
 
1
U D1 = U D1 · 1 + U D1L (5.3)
Lef f
 
1
AT = AT · 1 + AT L (5.4)
Lef f
 
1
P T W GT = P T W GT · 1 + P T W GT L (5.5)
Lef f
(5.6)

5.1.2 Temperature Dependence of Threshold Voltage

The temperature dependence of Vth is modeled by

! KT 1EXP
 T 
Vth (T ) = Vth (T N OM ) + KT 1i + KT 2i · Vbref f · −1
T N OM
T  
Vf b (T ) = Vf b (T N OM ) − KT 1 · −1 (5.7)
T N OM
V F BSDOF F (T ) = V F BSDOF F (T N OM ) · [1 + T V F BSDOF F · (T − T N OM )]
 T 
N F ACT OR(T ) = N F ACT OR(T N OM ) + T F ACT OR · −1 (5.8)
T N OM
 T 
ET A0(T ) = ET A0(T N OM ) + T ET A0 −1 (5.9)
T N OM

63
5.1.3 Temperature Dependence of Mobility

U 0(T ) = U 0(T N OM ) · (T /T N OM )U T E (5.10)

U A(T ) = U A(T N OM )[1 + U A1 · (T − T N OM )] (5.11)
U C(T ) = U C(T N OM )[1 + U C1 · (T − T N OM )] (5.12)
U D(T ) = U D(T N OM ) · (T /T N OM )U D1 (5.13)
U CS(T ) = U CS(T N OM ) · (T /T N OM )U CST E (5.14)
(5.15)

5.1.4 Temperature Dependence of Saturation Velocity

V SAT (T ) = V SAT (T N OM ) · (T /T N OM )−AT (5.16)

5.1.5 Temperature Dependence of LDD Resistance

rdstemp = (T /T N OM )P RT (5.17)
(5.18)

RDSMOD = 0 (internal source/drain LDD resistance)

RDSW (T ) = RDSW (T N OM ) · rdstemp (5.19)

RDSW M IN (T ) = RDSW M IN (T N OM ) · rdstemp (5.20)

RDSMOD = 1 (external source/drain LDD resistance)

RDW (T ) = RDW (T N OM ) · rdstemp (5.21)

RDW M IN (T ) = RDW M IN (T N OM ) · rdstemp) (5.22)
RSW (T ) = RSW (T N OM ) · rdstemp (5.23)
RSW M IN (T ) = RSW M IN (T N OM ) · rdstemp (5.24)

64
5.1.6 Temperature Dependence of Junction Diode IV

• Source-side diode The source-side diode is turned off if both Asef f and Psef f
are zero. Otherwise, the source-side saturation current is given by
Isbs = Asef f Jss (T ) + Psef f Jssws (T ) + Wef f cj · N F · Jsswgs (T ) (5.25)
where
 
Eg (T N OM ) Eg (T ) T
vt (T N OM )
− vt (T )
+ XT IS · ln T N OM !
Jss (T ) = JSS(T N OM ) · exp
N JS
 
Eg (T N OM ) Eg (T ) T
vt (T N OM )
− vt (T )
+ XT IS · ln T N OM !
Jssws (T ) = JSSW S(T N OM ) · exp
N JS
 
Eg (T N OM ) Eg (T ) T
kb ·T N OM
− kb ·T
+ XT IS · ln T N OM !
Jsswgs (T ) = JSSW GS(T N OM ) · exp
N JS
(5.26)
where Eg is given in Temperature Dependences of Eg and ni.
• Drain-side diode The drain-side diode is turned off if both Asef f and Psef f
arezero. Otherwise, the drain-side saturation current is given by
Isbd = Adef f Jsd (T ) + Pdef f Jsswd (T ) + Wef f cj · N F · Jsswgd (T ) (5.27)
where
 
Eg (T N OM ) Eg (T )
kb ·T N OM
− kb ·T
+ XT ID · ln T NTOM !
Jsd (T ) = JSD(T N OM ) · exp
N JD
 
Eg (T N OM ) Eg (T ) T
kb ·T N OM
− kb ·T
+ XT ID · ln T N OM !
Jsswd (T ) = JSSW D(T N OM ) · exp
N JD
 
Eg (T N OM ) Eg (T ) T
kb ·T N OM
− kb ·T
+ XT ID · ln T N OM !
Jsswgd (T ) = JSSW GD(T N OM ) · exp
N JD
(5.28)

65
5.1.7 Temperature Dependence of Junction Diode CV

– Source-side diode: The temperature dependences of zero-bias unit-length/area

junction capacitances on the source side are modeled by
CJS(T ) = CJS(T N OM ) + T CJ · (T − T N OM ) (5.29)
CJSW S(T ) = CJSW S(T N OM ) + T CJSW · (T − T N OM(5.30)
)
CJSW GS(T ) = CJSW GS(T N OM ) + T CJSW G · (T − T N OM )
(5.31)
The temperature dependences of the built-in potentials on the source side
are modeled by
P BS(T ) = P BS(T N OM ) − T P B · (T − T N OM ) (5.32)
P BSW S(T ) = P BSW S(T N OM ) − T P BSW · (T − T N OM(5.33)
)
P BSW GS(T ) = P BSW GS(T N OM ) − T P BSW G · (T − T N OM )
(5.34)

– Drain-side diode: The temperature dependences of zero-bias unit-length/area

junction capacitances on the drain side are modeled by
CJS(T ) = CJS(T N OM )[1 + T CJ · (T − T N OM )] (5.35)
CJSW S(T ) = CJSW S(T N OM ) + T CJSW · (T − T N OM )(5.36)
CJSW GS(T ) = CJSW GS(T N OM )[1 + T CJSW G · (T − T N OM )]
(5.37)
The temperature dependences of the built-in potentials on the drain side are
modeled by
P BD(T ) = P BD(T N OM ) − T P B · (T − T N OM ) (5.38)
P BSW D(T ) = P BSW D(T N OM ) − T P BSW · (T − T N OM(5.39)
)
P BSW GD(T ) = P BSW GD(T N OM ) − T P BSW G · (T − T N OM )
(5.40)

66
• trap-assisted tunneling (TAT) and recombination current
s !
JT W EF F
Jtsswgs (T ) = Jtsswgs (T N OM ) · +1
Wef f cj
" !#
−Eg (T N OM ) T
· exp · Xtsswgs · 1 − (5.41)
kb T T N OM
" !#
−Eg (T N OM ) T
Jtssws (T ) = Jtssws (T N OM ) · exp · Xtssws · 1 −
kb T T N OM
" !#
−Eg (T N OM ) T
Jtss (T ) = Jtss (T N OM ) · exp · Xtss · 1 −
kb T T N OM
s !
JT W EF F
Jtsswgd (T ) = Jtsswgd (T N OM ) · +1
Wef f cj
" !#
−Eg (T N OM ) T
· exp · Xtsswgd · 1 − (5.42)
kb T T N OM
" !#
−Eg (T N OM ) T
Jtsd (T ) = Jtsd (T N OM ) · exp · Xtsd · 1 −
kb T T N OM
h T
i
N JT SSW G(T ) = N JT SSW G(T N OM ) · 1 + T N JT SSW G −1
T N OM
h T
i
N JT SSW (T ) = N JT SSW (T N OM ) · 1 + T N JT SSW −1
T N OM
h T
i
N JT S(T ) = N JT S(T N OM ) · 1 + T N JT S −1
T N OM
h T
i
N JT SSW GD(T ) = N JT SSW GD(T N OM ) · 1 + T N JT SSW GD −1
T N OM
h T
i
N JT SSW D(T ) = N JT SSW D(T N OM ) · 1 + T N JT SSW D −1
T N OM
h T
i
N JT SSW D(T ) = N JT SSW D(T N OM ) · 1 + T N JT SSW D −1
T N OM
h T
i
N JT SD(T ) = N JT SD(T N OM ) · 1 + T N JT SD −1
T N OM
(5.43)

67
5.1.8 Temperature Dependences of Eg and ni

• Energy-band gap of channel (Eg ): The temperature dependence of Eg is modeled

by

T BGASU B × T nom2
Eg0 = BG0SU B − (5.44)
T nom + T BGBSU B
T BGASU B × T 2
Eg = BG0SU B − (5.45)
T + T BGBSU B

• Intrinsic carrier concentration of non-silicon channel (ni )

!(3/2) !
T Eg Eg
ni = N I0SU B × × exp − kT (5.46)
T nom 2 kT nom
q
2q

6 Stress effect Model Development

6.1 Stress Effect Model

CMOS feature size aggressively scaling makes shallow trench isolation(STI) very pop-
ular active area isolation process in advanced technologies. Recent years, strain channel
materials have been employed to achieve high device performance. The mechanical stress
effect induced by these process causes MOSFET performance function of the active area
size(OD: oxide definition) and the location of the device in the active area. And the
necessity of new models to describe the layout dependence of MOS parameters due to
stress effect becomes very urgent in advance CMOS technologies. Influence of stress
on mobility has been well known since the 0.13um technology. The stress influence on
saturation velocity is also experimentally demonstrated. Stress-induced enhancement
or suppression of dopant diffusion during the processing is reported. Since the doping
profile may be changed due to different STI sizes and stress, the threshold voltage shift
and changes of other second-order effects, such as DIBL and body effect, were shown
in process integration. BSIM4 considers the influence of stress on mobility, velocity
saturation, threshold voltage, body effect, and DIBL effect.

68
 Figure 7: the typical layout of a MOSFET

6.1.1 Stress Effect Model Development

Experimental analysis show that there exist at least two different mechanisms within
the influence of stress effect on device characteristics. The first one is mobility-related
and is induced by the band structure modification. The second one is Vth-related as a
result of doping profile variation. Both of them follow the same 1/LOD trend but reveal
different L and W scaling. We have derived a phenomenological model based on these
findings by modifying some parameters in the BSIM model. Note that the following
equations have no impact on the iteration time because there are no voltage-controlled
components in them.

Mobility-related Equations: This model introduces the first mechanism by adjust-

ing the U0 and Vsat according to different W, L and OD shapes. Define mobility relative
change due to stress effect as :
µef f
ρµef f = ∆µef f /µef f o = (µef f − µef f o )/µef f o = −1 (6.1)
µef f o

So,
µef f
= 1 + ρµef f (6.2)
µef f o

Figure 7 shows the typical layout of a MOSFET on active layout surrounded by STI
isolation. SA, SB are the distances between isolation edge to Poly from one and the other
side, respectively. 2D simulation shows that stress distribution can be expressed by a
simple function of SA and SB. Assuming that mobility relative change is propotional
to stress distribution. It can be described as function of SA, SB(LOD effect), L, W, and

69
 Figure 8: Stress distribution within MOSFET channel using 2D simulation

T dependence:
KU 0

ρµef f = · Inv sa + Inv sb (6.3)
Kstressu 0
where:
1
Inv sa = (6.4)
SA + 0.5 · Ldrawn
1
Inv sb = (6.5)
SB + 0.5 · Ldrawn
LKU 0
Kstress u0 = 1+
(Ldrawn + XL)LLODKU 0
W KU 0
+
(Wdrawn + XW + W LOD)W LODKU 0
!
P KU 0
+
(Ldrawn + XL)LLODKU 0 · (Wdrawn + XW + W LOD)W LODKU 0
!!
T emperature
× 1 + T KU 0 · −1 (6.6)
T N OM

So that:
1 + ρµef f (SA, SB)
µef f = µef f o (6.7)
1 + ρµef f (SAref , SBref )
1 + KV SAT · ρµef f (SA, SB)
νsattemp = νsattempo (6.8)
1 + KV SAT · ρµef f (SAref , SBref )

70
 and SAref , SBref are reference distances between OD edge to poly from one and the
other side.

Vth-related Equations: Vth0 (threshold voltage without stress effect), K2 and ETA0
are modified to cover the doping profile change in the devices with different LOD. They
use the same 1/LOD formulas as shown in earlier sections, but different equations for
W and L scaling:

KV T H0

V T H0 = V T H0original + · Inv sa + Inv sb − Inv saref − Inv sbref
Kstress vth0
ST K2

K2 = K2original + LODK2
· Inv sa + Inv sb − Inv saref − Inv sbref
Kstress vth0
ST ET A0

ET A0 = ET A0original + · Inv sa + Inv sb − Inv sa ref − Inv sb ref
Kstress vth0LODET A0
(6.9)

where:
1
Inv saref = (6.10)
SAref + 0.5 · Ldrawn
1
Inv sbref = (6.11)
SBref + 0.5 · Ldrawn
LKV T H0
Kstress vth0 = 1+
(Ldrawn + XL)LLODKV T H
W KV T H0
+
(Wdrawn + XW + W LOD)W LODKV T H
!
P KV T H0
+ (6.12)
(Ldrawn + XL)LLODKV T H · (Wdrawn + XW + W LOD)W LODKV T H

Multiple Finger Device: For multiple finger device, the total LOD effect is the
average of LOD effect to every finger. That is(see Figure 9) for the layout for multiple

71
 Figure 9: Layout of multiple finger MOSFET

finger device):

N F −1
1 X 1
Inv sa = (6.13)
N F i=0 SA + 0.5 · Ldrawn + i · (SD + Ldrawn )
N F −1
1 X 1
Inv sb = (6.14)
N F i=0 SB + 0.5 · Ldrawn + i · (SD + Ldrawn )
(6.15)

6.1.2 Effective SA and SB for Irregular LOD

General MOSFET has an irregular shape of active area shown in Figure 10 To fully
describe the shape of OD region will require additional instance parameters. However,
this will result in too many parameters in the net lists and would massively increase
the read-in time and degrade the readability of parameters. One way to overcome this
difficulty is the concept of effective SA and SB similar to [10]. Stress effect model as
described earlier allows an accurate and efficient layout extraction of effective SA and

72
Figure 10: A typical layout of MOS devices with more instance parameters (swi, sai and
sbi) in addition to the traditional L and W

SB while keeping fully compatibility of the LOD model. They are expressed as:
n
1 X swi 1
= · (6.16)
SAef f + 0.5 · Ldrawn i=1
Wdrawn sai + 0.5 · Ldrawn
n
1 X swi 1
= · (6.17)
SBef f + 0.5 · Ldrawn i=1
Wdrawn sbi + 0.5 · Ldrawn
(6.18)

7 Well Proximity Effect Model

8 Well Proximity Effect Model

Retrograde well profiles have several key advantages for highly scaled bulk comple-
mentary metal oxide semiconductor(CMOS) technology. With the advent of high-energy
implanters and reduced thermal cycle processing, it has become possible to provide a
relatively heavily doped deep nwell and pwell without affecting the critical device-related
doping at the surface. The deep well implants provide a low resistance path and sup-
press parasitic bipolar gain for latchup protection, and can also improve soft error rate

73
and noise isolation. A deep buried layer is also key to forming triple-well structures
for isolated-well NMOSFETs. However, deep buried layers can affect devices located
near the mask edge. Some of the ions scattered out of the edge of the photoresist are
implanted in the silicon surface near the mask edge, altering the threshold voltage of
those devices [11]. It is observed a threshold voltage shifts of up to 100 mV in a deep
boron retrograde pwell, a deep phosphorus retrograde nwell, and also a triple-well imple-
mentation with a deep phosphorus isolation layer below the pwell over a lateral distance
on the order of a micrometer [11]. This effect is called well proximity effect. BSIM6
considers the influence of well proximity effect on threshold voltage, mobility, and body
effect. This well proximity effect model is developed by the Compact Model Council
[12].

8.1 Well Proximity Effect Model

Experimental analysis [11] shows that well proximity effect is strong function of
distance of FET from mask edge, and electrical quantities influenced by it follow the
same geometrical trend. A phenomenological model based on these findings has been
developed by modifying some parameters in the BSIM model. Note that the following
equations have no impact on the iteration time because there are no voltage controlled
components in them. Well proximity affects threshold voltage, mobility and the body
effect of the device. The effect of the well proximity can be described through the
following equations :
If SCA, SCB, SCC are given then WPE is given by (8.1), otherwise it is given by (8.2)

V th0 =V th0org + KV T H0W E · (SCA + W EB · SCB + W EC · SCC)

K2 =K2org + K2W E · (SCA + W EB · SCB + W EC · SCC)
µef f =µef f,org · (1 + KU 0W E · (SCA + W EB · SCB + W EB · SCC)) (8.1)

74
 W drn = W/N F
T 1 = SC + W drn
T 2 = 1.0/SCREF
T 3 = exp(−10.0 · SC · T 2)
T 4 = exp(−10.0 · T 1 · T 2)
T 5 = exp(−20.0 · SC · T 2)
T 6 = exp(−20.0 · T 1 · T 2)
SCREF · SCREF
LOCALSCA =
SC · T 1
(0.1 · SC + 0.01 · SCREF ) · T 3 − (0.1 · T 1 + 0.01 · SCREF ) · T 4
LOCALSCB =
W drn
(0.05 · SC + 0.0025 · SCREF ) · T 5 − (0.05 · T 1 + 0.0025 · SCREF ) · T 6
LOCALSCC =
W drn
V th0 = V th0org + KV T H0W E · (LOCALSCA + W EB · LOCALSCB + W EC · LOCALSCC )
K2 = K2org + K2W E · (LOCALSCA + W EB · LOCALSCB + W EC · LOCALSCC )
µef f = µef f,org · (1 + KU 0W E · (LOCALSCA + W EB · LOCALSCB + W EB · LOCALSCC ))
(8.2)

where SCA, SCB, SCC are instance parameters that represent the integral of the
first/second/third distribution function for scattered well dopant. The guidelines for cal-
culating the instance parameters SCA, SCB, SCC have been developed by the Compact
Model Council which can be found at the CMC website [12].

75
9 C-V Model
Inversion Charge : Total inversion charge (excluding velocity saturation, CLM and poly
depletion) can be expressed explicitly in terms of normalized charge densities at source and
drain sides as follows,
Z L
QI = W · Qi dx (9.1)
0
Z 1
= −W L · Cox · Vt 2.nq .q dξ (9.2)
0

Z 1
QI
− = qI = 2.nq · q dξ (9.3)
W L · Cox Vt 0
x
Here ξ = L. Inversion charge density is normalized to −2.nq .Cox .Vt and voltages to Vt . From
(2.223),
Wef f dq
Ids = −2 · nq · µef f · · Cox · nVt2 · (2q + 1) (9.4)
Lef f dξ
Wef f
Normalizing current with 2 · nq · µef f · Lef f · Cox · nVt2 ,

dq
i = −(2q + 1) (9.5)
dξ
which gives dξ = − (2q+1)
i dq = − (qs −qd(2q+1)
)(1+qs +qd ) . Substituting in (9.3)
Z qd
2nq
qI = − q(2q + 1) dq (9.6)
(qs − qd )(1 + qs + qd ) qs
" #
2nq 2 3 1
=− (qd − qs 3 ) + (qd 2 − qs 2 ) (9.7)
(qs − qd )(1 + qs + qd ) 3 2
on rearranging,
" #
1 (qs − qd )2
qI = n q · qs + qd + · (9.8)
3 1 + qs + qd

Bulk Charge: Bulk charge density is given as

Qb = −Cox · (VG − VF B − ψS ) − Qi (9.9)

(9.10)

76
using charge linearization
!
1
Qb = −Cox · (VG − VF B − ψP ) − Qi 1− (9.11)
nq

Total bulk charge,

Z L
QB = W · Qb dx (9.12)
0
" ! Z #
1
1 Qi
= −W L · Cox · VG − VF B − ψP + 1− · dξ (9.13)
nq 0 Cox

Normalizing the bulk charge to −W.L.Cox .Vt ,

Z 1
qB = vg − vf b − ψp − 2(nq − 1) · q dξ (9.14)
0

−(2q+1)
We know that ids = −(2q + 1) dq
dξ with ids given by (2.231). Thus dξ = − ids dq,
qd
2(nq − 1)
Z
qB = vg − vf b − ψp + · q(2q + 1) dq (9.15)
ids qs
Z qd " 3 #
2(nq − 1) 2q q2
= vg − vf b − ψp + + (9.16)
(qs − qd )(1 + qs + qd ) qs 3 2
" #
2(nq − 1) 2 1
= vg − vf b − ψp + · (qd − qs )(qd2 + qs2 + qs .qd ) + · (qd − qs )(qd + qs )
(qs − qd )(1 + qs + qd ) 3 2
(9.17)

which on rearrangement becomes,

" #
1 (qs − qd )2
qB = vg − vf b − ψp − (nq − 1) qs + qd + · (9.18)
3 1 + qs + qd

Bulk charge with poly depletion effect :

" ! # " #
1 ∆q 2 4 1 2 1 (q s − q d )2
qB = A + B + . 3 · · C 2 + P.Q · + − n q . qs + qd + ·
3 C 8 1 + qs + qd γg2 3 1 + qs + qd
(9.19)

77
where
s
1 vg − vf b − ψp + 2.qs
P = + (9.20)
4 γg2
s
1 vg − vf b − ψp + 2.qd
Q= + (9.21)
4 γg2
vg − vf b − ψp + 2.qs
A= r (9.22)
v −v −ψ +2.qs
1 + 2. 14 + g f b γ 2 p
g

vg − vf b − ψp + 2.qd
B= r (9.23)
v −v −ψ +2.qs
1 + 2. 14 + g f b γ 2 p
g
s s
1 vg − vf b − ψp + 2.qs 1 vg − vf b − ψp + 2.qd
C= + 2
+ + (9.24)
4 γg 4 γg2

Source and Drain Charges

" ! 2 #
nq 1 4 6 qs − qdef f
Qs = 2 · qs + qdef f + · 1 + · qs + · qdef f (9.25)
3 2 5 5 1 + qs + qdef f
" ! 2 #
nq 1 6 4 qs − qdef f
Qd = qs + 2 · qdef f + · 1 + · qs + · qdef f (9.26)
3 2 5 5 1 + qs + qdef f

(9.27)

Quantum Mechanical Effect

inv ADOS · (1.9 · 10−9 )

XDC = h i0.7∗BDOS (9.28)
Qi +ET AQM ·QB
1+ QM 0

inv 3.9 · 0
Cox = inv (9.29)
3.9 XDC
T OXP · EP SROX + ratio

78
 Intrinsic Charge expressions:

inv
W LCOXV tinv = N F · W act · Lact · Cox · nV t (9.30)
 
0 · EP SROX
QBi = −N F · W act · Lact · · nV t · Qb (9.31)
T OXP
QSi = −W LCOXV tinv · Qs (9.32)
QDi = −W LCOXV tinv · Qd (9.33)
QGi = QSi + QDi + QBi (9.34)

Bias-dependent overlap capacitance model

An accurate overlap capacitance model is essential. This is especially true for the drain
side where the effect of the capacitance is amplified by the transistor gain. The overlap
capacitance changes with gate to source and gate to drain biases. In LDD MOSFETs a
substantial portion of the LDD region can be depleted, both in the vertical and lateral
directions. This can lead to a large reduction of the overlap capacitance. This LDD
region can be in accumulation or depletion. We use a single equation for both regions by
using such smoothing parameters as Vgs,overlap and Vgd,overlap for the source and drain side,
respectively. Unlike the case with the intrinsic capacitance, the overlap capacitances are
reciprocal. In other words, Cgs,overlap = Csg,overlap and Cgd,overlap = Cdg,overlap .
The bias-dependent overlap capacitance model in BSIM6 is adopted from BSIM4.
The overlap charge is given by:
Qgs,ov
= CGSO · Vgs +
N F · Wef f CV
" r !#
CKAP P AS 4Vgs,overlap
CGSL · Vgs − Vf bsd − Vgs,overlap − 1− −1
2 CKAP P AS
(9.35)

79
 Qgd,ov
= CGDO · Vgd +
N F · Wef f CV
" r !#
CKAP P AD 4Vgd,overlap
CGDL · Vgd − Vf bsd − Vgd,overlap − 1− −1
2 CKAP P AD
(9.36)
 
1
q
Vgs,overlap = Vgs − Vf bsd + δ1 − (Vgs − Vf bsd + δ1 )2 + 4δ1 (9.37)
2
 
1
q
2
Vgd,overlap = Vgd − Vf bsd + δ1 − (Vgd − Vf bsd + δ1 ) + 4δ1 (9.38)
2
δ1 = 0.02V (9.39)

Outer Fringing Capacitance

The fringing capacitance consists of a bias-independent outer fringing capacitance and
a bias-dependent inner fringing capacitance. Only the bias-independent outer fringing
capacitance is modeled. If CF is not given then outer fringe capacitance is calculated
as
2 · EP SROX · 0 0.4e − 6
CF = · ln[CF RCOEF F · (1 + )] (9.40)
π T OX

80
10 Parameter Extraction Procedure
The objective of this section is to provide guidelines for the extraction of the main
model parameters. The procedure is structured in such a way that parameters linked to
specific psychical phenomena are extracted from analyses where these effects are promi-
nent. Although parameter extraction is not always a straight-forward procedure, the
aim is to minimize the effort invested and the number of the essential loops performed.
If all the steps of the described procedure are followed then a global model card is
obtained which means that the model can be used across the entire width/length plane
of the technology. If a local fitting is targeted, then only the parameters of Section 10.1
need to be extracted for each DUT. However, in that case binning is necessary if the
model card is to be used for the entire geometry range of the technology. Irrespectively
of the choice between global and local fitting, different model cards should be extracted
for nmos and pmos devices or for different technologies.
Before proceeding to the extraction of any parameter, it is very important that
TNOM is set to the value of the temperature at which the measurements were car-
ried out. Also, it is recommended that if they are available, the values of the process
parameters are provided. The most common process parameters are shown in Table 3.

Parameter Name Physical Description

EPSROX Relative Gate Dielectric Constant
EPSRSUB Relative Dielectric Constant of the Channel
TOXE Electrical Gate Equivalent Oxide Thickness
TOXP or DTOX Physical Gate Equivalent Oxide Thickness
NDEP Channel Doping Concentration
NGATE Gate Doping Concentration
NSD S/D Doping Concentration
XJ S/D Jucntion Depth
XW/XL Channel W/L Offset due to Mask/Etch Effect

Table 3: Process parameters which are recommended to be provided before parameter

extraction.

81
10.1 Extraction of Geometry Independent Parameters
The first part of the model parameter extraction procedure is to extract the parame-
ters that are related to the main physical phenomena, which define transistor’s behavior,
and are also geometry independent. For that, a wide and long channel device should
be chosen. At this point, WWIDE and LLONG parameters must be assigned to the
values of the width and length of this large chosen DUT. This ensures that once the
behavior of the long/wide channel device is fitted, it cannot be further affected by the
values scaling parameters that will be extracted in the next steps.

10.1.1 Gate Capacitance CGG vs. VG Analysis @ VS = 0 V , VD = 0 V &

VB = 0 V

At this step process parameters and parameters related to quantum mechanical effect
are extracted. Even if values have been already assigned to process parameters, a fine
tuning should be made in order to fit accurately the electrical behavior of the device.
From CGG vs. VG analysis the following process parameters can be extracted: NDEP,
TOXE, VFB and NGATE. Each of these parameters affects a different region or in
a different way the CGG capacitance, so they should be extracted accordingly. More
specifically:

• VFB is defining the flat-band voltage of the device and it can be extracted by
studying the region from depletion till the onset of strong-inversion.

• NDEP is affecting CGG in the depletion region. If possible, NDEP, which defines
the doping level, is better to be extracted from CGB vs. VG analysis (S and D
terminals are grounded).

• TOXE is affecting the deep accumulation and strong-inversion regions.

• NGATE is related to the poly-silicon depletion effect, so it affects the slope of CGG
in the strong-inversion region.

Furthermore, the value of COX is affected by the Quantum Mechanical effect. So, the
parameters: ADOS, BDOS, QM0 and ETAQM are also extracted from CGG vs. VG
analysis, when focusing at the slope of CGG at the onset of the strong-inversion region.

82
10.1.2 Drain Current ID vs. VG Analysis @ VD = [VD,lin , VD,sat ], VS = 0 V &
VB = 0 V

In this step, the VG dependence of the drain current - ID , is extracted. Different

parameters are extracted in two different regions of operation, namely linear mode (i.e.
VD  VG − VT H ) and saturation (i.e. VD  VG − VT H ). It is very important that during
0 00
extraction in this step, both ID and the transconductance - gm (even gm and gm ) are
extracted at once.

Linear Mode

• Focusing in weak-inversion region (ID vs. VG characteristic when y-axis is in loga-

rithmic scale), NFACTOR, which is related to the sub-threshold slope of the ID ,
can be extracted. Furthermore, a fine tuning of the NDEP and VFB parameters
is performed. In case the values of NDEP and VFB obtained during the fitting
of ID vs. VG characteristic differ much from those obtained during the fitting of
CGG vs. VG characteristic (Section 10.1.1), parameters NDEPCV and VFBCV
can be used for dynamic operation (CV) and NDEP and VFB for static operation
(IV). In general, using different values for NDEP and NDEPCV for IV and CV
operation is not recommended unless necessary.

• From strong-inversion region, the mobility U0, the parameter for the effective field
ETAMOB, the parameters related to the effect of mobility reduction due to vertical
field UA and EU and the parameters for the coulomb scattering effect UD and
UCS, are extracted. Furthermore, the parameters for S/D series resistances are
also extracted under the same bias conditions. If RDSMOD = 0 (internal S/D
series resistances), RDSW is extracted. Otherwise, RSW and RDW are extracted.

Saturation

• From weak-inversion region (ID vs. VG characteristic when y-axis is in logarithmic

scale), CDSCD paramerer, which is linked to the dependence of the sub-threshold
slope on drain bias, is extracted.

• Focusing in strong-inversion region, the parameters that are connected to the ve-
locity saturation effect, namely VSAT, PSAT, PTWG and PSATX, can be ex-
tracted. PSATX does need to be changed.

83
Finally, from accumulation to depletion region, in both linear mode and saturation, the
parameters related to GIDL effect are extracted. First, the selector GIDLMOD should
be set to 1 to activate GIDL/GILS currents and then the parameters AGIDL, BGIDL,
CGIDL and EGIDL are extracted. Ideally GIDL and GILS currents should be equal,
so it is sufficient to extract AGIDL, BGIDL, CGIDL and EGIDL parametrers. But
in case GIDL and GISL currents differ, then parameters AGISL, BGISL, CGISL and
EGISL can also be used.

10.1.3 Gate Current IG vs. VG Analysis @ various VD , VS = 0 V & VB = 0 V

From IG vs. VG analysis, parameters related to the gate current can be extracted.
First, the tunneling components should be activated by setting to 1 the selectors IGC-
MOD and IGBMOD. Different parameters are extracted in different regions of oper-
ation and more specifically:

Accumulation to weak-inversion Region

• AIGBACC, BIGBACC, CIGBACC and NIGBACC, which are linked to the

gate-to-substrate current component determined by ECB.

• AIGS, BIGS and CIGS, which are linked to the tunneling current between the
gate and the source diffusion region and AIGD, BIGD and CIGD, which are
linked to the tunneling current between the gate and the drain diffusion region.

• DLCIG and DLCIGD, which are linked to the S/D overlap length for IGS and
IGD respectively.

Weak to strong-inversion Region

• AIGBINV, BIGBINV, CIGBINV, EIGBINV and NIGBINV, which are linked

to the gate-to-substrate current component determined by EVB.

• AIGC, BIGC, CIGC, NIGC and PIGCD, which are linked to the gate-to-
channel current. PIGCD is expressing the VD dependence of gate-to-channel cur-
rent.

84
10.1.4 Drain Current ID vs. VD Analysis @ various VG , VS = 0 V & VB = 0 V
0
In this step, both ID vs. VD and output conductance - gds (even gds ) vs. VD char-
acteristics are studied at once. Different effects impact both the characteristics, so the
parameters related to those effects are extracted. In detail,

• DELTA, which is a smoothing factor for the transition between VDS and VDS,sat .

• PDITS and PDITSD, linked to DITS effect.

• PCLM, PCLMG and FPROUT linked to the CLM effect.

• PDIBLC, linked to the impact of DIBL effect on Rout .

• PVAG, linked to the VG dependence on Early voltage.

10.1.5 Gate Capacitance CGG vs. VG Analysis @ VDS 6= 0 V & VB = 0 V

Velocity saturation (VS) and channel length modulation (CLM) effects not only
affect the static behavior of the transistor but the dynamic as well. The extraction of
VSAT and PCLM from ID vs. VG and ID vs. VD characteristics should be sufficient in
order to capture these effects for CV operation. To verify that, CGG vs. VG characteristic
for different VDS 6= 0 V , from linear mode to saturation must be studied. If different
values for VSAT and PCLM are necessary for accurate fitting of the CV behavior at
different VD biases, then VSATCV and PCLMCV can be used.

10.1.6 Drain Current ID vs. VG Analysis @ VD = [VD,lin , VD,sat ] & various VB

In this step almost the same procedure as in Section 10.1.2 will be repeated in order
to extract the parameters that are linked to the body effect. Similar to Section 10.1.2,
it is also very important that during the extraction in this step both ID and gm are
studied at once.

Linear Mode

• Focusing in weak-inversion region, CDSCB, which is linked to the VB (or VS )

dependence of the sub-threshold slope, is extracted. Also K2, which is linked to the
VT H shift due to vertical non-uniform doping, is extracted in the same region.

85
 • In strong-inversion region, UC, which is linked to the VB (or VS ) dependence of
mobility, is extracted. The parameter for VB (or VS ) dependence of S/D series
resistances, PRWB, is also extracted under the same bias conditions.

Saturation

• In strong-inversion region, the parameter that is connected to VB (or VS ) dependence

of the velocity saturation effect, i.e. PSATB, is extracted.

In order to validate that the values of the parameters, which are linked to VB (or VS )
dependencies, are correctly extracted, it is useful to check ID vs. VD and gds vs. VD
characteristics @ various VG & VB 6= 0 V (or VS 6= 0 V ) and, if needed, to fine tune the
values of the parameters.

10.1.7 Fitting Verification

When all the extraction steps of this part have been performed, the fitting of the
model should be checked for all the analyses carried out up to this point. Parameters
can be fine tuned for better fitting in all regions.

10.2 Extraction of Short Channel Effects & Length Scaling

Parameters
Once the behavior of the wide/long channel device has been accurately modeled, the
next step is the extraction of the parameters that are either related to short channel
effects or express the different length dependencies. So at this part, devices across the
entire length range of the technology, from the shortest to the longest one, are studied
simultaneously. In order to avoid the impact of narrow channel effects or of the width
dependencies these devices should have the same wide channel. The extraction that
is carried out follows the same flow as in Section 10.1, but now a set of devices with
constant wide channel but different channel lengths is used.

86
10.2.1 Gate Capacitance CGG vs. VG Analysis @ VS = 0 V , VD = 0 V &
VB = 0 V

In this step, parameters related to overlap and fringing capacitances as well as those
that are linked to the length dependence of doping concentration and flat-band voltage
are extracted. More specifically:

• NDEPL1, NDEPLEXP1, NDEPL2 and NDEPLEXP2, which are the length

scaling parameters for the doping concentration, are extracted from CGG in the
depletion region. If possible, it is recommended that those parameters are extracted
from CGB vs. VG analysis (S and D terminals are grounded).
• Extraction of parameters related to overlap and fringing capacitances is carried out
by studying the entire range of VG bias of CGG vs. VG characteristic. These param-
eters are: CGSO, CGDO, CGBO, CGSL, CGDL, CKAPPAS, CKAPPAD
and CF. If possible, it is recommended that CGSO, CGDO, CGBO and CF
are extracted from CGD vs. VG at low VB (when S and D terminals are connected
together and B terminal is grounded), while CGSL, CGDL, CKAPPAS and CK-
APPAD are extracted from CGD vs. VG at high VB (when S, D and B terminals
are connected together).
• DLC, which is the channel-length offset parameter for the CV model, is extracted
in the strong-inversion region of CGG .
• VFBCVL and VFBCVLEXP, which express the length dependence of flat-band
voltage at CV, are extracted from depletion region till the onset of strong-inversion.
In order to be able to use VFBCVL and VFBCVLEXP parameters, VFBCV
must be 6= 00.

10.2.2 Drain Current ID vs. VG Analysis @ VD = [VD,lin , VD,sat ], VS = 0 V &

VB = 0 V

In this step, parameters related to short channel effects or to length dependencies

of ID vs. VG , are extracted. Similar to the procedure described in Section 10.1.2, the
parameters are divided in two groups, those which are extracted in linear mode (i.e.
VD  VG − VT H ) and those which are extracted in saturation (i.e. VD  VG − VT H ).
It is very important that during the extraction both ID and gm of all the devices are
studied at once.

87
Linear Mode

• Focusing in weak-inversion region (ID vs. VG characteristic when y-axis is in log-

arithmic scale), NFACTORL and NFACTORLEXP, which are related to the
length dependence of the sub-threshold slope of ID vs. VG , can be extracted. Fur-
thermore, LINT, which is the channel length offset parameter, is used to fit both
the sub-threshold slope and the VT H . For fitting the VT H of the devices also DVTP0
and UD can prove to be useful. UD should be used only for fine tuning because
it mainly affects the region above threshold. It is recommended that the param-
eters NDEPL1, NDEPLEXP1, NDEPL1 and NDEPLEXP1 keep the values
extracted from the CGG vs. VG analysis (Section 10.2.1). But, if the fitting of the
VT H across the entire length range cannot be achieved without changing the values
of NDEPL1, NDEPLEXP1, NDEPL1 and NDEPLEXP1, then these param-
eters are used for static operation (IV) and NDEPCVL1, NDEPCVLEXP1,
NDEPCVL1 and NDEPCVLEXP1 parameters are used for dynamic operation
(CV).

• In strong-inversion region, the parameters related to the length dependence of:

i) the mobility; U0L and U0LEXP, ii) the effect of mobility reduction due to
vertical field; UAL, UALEXP, EUL and EULEXP and iii) the coulomb scat-
tering effect; UDL and UDLEXP, are extracted. Furthermore, parameters for
the length dependence of S/D series resistances, namely RDSWL and RDSWL-
EXP (when RDSMOD = 00) or RSWL, RSWLEXP, RDWL and RDWL-
EXP (when RDSMOD = 11), are also extracted under the same bias conditions.

Saturation

• In weak-inversion region (ID vs. VG characteristic when y-axis is in logarithmic

scale), CDSCDL and CDSCDLEXP paramerers, which are linked to the length
dependence of the sub-threshold slope dependence on drain bias, are extracted.
Moreover, parameters for DIBL effect, which control VT H when VDS 6= 0, namely
ETA0 and DSUB, are also extracted in the same region.

• Focusing in strong-inversion region, the length scaling parameters linked to the ve-
locity saturation effect, i.e VSATL, VSATLEXP, PSATL, PSATLEXP, PTWGL
and PTWGLEXP, can be extracted.

88
Finally, from accumulation to depletion region, in both linear mode and saturation,
the parameters AGIDLL/AGISLL, which are related the length dependence of GIDL
effect (GIDL/GISL currents), are extracted.

10.2.3 IG vs. VG Analysis @ various VD , VS = 0 V & VB = 0 V

From IG vs. VG analysis, parameters related to the length dependence of gate current
are extracted. These parameters are: AIGCL, AIGSL, AIGDL and PIGCDL.

10.2.4 ID vs. VD Analysis @ various VG , VS = 0 V & VB = 0 V

In this step, both ID vs. VD and gds vs. VD characteristics should be studied at once.
Similar to the procedure described in Section 10.2.4 the parameters that are extracted
are:

• DELTAL and DELTALEXP, which are related to the length dependence of the
smoothing factor for the transition between VDS and VDS,sat .

• PDITSL, linked to the length dependence of DITS effect.

• PCLML, PCLMLEXP, FPROUTL and FPROUTLEXP linked to the length

dependence of CLM effect.

• PDIBLCL and PDIBLCLEXP, linked to the length dependence of the impact

of DIBL effect on Rout .

It is very important to be mentioned here, that if the slope of gds vs. VD characteristic at
low levels of inversion is steeper than the measurements, then ETA0 should be decreased
and DVTP1 can be used to achieve an accurate fit for the VT H in saturation.

10.2.5 CGG vs. VG Analysis @ VDS 6= 0 V & VB = 0 V

The extraction of the length scaling parameters of VSAT and PCLM from ID vs. VG
and ID vs. VD characteristics (Steps 10.2.2 and 10.2.4) should be sufficient in order to
capture VS and CLM effects for CV operation. To verify that, CGG vs. VG characteristic
of all devices, for different VDS 6= 0 V , from linear mode to saturation, must be studied. If
different values for VSATL, VSATLEXP, PCLML and PCLMLEXP are necessary

89
for accurate fitting of the CV behavior across L, then VSATCVL, VSATCVLEXP,
PCLMCVL and PCLMCVLEXP can be used.

10.2.6 ID vs. VG Analysis @ VD = [VD,lin , VD,sat ] & various VB (or various VS )

In this step almost the same procedure as in Section 10.1.6 will be repeated in order
to extract the length scaling parameters that are linked to the body effect. Similar to
Section 10.1.6, it is also very important that during the extraction in this step both ID
and gm of all devices are studied at once.

Linear Mode

• Focusing in weak-inversion region, K2L and K2LEXP, which are linked to the
length dependence VT H shift due to vertical non-uniform doping, are extracted.

• In strong-inversion region, UCL and UCLEXP, which are linked to the length de-
pendence of mobility reduction with VB (or VS ) bias, are extracted. The parameters
for the length dependence of S/D series resistances with VB (or VS ) bias, namely
PRWBL and PRWBLEXP, are also extracted under the same bias conditions.

Saturation

• In weak-inversion region (ID vs. VG characteristic when y-axis is in logarithmic

scale), the parameters related to length dependence of DIBL effect dependence on
VB (or VS ) bias, namely ETAB and ETABEXP, are extracted.

In order to validate that the values of the length scaling parameters, which are linked
to VB (or VS ) dependencies, are correctly extracted, it is useful to check ID vs. VD and
gds vs. VD characteristics @ various VG & VB 6= 0 V (or VS 6= 0 V ) and, if needed, to
fine tune the values of the parameters.

10.2.7 Fitting Verification

When all the steps for the extraction of short channel effects and length scaling
parameters have been performed, the fitting of the model should be checked for all the
analyses carried out in Section 10.2 and parameters can be fine tuned for better fitting.

90
10.3 Extraction of Narrow Channel Effects & Width Scaling
Parameters
The next step in the parameter extraction procedure is the extraction of the pa-
rameters that are either related to narrow channel effects or express the different width
dependencies. So at this part, devices across the entire width range of the technology,
from the narrowest to the widest one, are studied simultaneously. In order to avoid the
impact of short channel effects or of the length dependencies these devices should have
the same long channel. The extraction that is carried out follows the same flow as in
Section 10.2, but now a set of devices with constant long channel but different channel
widths is used.

10.3.1 Gate Capacitance CGG vs. VG Analysis @ VS = 0 V , VD = 0 V &

VB = 0 V

In this step, parameters related to the width dependencies of the CV behavior of the
device, e.g. width dependence of the doping concentration and flat-band voltage, are
extracted. More specifically:

• NDEPW and NDEPWEXP, which are the width scaling parameters for the
doping concentration, are extracted from CGG in the depletion region. If possible,
it is recommended that those parameters are extracted from CGB vs. VG analysis (S
and D terminals are grounded).
• DWC, which is the channel-width offset parameter for the CV model, is extracted
in the strong-inversion region of CGG .
• VFBCVW and VFBCVWEXP, which express the width dependence of flat-band
voltage at CV, are extracted along the entire VG bias range of CGG characteristic.
In order to be able to use VFBCVW and VFBCVWEXP parameters, VFBCV
must be 6= 00.

10.3.2 Drain Current ID vs. VG Analysis @ VD = [VD,lin , VD,sat ], VS = 0 V &

VB = 0 V

In this step, parameters related to width dependencies of ID vs. VG , are extracted.

Similar to the procedure described in Section 10.1.2, the parameters are divided in two

91
groups, those which are extracted in linear mode (i.e. VD  VG − VT H ) and those which
are extracted in saturation (i.e. VD  VG − VT H ). It is very important that during the
extraction both ID and gm of all the devices are studied at once.

Linear Mode

• Focusing in weak-inversion region (ID vs. VG characteristic when y-axis is in loga-

rithmic scale), NFACTORW and NFACTORWEXP, which are related to the
width dependence of the sub-threshold slope of ID vs. VG , can be extracted. Fur-
thermore, WINT, which is the channel width offset parameter, is used to fit both
the sub-threshold slope and the VT H across W. It is recommended that the parame-
ters NDEPW and NDEPWEXP keep the values extracted from the CGG vs. VG
analysis (Section 10.3.1). But, if the fitting of the VT H across the entire width range
cannot be achieved without changing the values of NDEPW and NDEPWEXP,
then these parameters are used for static operation (IV) and NDEPCVW and
NDEPCVWEXP parameters are used for dynamic operation (CV).
• In strong-inversion region, the parameters related to the width dependence of mo-
bility reduction due to vertical field effect, namely UAW, UAWEXP, EUW and
EUWEXP, are extracted.

Saturation

• Focusing in strong-inversion region, the width scaling parameters linked to the ve-
locity saturation effect, i.e. VSATW and VSATWEXP, can be extracted.

Finally, from accumulation to depletion region, in both linear mode and saturation, the
parameters AGIDLW/AGISLW, which are related the width dependence of GIDL
effect (GIDL/GISL currents), are extracted.
In order to validate that the values of the width scaling parameters are correctly
extracted, it is useful to check ID vs. VD and gds vs. VD characteristics @ various VG ,
VS = 0 V & VB = 0 V (or VS 6= 0 V ) and, if needed, to fine tune the values of the
parameters.

10.3.3 Gate Current IG vs. VG Analysis @ various VD , VS = 0 V & VB = 0 V

From IG vs. VG analysis, parameters related to the width dependence of gate current
are extracted. These parameters are: AIGCW, AIGSW and AIGDW.

92
10.3.4 Gate Capacitance CGG vs. VG Analysis @ VDS 6= 0 V & VB = 0 V

The extraction of the width scaling parameters of VSATW and VSATWEXP

from ID vs. VG and ID vs. VD characteristics (Step 10.3.2) should be sufficient in order
to capture VS for CV operation. To verify that, CGG vs. VG characteristic of all devices,
for different VDS 6= 0 V , from linear mode to saturation, must be studied. If different
values for VSATW and VSATWEXP are necessary for accurate fitting of the CV
behavior across W, then VSATCVW and VSATCVWEXP can be used.

10.3.5 Drain Current ID vs. VG Analysis @ VD = [VD,lin , VD,sat ] & various VB

(or various VS )

In this step, from weak-inversion region of linear mode, K2W and K2WEXP, which
are linked to the width dependence VT H shift due to vertical non-uniform doping, can
be extracted. For validation purposes, it is useful to check: i) ID vs. VG and gm vs. VG
characteristics in weak and strong-inversion and for both linear mode and saturation,
and ii) ID vs. VD and gds vs. VD characteristics @ various VG & VB 6= 0 V (or VS 6= 0 V )
and, if needed, extract K2W and K2WEXP to fit both (i) and (ii).

10.3.6 Fitting Verification

When all the extraction steps for the width scaling have been performed, the fitting
of the model should be checked for all the analyses carried out in Section 10.3and
parameters can be further tuned for better fitting.

10.4 Extraction of Parameters for Narrow/Short Channel De-

vices
The final part in the parameter extraction procedure from a geometrical point of
view, is the extraction of the parameters for narrow/short channel devices. These devices
have the minimum dimensions so it is more difficult to capture their behavior. Since
the narrow/short channel device parameters can affect the already performed fitting
across length and width, it is recommended that two different sets of devices are studied
simultaneously, i.e. one set with a constant short channel but different channel widths

93
(from narrowest to widest) and one set with a constant narrow channel but different
channel lengths (from the shortest to the longest one).

10.4.1 Gate Capacitance CGG vs. VG Analysis @ VS = 0 V , VD = 0 V &

VB = 0 V

In this step, geometry dependent parameters for modeling the CV behavior of the
narrow/short channel devices, are extracted. More specifically:

• NDEPWL and NDEPWLEXP, which are used to fit the doping concentration
of small channel devices, are extracted from CGG in the depletion region. If possible,
it is recommended that those parameters are extracted from CGB vs. VG analysis (S
and D terminals are grounded).

• LWLC and WWLC, which are coefficients of length/width dependencies for CV

model, are extracted in the strong-inversion region of CGG .

• VFBCVWL and VFBCVWLEXP, which are used to fit the flat-band voltage
at CV, are extracted from depletion till the onset of strong-inversion region of CGG
characteristic. In order to be able to use VFBCVWL and VFBCVWLEXP
parameters, VFBCV must be 6= 00.

10.4.2 Drain Current ID vs. VG Analysis @ VD = [VD,lin , VD,sat ], VS = 0 V &

VB = 0 V

In this step, geometry dependent parameters for modeling ID of the narrow/short

channel devices, are extracted. Similar to the procedure described in Section 10.1.2, the
parameters are divided in two groups, those which are extracted in linear mode (i.e.
VD  VG − VT H ) and those which are extracted in saturation (i.e. VD  VG − VT H ).
It is very important that during the extraction both ID and gm of all the devices are
studied at once.

Linear Mode

• Focusing in weak-inversion region (ID vs. VG characteristic when y-axis is in loga-

rithmic scale), NFACTORWL and NFACTORWLEXP, which are used to fit

94
 the sub-threshold slope of ID vs. VG for small channel devices, can be extracted.
It is recommended that the parameters NDEPWL and NDEPWLEXP keep the
values extracted from the CGG vs. VG analysis (Section 10.4.1). But, if the fitting
of the VT H for both sets of devices cannot be achieved without changing the values
of NDEPWL and NDEPWLEXP, then these parameters are used for static op-
eration (IV) and NDEPCVWL and NDEPCVWLEXP parameters are used for
dynamic operation (CV).
• In strong-inversion region, the parameters which are used to model the effect of
mobility reduction due to vertical field in small channel devices, namely UAWL,
UAWLEXP, EUWL and EUWLEXP, are extracted.

Saturation

• Focusing in strong-inversion region, the parameters which are used to model to the
velocity saturation effect in small channel devices, i.e. VSATWL and VSATWL-
EXP, can be extracted.

In order to validate that the values of the parameters, modeling the behavior of nar-
row/short channel devices, are correctly extracted, it is useful to check ID vs. VD and
gds vs. VD characteristics @ various VG , VS = 0 V & VB = 0 V and, if needed, to fine
tune the values of the parameters.

10.4.3 CGG vs. VG Analysis @ VDS 6= 0 V & VB = 0 V

The extraction of the parameters, which are used to model to the velocity saturation
effect in small channel devices, VSATWL and VSATWEXP, from ID vs. VG and
ID vs. VD characteristics (Step 10.4.2) should be sufficient in order to capture VS for
CV operation. To verify that, CGG vs. VG characteristic of all devices, for different
VDS 6= 0 V , from linear mode to saturation, must be studied. If different values for
VSATWL and VSATWLEXP are necessary for accurate fitting of the CV behavior
for both sets of devices, then VSATCVWL and VSATCVWLEXP can be used.

10.4.4 Drain Current ID vs. VG Analysis @ VD = [VD,lin , VD,sat ] & various VB

(or various VS )

In this step, from weak-inversion region of linear mode, K2WL and K2WLEXP,
which are linked to the VT H shift due to vertical non-uniform doping in small channel

95
devices, can be extracted. For validation purposes, it is useful to check: i) ID vs. VG and
gm vs. VG characteristics in weak and strong-inversion and for both linear mode and
saturation, and ii) ID vs. VD and gds vs. VD characteristics @ various VG & VB 6= 0 V
(or VS 6= 0 V ) and, if needed, extract K2WL and K2WLEXP to fit both (i) and (ii).

10.4.5 Fitting Verification

When all the steps for narrow/short channel devices have been performed, the fitting
of the model should be checked for all the analyses carried out in Section 10.4and
parameters can be fine tuned for better fitting.

10.5 Extraction of Temperature Dependence Parameters

Up to this point of the parameter extraction procedure, the temperature dependence
of the parameters has been ignored since all the parameters were extracted at TNOM. In
this part, the parameters that are related to the impact of temperature on the behavior of
devices are extracted, and for that, data across the temperature range of the technology
are necessary. The behavior of devices is studied with the same geometrical sequence as
the previous steps, while the temperature dependence parameters are extracted in the
same regions of operation as the parameters of the corresponding physical effects.

10.5.1 Wide & Long Channel Devices

The first step, in the extraction of temperature dependence parameters, is to extract

the behavior of a long and wide channel device @ different T and for different analy-
ses. It is recommended that the same device as the one in Section 10.1 is used. In detail:

ID vs. VG analysis @ VD = VD,lin , VS = 0 V & VB = 0 V

• From weak-inversion region (ID vs. VG characteristic when y-axis is in logarithmic

scale), the parameters TBGASUB and TBGBSUB, which control the temper-
ature dependence of Eg , are extracted. Also, TNFACTOR is extracted in order
to fit the sub-threshold slope of ID in different T, while KT1 and KT1EXP are
extracted for fitting the VT H across T.

96
 • From strong-inversion region, the mobility temperature exponent, UTE and the
temperature coefficients: i) for mobility reduction due to vertical field effect,
namely UA1 and UD1, ii) for coulomb scattering effect, UCSTE and iii) for
S/D series resitances, PRT, are extracted.

ID vs. VG analysis @ VD = VD,sat , VS = 0 V & VB = 0 V

• From strong-inversion region, the parameters that are used to model to the tem-
perature dependence of velocity saturation effect, i.e. AT and PTWGT, are
extracted.

It is very important that in the above analyses both ID and gm of all the devices are
studied at once. Furthermore, from accumulation to depletion region, in both linear
mode and saturation of ID vs. VG analysis, the parameter TGIDL, which controls the
temperature dependence of GIDL effect, is extracted.

ID vs. VD Analysis @ various VG , VS = 0 V & VB = 0 V

From ID vs. VD analysis in different temperatures, TDELTA, which is related to the

temperature dependence of the smoothing factor for the transition between VDS and
VDS,sat , is extracted.

ID vs. VG Analysis @ VD = VD,lin & various VB (or various VS )

• From weak-inversion region (ID vs. VG characteristic when y-axis is in logarithmic

scale) KT2, which is linked to the temperature dependence of VT H shift due to
vertical non-uniform doping with VB (orVS ) bias, is extracted.

• From strong-inversion region, the temperature coefficient for mobility reduction

with VB (orVS ) bias, namely UC1, is extracted.

For validation purposes, it is useful to check: i) ID vs. VG and gm vs. VG characteristics

in weak and strong-inversion and for both linear mode and saturation, and ii) ID vs. VD
and gds vs. VD characteristics @ various VG & VB 6= 0 V (or VS 6= 0 V ) and, if needed,
extract KT2 and UC1 to fit both (i) and (ii).

97
10.5.2 Length Scaling of Wide Channel Devices

The following step in the extraction of temperature dependence parameters, is to

study the temperatures dependences across L. For this, data @ different T of a set of
devices with constant wide channel but different channel lengths are used.

ID vs. VG analysis @ VD = VD,lin , VS = 0 V & VB = 0 V

• From weak-inversion region (ID vs. VG characteristic when y-axis is in logarithmic

scale), the parameter KT1L is extracted for fitting the VT H across L, at different
T.

• From strong-inversion region, the length scaling parameters for: i) mobility tem-
perature exponent, UTEL and for the temperature coefficients or mobility reduc-
tion due to vertical field effect, namely UA1L and UD1L, are extracted.

ID vs. VG analysis @ VD = VD,sat , VS = 0 V & VB = 0 V

• From weak-inversion region (ID vs. VG characteristic when y-axis is in logarithmic

scale), the parameter TETA0, which is related to the temperature dependence of
DIBL effect and thus is controlling the VT H in saturation, is extracted.

• From strong-inversion region, the parameters that are used to model the temper-
ature dependence of velocity saturation effect across L, i.e. ATL and PTWGTL,
are extracted.

It is very important that in the above analyses both ID and gm of all the devices
are studied at once. For validating that the values of length scaling parameters for
temperature dependence parameters are extracted correctly, it is useful to check also
ID vs. VD and gds vs. VD characteristics and, if needed, to fine tune their value by
repeating Step 10.5.2.

98
Figure 11: Parameters Extraction Procedure.

99
11 Instance Parameters

Name Unit Default Min Max Description

L m 10u - - Designed Gate Length
W m 10u - - Designed Gate Width (per finger)
NF - 1 1 - Number of fingers
NRS - 1 - - Number of source diffusion squares
NRD - 1 - - Number of drain diffusion squares
VFBSDOFFV - 0 - - Source-Drain flat band offset
MINZ - 0 0 1 Minimize either no. of drain or source ends
XGW m 0 0 - Distance from gate contact center to dev edge
NGCON - 1 1 2 Number of gate contacts
RGATEMOD - 0 0 2 Gate resistance model selector
RBODYMOD - 0 0 2 Substrate resistance network model selector
GEOMOD - 0 0 10 Geometry-dependent parasitic model selector-
specifying how the end S/D diffusion are con-
nected
RGEOMOD - 0 0 8 Bias independent parasitic resistance model
selector
RBPB Ohm 50 1mV - Resistance between bNodePrime and bNode
RBPD Ohm 50 1mV - Resistance between bNodePrime and dbNode
RBPS Ohm 50 1mV - Resistance between bNodePrime and sbNode
RBDB Ohm 50 1mV - Resistance between dbNode and bNode
RBSB Ohm 50 1mV - Resistance between sbNode and bNode
SA - 0 0 - Distance between OD edge from Poly from one
side
SB - 0 0 - Distance between OD edge from Poly from
other side
SD - 0 0 - Distance between neighboring fingers
SCA - 0 0 - Integral of the first distribution function for
scatted well dopant
SCB - 0 0 - Integral of second distribution function for
scattered well dopant

100
SCC - 0 0 - Integral of third distribution function for scat-
tered well dopant
SC - 0 0 - Distance to a single well edge
2
AS m 0 0 - Source to Substrate Junction Area
AD m2 0 0 - Drain to Substrate Junction Area
PS m 0 0 - Source to Substrate Junction Perimeter
PD m 0 0 - Drain to Substrate Junction Perimeter

12 Model Controllers and Process Parameters

(b)
Note: binnable parameters are marked as:

Name Unit Default Min Max Description and Scaling Parameters

TYPE - 1 -1 1 NMOS=1, PMOS=-1
CVMOD - 0 0 1 IV-CV: Consistent:0, Different:1
GEOMOD - 0 0 10 For description, please refer Table 1
RGEOMOD - 0 0 8 Bias independent parasitic resistance model
selector, refer Table 2
RGATEMOD - 0 0 2 Gate resistance Model selector
ASYMMOD - 0 0 1 Asymmetry model will be ON or OFF
MOBSCALE - 0 0 1 Two different models for mobility.
RBODYMOD - 0 0 2 Substrate resistance network model selector
RDSMOD - 0 0 2 0:Bias dependent internal, independent exter-
nal,
1:External RDS, 2:Internal RDS
COVMOD - 0 0 1 Bias-independent overlap capacitance:0, Bias-
dependent overlap capacitance:1
GIDLMOD - 0 0 1 Turn off GIDL model:0, Turn-on GIDL
model:1
SHMOD - 0 0 1 Turn off Self Heating model:0, Turn-on :1
PERMOD - 1 0 1 Whether PS/PD (when given) includes the
gate-edge perimeter
1: (including the gate-edge perimeter)

101
 0: (not including the gate-edge perimeter)
BINUNIT - 1 0 1 Binning unit selector
XL m 0 - - L offset for channel length due to mask/etch
effect
XW m 0 - - W offset for channel length due to mask/etch
effect
(b)
LINT m 0 - - Length reduction parameter (dopant diffusion
effect)
(b)
WINT m 0 - - Width reduction parameter (dopant diffusion
effect)
(b)
DLC m 0 - - Length reduction parameter for CV (dopant
diffusion effect)
(b)
DWC m 0 - - Width reduction parameter for CV (dopant
diffusion effect)
TOXE m 3.0n - - SiO2 equivalent gate dielectric thickness
TOXP m =TOXE - - Physical dielectric thickness
DTOX m 0.0 - - Difference between effective dielectric thick-
ness and physical thickness
(b) −3
NDEP m 1e24 - - channel (body) doping concentration. Global
Scaling Parameters - NDEPL1, NDE-
PLEXP1, NDEPL2, NDEPLEXP2, NDEPW,
NDEPWEXP, NDEPWL, NDEPWLEXP
(b) −3
NSD m 1e26 2e25 1e27 S/D doping concentration
EASUB eV 4.05 - - Electron affinity of substrate
(b) −3
NGATE m 5e25 - - parameter for Poly Gate doping. Set
N GAT E = 0 for metal gates
VFB(b) V -0.5 - - Flat band Voltage
EPSROX - 3.9 1 - relative dielectric constant of the gate insula-
tor
EPSRSUB - 11.9 1 - relative dielectric constant of the channel ma-
terial
−3
NI0SUB m 1.1e16 - - intrinsic carrier concentration of channel at
300.15K
(b)
XJ m 1.5e-7 - - S/D junction depth

102
DMCG 0 0 - Distance of Mid-Contact to Gate edge
DMCI DMCG 0 - Distance of Mid-Contact to Isolation
DMDG 0 0 - Distance of Mid-Diffusion to Gate edge
DMCGT 0 0 - Distance of Mid-Contact to Gate edge in Test

103
13 Basic Model Parameters
(b)
Note: binnable parameters are marked as:

Name Unit Default Min Max Description

LLONG m 10µm - - Length of extracted long channel device
WWIDE m 10µm - - Width of extracted long channel device
(b) 2
CIT F/m 0 - - Interface trap capacitance
(b)
NFACTOR 0 - - Subthreshold Swing factor. Global
Scaling Parameters - NFACTORL,
NFACTORLEXP, NFACTORW,
NFACTORWEXP, NFACTORWL
(b) 2
CDSCD F/m 1e-9 - - Drain-bias sensitivity of Subthreshold
Swing. Global Scaling Parameters -
CDSCDL, CDSCDLEXP
(b) 2
CDSCD F/m 1e-9 - - Drain-bias sensitivity of Subthreshold
Swing. Global Scaling Parameters -
CDSCDL, CDSCDLEXP
(b) 2
CDSCBR F/m CDSCD 0.0 - Reverse-mode drain-bias sensitivity.
Global Scaling Parameter - CDSCDLR
(b) 2
CDSCDR F/m 1e-9 - - Drain-bias sensitivity of Subthreshold
Swing. Global Scaling Parameters -
CDSCDR, LCDSCDR
(b)
DVTP0 - 1e-10 - - Coefficient of drain-inducred Vth shift
for long channel devices with pocket im-
plant
DVTP0 - 1e-10 - - Process related threshold shift
(b)
DVTP1 - 0 - - Coefficient of drain-inducred Vth shift
for long channel devices with pocket im-
plant
(b)
DVTP2 - 0 - - Coefficient of drain-inducred Vth shift
for long channel devices with pocket im-
plant

104
DVTP3(b) - 0 - - Coefficient of drain-inducred Vth shift
for long channel devices with pocket im-
plant
DVTP4(b) - 0 - - Coefficient of drain-inducred Vth shift
for long channel devices with pocket im-
plant
(b)
DVTP5 - 0 - - Coefficient of drain-inducred Vth shift
for long channel devices with pocket im-
plant
(b)
PHIN V 0.045 - - Vertical nonuniform doping effect on
surface potential
(b)
K2 V 0 - - Vth shift due to nonuniform vertical
doping. Global Scaling Parameters -
K2L, K2LEXP, K2W, K2WEXP
(b)
K1 V 0 - - Vth shift due to nonuniform verti-
cal doping. Global Scaling Parame-
ters - K1L, K1LEXP, K1W, K1WL,
K1WEXP, K1WLEXP
(b)
ETA0 - 0.08 - - DIBL coefficient
(b)
ETA0R - 0.08 - - DIBL coefficient
(b)
DSUB - 0.375 >0 - DIBL exponent coefficient
(b)
ETAB - -0.07 - - Body bias sensitivity to DIBL effect.
Global Scaling Parameters - ETABEXP
(b) 2
U0 m /V − s 67e-3 - - Low field mobility. Global Scaling Pa-
rameters - U0L, U0LEXP
ETAMOB - 1.0 - - effective field parameter
(b) EU
UA (cm/M V ) 0.001 > 0.0 - Phonon / surface roughness scattering
parameter. Global Scaling Parameters
- UAL, UALEXP, UAW, UAWEXP,
UAWL
(b)
EU cm/M V 1.5 > 0.0 - Phonon / surface roughness scattering
parameter. Global Scaling Parameters
- EUL, EULEXP, EUW, EUWEXP,
EUWL

105
UD(b) cm/M V 0.001 > 0.0 - Columbic scattering parameter. Global
Scaling Parameters - UDL, UDLEXP
(b)
UCS - 2.0 1 2 Columbic scattering parameter.
(b)
UC - 0.0 - - Body-bias sensitivity on mobility.
Global Scaling Parameters - UCL,
UCLEXP
(b)
VSAT m/s 1e6 - - Saturation velocity. Global Scal-
ing Parameters - VSATL, VSALEXP,
VSATW, VSATWEXP
(b)
VSATR m/s 1e6 - - Saturation velocity. Global Scal-
ing Parameters - VSATR, LVSATR,
WVSATR, PVSATR
(b)
DELTA - 0.125 >0 0.5 Smoothing factor for Vds to Vdsat.
Global Scaling Parameters - DELTAL,
DELTALEXP
(b)
PSAT - 1.0 0.25 1.0 Velocity saturation exponent. Global
Scaling Parameters - PSATL, PSATL-
EXP
(b) −2
PTWG V 0 - - Correction factor for velocity saturation
in forward mode. Global Scaling Pa-
rameters - PTWGL, PTWGLEXP
(b) −2
PTWGR V PTWG - - Correction factor for velocity saturation
in reverse mode. Global Scaling Param-
eters - PTWGLR, PTWGLEXPR
(b) −2
A1 V 0.0 - - Non-saturation effect parameter in
strong inversion region.
(b) −1
A2 V 0.0 - - Non-saturation effect parameter in
moderate inversion region.
PSATX - 1 0.25 4 Fine tuning of PTWG effect
(b)
PSATB - 0 - - Velocity saturation exponent for non-
zero Vbs
(b)
PCLM - 0.00 - - Channel Length Modulation (CLM) pa-
rameter. Global Scaling Parameters -
PCLML, PCLMLEXP

106
PCLMG - 0 - - Gate bias dependent parameter for
channel Length Modulation (CLM)
(b)
PSCBE1 - 4.24e8 − - Substrate current body-effect coeffi-
cient
(b)
PSCBE2 - 1.0e-8 − - Substrate current body-effect coeffi-
cient
(b)
PDITS - 0 − - Drain-induced Vth shift
PDITSL - 0 − - L dependence of Drain-induced Vth
shift
(b)
PDITSD - 0 − - VDS dependence of Drain-induced Vth
shift
(b)
RSWMIN Ω− µW
m
R
0.0 0.0 - source extension resistance per unit
width at high Vgs
(b)
RSW Ω− µW
m
R
10 0.0 - Zero bias source extension resistance
per unit width. Global Scaling Param-
eters - RSWL, RSWLEXP
(b)
RDWMIN Ω− µW
m
R
0.0 0.0 - Drain extension resistance per unit
width at high Vgs
RDW(b) Ω − µW
m
R
10 0.0 - Zero bias drain extension resistance per
unit width. Global Scaling Parameters
- RDWL, RDWLEXP
(b)
RDSWMIN Ω− µW
m
R
0.0 0.0 - LDD resistance per unit width at high
Vgs f orRDSM OD = 0
(b)
RDSW Ω− µW
m
R
10 0.0 - Zero bias LDD resistance per unit
width for RDSMOD=0. Global Scaling
Parameters - RDSWL, RDSWLEXP
(b) −1
PRWG V 1 0 - gate bias dependence of S/D extension
resistance
(b) −1
PRWB V 0 0 - body bias dependence of S/D extension
resistance. Global Scaling Parameters -
PRWBL, PRWBLEXP
(b)
WR - 1.0 - - W dependence parameter of S/D exten-
sion resistance

107
RSH Ω 0 0 - Sheet resistance
(b)
PDIBLC - 2e-4 0 - DIBL effect on Rout. Global Scal-
ing Parameters - PDIBLCL, PDI-
BLCLEXP
(b)
PDIBLCB - 0 0 - Body-bias sensitivity on DIBL
(b)
PVAG - 1 - - Vgs dependence on early voltage
(b)
FPROUT - 0 0 - gds degradation factor due to pocket
implant. Global Scaling Parameters -
FPROUTL, FPROUTLEXP
(b)
AGIDL - 0 - - Pre-exponential coefficient for GIDL.
Global Scaling Parameters - AGIDLL,
AGIDLW
(b)
BGIDL - 2.3e-9 - - exponential coefficient for GIDL
(b)
CGIDL - 0.5 - - exponential coefficient for GIDL
(b)
EGIDL - 0.8 - - band bending parameter for GIDL
(b)
AGISL - 0 - - Pre-exponential coefficient for GISL
(AGISL< 0 means GISL parameters
will same as GIDL parameters). Global
Scaling Parameters - AGISLL, AG-
ISLW
(b)
BGISL - 2.3e-9 - - exponential coefficient for GISL
(b)
CGISL - 0.5 - - exponential coefficient for GISL
(b)
EGISL - 0.8 - - band bending parameter for GISL
(b)
ALPHA0 - 0.0 - - First parameter of impact ionization
current. Global Scaling Parameters -
ALPHA0L, ALPHA0LEXP
(b)
BETA0 - 0.0 - - First Vds dependent parameter of im-
pact ionization current
(b) 2 0.5
AIGC (F s /g) 1.36e-2 - - Parameter for Igcs and Igcd . Global
(NMOS) Scaling Parameters - AIGCL, AIGCW
and
9.8e-3
(PMOS)

108
BIGC(b) (F s2 /g)0.5 1.71e-3 - - Parameter for Igcs and Igcd
(NMOS)
and
7.59e-4
(PMOS)
(b) 2 0.5
CIGC (F s /g) 0.075 - - Parameter for Igcs and Igcd
(NMOS)
and 0.03
(PMOS)
(b) 2 0.5
AIGS (F s /g) 1.36e-2 - - Parameter for Igs . Global Scaling Pa-
(NMOS) rameters - AIGSL, AIGSW
and
9.8e-3
(PMOS)
(b) 2 0.5
BIGS (F s /g) 1.71e-3 - - Parameter for Igs
(NMOS)
and
7.59e-4
(PMOS)
(b) 2 0.5
CIGS (F s /g) 0.075 - - Parameter for Igs
(NMOS)
and 0.03
(PMOS)
(b)
DLCIG m LINT - - Source/Drain overlap length for Igs
(b) 2 0.5
AIGD (F s /g) 1.36e-2 - - Parameter for Igd . Global Scaling Pa-
(NMOS) rameters - AIGDL, AIGDW
and
9.8e-3
(PMOS)
(b) 2 0.5
BIGD (F s /g) 1.71e-3 - - Parameter for Igd
(NMOS)
and
7.59e-4
(PMOS)

109
CIGD(b) (F s2 /g)0.5 0.075 - - Parameter for Igd
(NMOS)
and 0.03
(PMOS)
(b)
DLCIGD m DLCIG - - Source/Drain overlap length for Igd
(b)
POXEDGE - 1.0 - - Factor for the gate oxide thickness in
source/drain overlap regions
(b)
PIGCD - 1.0 - - Vds dependence of Igcs and Igcd .
Global Scaling Parameters - PIGCDL,
PIGCDLEXP
(b)
NTOX - 1.0 - - Exponent for the gate oxide ratio
TOXREF m 3.0e-9 - - Nominal gate oxide thickness for gate
dielectric tunneling current model only
(b)
VFBSDOFF V 0.0 - - Flatband Voltage Offset Parameter
(b) −3
NDEPCV m NDEP - - channel (body) doping concentration
for CV. Global Scaling Parameters
- NDEPCVL1, NDEPCVLEXP1,
NDEPCVL2, NDEPCVLEXP2,
NDEPCVW, NDEPCVWEXP, NDE-
PCVWL, NDEPCVWLEXP
(b) −3
VFBCV m VFB - - channel (body) doping concentration
for CV. Global Scaling Parameters
- VFBCVL, VFBCVLEXP, VF-
BCVW, VFBCVWEXP, VFBCVWL,
VFBCVWLEXP
(b)
VSATCV m/s VSAT - - Saturation velocity for CV. Global Scal-
ing Parameters - VSATCVL, VSACVL-
EXP, VSATCVW, VSATCVWEXP
PCLMCV(b) - PCLM - - Channel Length Modulation (CLM) pa-
rameter for CV. Global Scaling Param-
eters - PCLMCVL, PCLMCVLEXP
(b)
CF F/m 0 0.0 - Outer fringe cap
(b)
CFRCOEFF F/m 1 1 - Outer fringe cap coefficient

110
CGSO F/m calculated 0.0 - Non LDD region source-gate overlap ca-
pacitance per unit channel width
CGDO F/m calculated 0.0 - Non LDD region drain-gate overlap ca-
pacitance per unit channel width
(b)
CGSL F/m 0 0.0 - Overlap capacitance between gate and
lightly-doped source region
(b)
CGDL F/m 0 0.0 - Overlap capacitance between gate and
lightly-doped drain region
(b)
CKAPPAS V 0.6 0.02 - Coefficient of bias-dependent overlap
capacitance for the source side
(b)
CKAPPAD V 0.6 0.02 - Coefficient of bias-dependent overlap
capacitance for the drain side
CGBO F/m 0 0.0 - Gate-substrate overlap capacitance per
unit channel length
ADOS - 0 0 - Quantum mechanical effect prefactor
cum switch in inversion
BDOS - 1.0 0 - Charge centroid parameter - slope of
CV curve under QME in inversion
QM0 - 1e-3 > 0.0 - Charge centroid parameter - starting
point for QME in inversion
ETAQM - 0.0 0 - Bulk charge coefficient for charge cen-
troid in inversion
DLBIN 0.0 - - Length reduction parameter for binning
DWBIN 0.0 - - Width reduction parameter for binning
LMLT 1.0 > 0.0 - Length shrinking factor
WMLT 1.0 > 0.0 - Width shrinking factor

14 High-Speed/RF Model Parameters

Name Description Default

111
XRCRG1 (b) Parameter for distributed channel-resistance effect for both 12.0
intrinsic-input resistance and charge-deficit NQS mod-
els(Warning message issued if binned XRCRG1 ≤ 0.0 ) dis-
tributed channel-resistance effect for both intrinsic-input re-
sistance and charge-deficit NQS models(Warning message is-
sued if binned XRCRG1 ≤ 0.0 )
XRCRG2 (b) Parameter to account for the excess channel diffusion resis- 1.0
tance for both intrinsic input resistance and charge-deficit
NQS models
RBPB (Also Resistance connected between bNodePrime and bNode 50.0ohm
an instance
parameter)
RBPD (Also Resistance connected between bNodePrime and dbNode (If 50.0ohm
an instance less than 1.0e-3ohm, reset to 1.0e-3ohm )
parameter)
RBPS (Also Resistance connected between bNodePrime and sbNode (If 50.0ohm
an instance less than 1.0e-3ohm, reset to 1.0e-3ohm)
parameter)
RBDB (Also Resistance connected between dbNode and bNode 50.0ohm
an instance
parameter)
RBSB (Also Resistance connected between sbNode and bNode 50.0ohm
an instance
parameter)
GBMIN Conductance in parallel with each of the five substrate re- 1.0e-
sistances to avoid potential numerical instability due to un- 12mho
reasonably too large a substrate resistance (Warning message
issued if less than 1.0e-20 mho )
RBPS0 Scaling prefactor for RBPS 50
Ohms
RBPSL Length Scaling parameter for RBPS 0.0
RBPSW Width Scaling parameter for RBPS 0.0
RBPSNF Number of fingers Scaling parameter for RBPS 0.0
RBPD0 Scaling prefactor for RBPD 50
Ohms
RBPDL Length Scaling parameter for RBPD 0.0

112
RBPDW Width Scaling parameter for RBPD 0.0
RBPDNF Number of fingers Scaling parameter for RBPD 0.0
RBPBX0 Scaling prefactor for RBPBX 100
Ohms
RBPBXL Length Scaling parameter forRBPBX 0.0
RBPBXW Width Scaling parameter for RBPBX 0.0
RBPBXNF Number of fingers Scaling parameter for RBPBX 0.0
RBPBY0 Scaling prefactor for RBPBY 100
Ohms
RBPBYL Length Scaling parameter forRBPBY 0.0
RBPBYW Width Scaling parameter for RBPBY 0.0
RBPBYNF Number of fingers Scaling parameter for RBPBY 0.0
RBSBX0 Scaling prefactor for RBSBX 100
Ohms
RBSBY0 Scaling prefactor for RBSBY 100
Ohms
RBDBX0 Scaling prefactor for RBDBX 100
Ohms
RBDBY0 Scaling prefactor for RBDBY 100
Ohms
RBSDBXL Length Scaling parameter for RBSBX and RBDBX 0.0
RBSDBXW Width Scaling parameter for RBSBX and RBDBX 0.0
RBSDBXNF Number of fingers Scaling parameter for RBSBX and RBDBX 0.0
RBSDBYL Length Scaling parameter for RBSBY and RBDBY 0.0
RBSDBYW Width Scaling parameter for RBSBY and RBDBY 0.0
RBSDBYNF Number of fingers Scaling parameter for RBSBY and RBDBY 0.0

113
15 Flicker and Thermal Noise Model Parameters
Parameter Description Default Value
Name
NOIA Flicker noise parameter A 6.25e41(eV )−1 s1−EF m−3
for NMOS;
−1 1−EF −3
6.188e40(eV ) s m
for PMOS
NOIB Flicker noise parameter B 3.125e26(eV )−1 s1−EF m−1
for NMOS;
−1 1−EF −1
1.5e25(eV ) s m
for PMOS
NOIC Flicker noise parameter C 8.75(eV )−1 s1−EF m
EM Saturation field 4.1e7V/m
AF Flicker noise exponent 1.0
EF Flicker noise frequency exponent 1.0
KF Flicker noise coefficient 0.0A2−EF s1−EF
LINTNOI Length Reduction Parameter Offset 0.0 m
NTNOI Noise factor for short-channel devices for 1.0
TNOIMOD=0 only
TNOIA Coefficient of channel-length dependence of 1.5
total channel thermal noise
TNOIB Channel-length dependence parameter for 3.5
channel thermal noise partitioning
TNOIC Length dependent parameter for Correlation 0
Coefficient
RNOIA Thermal Noise Coefficient 0.577
RNOIB Thermal Noise Coefficient 0.5164
RNOIC Correlation Coefficient parameter 0.395

114
16 Layout-Dependent Parasitic Model Parameters

Parameter Description Default Value

Name
DMCG Distance from S/D contact center to the gate 0.0m
edge
DMCI Distance from S/D contact center to the iso- DMCG
lation edge in the channel-length direction
DMDG Same as DMCG but for merged device only 0.0m
DMCGT DMCG of test structures 0.0m
NF (instance Number of device fingers (Fatal error if less 1
parameter than one )
only)
DWJ Offset of the S/D junction width DWC (in CVmodel)
MIN (in- Whether to minimize the number of drain 0 (minimize the drain dif-
stance pa- or source diffusions for even-number fingered fusion number)
rameter only) device
XGW(Also Distance from the gate contact to the channel 0.0m
an instance edge
parameter)
XGL Offset of the gate length due to variations in 0.0m
patterning
XL Channel length offset due to mask/ etch ef- 0.0m
fect
XW Channel width offset due to mask/etch effect 0.0m
NGCON(Also Number of gate contacts (Fatal error if less 1
an instance than one; if not equal to 1 or 2, warning mes-
parameter) sage issued and reset to 1 )

115
17 Asymmetric Source/Drain Junction Diode Model
Parameters
Parameter Description Default Value
Name (sepa-
rate for source
and drain side
as indicated in
the names)
IJTHSREV Limiting current in reverse bias region IJTHSREV = 0.1A,
IJTHDREV IJTHDREV = IJTH-
SREV
IJTHSFWD Limiting current in forward bias region IJTHSFWD = 0.1A,
IJTHDFWD IJTHDFWD = IJTHS-
FWD
XJBVS XJBVD Fitting parameter for diode breakdown XJBVS = 1.0, XJBVD =
XJBVS
BVS BVD Breakdown voltage (If not positive, reset BVS = 10.0V, BVD =
to 10.0V ) BVS
JSS JSD Bottom junction reverse saturation cur- JSS= 1.0e-4A/m2, JSD
rent density = JSS
JSWS JSWD Isolation-edge sidewall reverse saturation JSWS = 0.0A/m, JSWD
current density = JSWS
JSWGS JSWGD Gate-edge sidewall reverse saturation cur- JSWGS =0.0A/m,
rent density JSWGD = JSWGS
JTSS JTSD Bottom trap-assisted saturation current JTSS = 0.0A/m JTSD =
density JTSS
JTSSWS STI sidewall trap-assisted saturation cur- JTSSWS = 0.0A/m2
JTSSWD rent density JTSSWD = JTSSWS
JTSSWGS Gate-edge sidewall trap-assisted satura- JTSSWGS = 0.0A/m
JTSSWGD tion current density JTSSWGD = JTSSWGS
JTWEFF Trap-assistant tunneling current density 0.0
width dependence
NJTS NJTSD Non-ideality factor for JTSS and JTSD NJTS = 20.0 NJTSD =
NJTS

116
NJTSSW Non-ideality factor for JTSSWS and NJTSSW = 20.0
NJTSSWD JTSSWD NJTSSWD = NJTSSW
NJTSSWG Non-ideality factor forJTSSWGS and NJTSSWG = 20.0
NJTSSWGD JTSSWGD NJTSSWGD =
NJTSSWG
XTSS, XTSD Power dependence of JTSS, JTSD on tem- XTSS = 0.02 XTSD =
perature 0.02
XTSSWS, Power dependence of JTSSWS, JTSSWD XTSSWS =0.02
XTSSWD on temperature XTSSWD = 0.02
XTSSWGS, Power dependence of JTSSWGS, JTSS- XTSSWGS = 0.02
XTSSWGD WGD on temperature XTSSWGD = 0.02
VTSS VTSD Bottom trap-assisted voltage dependent VTSS = 10V VTSD =
parameter VTSS
VTSSWS STI sidewall trap-assisted voltage depen- VTSSWS =10V
VTSSWD dent parameter VTSSWD =VTSSWS
VTSSWGS Gate-edge sidewall trap-assisted voltage VTSSWGS = 10V
VTSSWGD dependent parameter VTSSWGD =VTSS-
WGS
TNJTS Temperature coefficient for NJTS and TNJTS=0.0 TNJTSD
TNJTSD NJTSD =TNJTS
TNJTSSW Temperature coefficient for NJTSSW and TNJTSSW=
TNJTSSWD NJTSSWD 0.0 TNJTSSWD
=TNJTSSW
TNJTSSWG Temperature coefficient for NJTSSWG TNJTSSWG =0.0
TNJTSSWGD and NJTSSWG TNJTSSWGD =
TNJTSSWG
CJS CJD Bottom junction capacitance per unit area CJS=5.0e-4 F/m2
at zero bias CJD=CJS
MJS MJD Bottom junction capacitance grating coef- MJS=0.5 MJD=MJS
ficient
MJSWS Isolation-edge sidewall junction capaci- MJSWS =0.33 MJSWD
MJSWD tance grading coefficient =MJSWS
CJSWS CJSWD Isolation-edge sidewall junction capaci- CJSWS= 5.0e-10 F/m
tance per unit area CJSWD =CJSWS
CJSWGS Gate-edge sidewall junction capacitance CJSWGS =CJSWS
CJSWGD per unit length CJSWGD =CJSWS

117
MJSWGS Gate-edge sidewall junction capacitance MJSWGS =MJSWS
MJSWGD grading coefficient MJSWGD =MJSWS
PBS Source-side bulk junction built-in poten- 1.0V
tial
PBD Drain-side bulk junction built-in potential PBD=PBS
PBSWS PB- Isolation-edge sidewall junction built-in PBSWS =1.0V PBSWD
SWD potential =PBSWS
PBSWGS PB- Gate-edge sidewall junction built-in po- PBSWGS =PBSWS PB-
SWGD tential SWGD =PBSWS

118
18 Temperature Dependence and Self Heating Pa-
rameters
Parameter Description Default Value
Name
TNOM Temperature at which parameters are ex- 270 C
tracted
DTEMP Variability handle for temperature 0
UTE (b) Mobility temperature exponent -1.5
UCSTE(b) Temperature coefficient of coulombic mobil- -4.775e-3
ity
TDELTA Temperature coefficient for DELTA 0.0
TGIDL (b) Temperature coefficient for GIDL/GISL 0.0
IIT (b) Temperature coefficient for BETA0 0.0
KT1 (b) Temperature coefficient for threshold voltage -0.11V
KT1EXP Temperature exponent for threshold voltage 1.0
KT1L (b) Channel length dependence of the tempera- 0.0Vm
ture coefficient for threshold voltage
KT2(b) Body-bias coefficient of Vth temperature ef- 0.022
fect
UA1 (b) Temperature coefficient for UA 1.0e-9m/V
UC1 (b) Temperature coefficient for UC 0.056V-1 for MOB-
MOD=1; 0.056e-9m/V 2
for MOBMOD=0 and 2
UD1 (b) Temperature coefficient for UD 0.0(1/m)2
AT (b) Temperature coefficient for saturation veloc- 3.3e4m/s
ity
PTWGT Temperature coefficient for PTWG 0.0

PRT (b) Temperature coefficient for Rdsw 0.0ohm-m

NJS, NJD Emission coefficients of junction for source NJS=1.0; NJD=NJS
and drain junctions, respectively
XTIS, XTID Junction current temperature exponents for XTIS=3.0; XTID=XTIS
source and drain junctions, respectively
TPB Temperature coefficient of PB 0.0V/K
TPBSW Temperature coefficient of PBSW 0.0V/K

119
TPBSWG Temperature coefficient of PBSWG 0.0V/K
TCJ Temperature coefficient of CJ 0.0K-1
TCJSW Temperature coefficient of CJSW 0.0K-1
TCJSWG Temperature coefficient of CJSWG 0.0K-1
TVFBSDOFF Temperature coefficient of VFBSDOFF 0.0K-1
TNFACTOR(b)Temperature coefficient of NFACTOR 0.0
TETA0 Temperature coefficient of ETA0 0.0
RTH0 Thermal resistance for self-heating calcula- 0.0
tion
CTH0 Thermal capacitance for self-heating calcula- 1.0E-5
tion
WTH0 Width-dependence coefficient for self heating 0.0
calculation

120
19 Stress Effect Model Parameters
Parameter Description Default Value
Name
SA (Instance Distance between OD edge to Poly from one 0.0
Parameter) side (If not given or(≤ 0), stress effect will
be turned off)
SB (Instance Distance between OD edge to Poly from 0.0
Parameter) other side (If not given or(≤ 0), stress effect
will be turned off)
SD (Instance Distance between neighbouring fingers (For 0.0
Parameter) NF>1 :If not given or(≤ 0), stress effect will
be turned off)
SAref Reference distance between OD and edge to 1E-06[m]
poly of one side (>0.0)
SBref Reference distance between OD and edge to 1E-06[m]
poly of the other side (>0.0)
WLOD Width parameter for stress effect 0.0[m]
KU0 Mobility degradation/enhancement coeffi- 0.0[m]
cient for stress effect
KVSAT Saturation velocity degradation/ enhance- 0.0[m]
ment parameter for stress effect (1 ≤
kvsat ≤ 1)
TKU0 Temperature coefficient of KU0 0.0
LKU0 Length dependence of ku0 0.0
WKU0 Width dependence of ku0 0.0
PKU0 Cross-term dependence of ku0 0.0
LLODKU0 Length parameter for u0 stress effect (>0) 0.0
WLODKU0 Width parameter for u0 stress effect (>0) 0.0
KVTH0 Threshold shift parameter for stress effect 0.0[Vm]
LKVTH0 Length dependence of kvth0 0.0
WKVTH0 Width dependence of kvth0 0.0
PKVTH0 Cross-term dependence of kvth0 0.0
LLODVTH Length parameter for Vth stress effect (>0) 0.0
WLODVTH Width parameter for Vth stress effect (>0) 0.0
STK2 K2 shift factor related to Vth0 change 0.0[m]

121
LODK2 K2 shift modification factor for stress effect 0.0
(>0)
STETA0 eta0 shift factor related to Vth0 change 0.0[m]
LODETA0 eta0 shift modification factor for stress effect 1.0
(>0)

122
20 Well-Proximity Effect Parameters

Parameter Name Description Default Value

SCA (Instance Pa- Integral of the first distribution func- 0.0
rameter) tion for scattered well dopant (If not
given , calculated)
SCB (Instance Pa- Integral of the second distribution func- 0.0
rameter) tion for scattered well dopant (If not
given , calculated)
SCC (Instance Pa- Integral of the third distribution func- 0.0
rameter) tion for scattered well dopant (If not
given , calculated)
SC (Instance Pa- Distance to a single well edge (If not 0.0[m]
rameter) given or ≤ 0.0, turn off WPE)
WEB Coefficient for SCB (>0.0) 0.0
WEC Coefficient for SCC (>0.0) 0.0
KVTH0WE(b) Threshold shift factor for well proxim- 0.0
ity effect
K2WE (b) K2 shift factor for well proximity effect 0.0
KU0WE (b) Mobility degradation factor for well 0.0
proximity effect
SCREF Reference distance to calculate SCA, 1e-6[m]
SCB and SCC (<0)

123
21 Edge FET Device Parameters
(b)
Note: binnable parameters are marked as:

Name Unit Default Min Max Description

− −
WEDGE m 10e 9 1e 9 - Edge FET Width
DGAMMA 0 - - Different in body-bias coefficient be-
tween Edge-FET and Main-FET
DGAMMAL 0 - - L dependence parameter for DGAMMA
DGAMMALEXP 1.0 - - Exponent of L dependence parameter
for DGAMMA
DVTEDGE 0.0 - - Vth shift for Edge FET
(b)
NFACTOREDGE NFACTOR - - NFACTOR for Edge FET
(b) 2
CITEDGE F/m CIT - - CIT for Edge FET
(b) 2
CDSCDEDGE F/m CDSCD - - CDSCD for edge FET
(b) 2
CDSCBEDGE F/m CDSCB - - CDSCB for edge FET
(b) 2
ETA0EDGE F/m ETA0 - - DIBL parameter for edge FET
(b) 2
ETABEDGE F/m ETAB - - ETAB for edge FET
(b)
KT1EDGE V KT1 - - Temperature dependence parameter of
threshold voltage for edge FET
(b) 2
KT1LEDGE F/m KT1L - - Temperature dependence parameter of
threshold voltage for edge FET
(b)
KT2EDGE V KT2 - - Temperature dependence parameter of
threshold voltage for edge FET
KT1EXPEDGE KT1EXP - - Temperature dependence parameter of
threshold voltage for edge device
(b)
TNFACTOREDGE TNFACTOR- - Temperature dependence parameter of
sub-threshold slope factor for edge
TETA0EDGE TETA0 - - Temperature dependence parameter of
DIBL parameter for edge FET
DVT0EDGE 2.2 - - First coefficient of SCE effect on Vth
for Edge FET
DVT1EDGE 0.53 - - Second coefficient of SCE effect on Vth
for Edge FET

124
DVT2EDGE 0.0 - - Body-bias coefficient for SCE effect for
Edge FET

125
22 Parameter equivalence between BSIM6 & BSIM4
The equivalent parameters are the closest match between two models. There values
may be different in two models.

Region BSIM6 Parameter BSIM4 Parameter Comment

Name Name
Core Parameters GEOMOD GEOMOD
RGEOMOD RGEOMOD
RDSMOD RDSMOD
COVMOD COVMOD
L L
W W
XL XL
XW XW
LINT LINT
WINT WINT
DLC DLC
DWC DWC
TOXE TOXE
TOXP TOXP
NF NF
NDEP NDEP or
VTH0/VTHO
NGATE NGATE
VFB, VFBCV VFB, VFBCV
Material proper- EASUB - Corresponds
ties
NI0SUB - to BSIM4
EPSRSUB - mtrlmod=1
EPSROX -
Threshold Volt- NDEPL1, NDE- DVT0, DVT1, Length scaling
age PLEXP1, NDEPL2, DVT2, LPE0
NDEPLEXP2
NDEPW, NDEP- DVT0W, DVT1W, Width and
WEXP, NDEPWL, DVT2W, K3, W0 Narrow-short
NDEPWLEXP Scaling
K2W K3B

126
 DVTP0, DVTP1, same as BSIM4
DVTP2, DVTP3,
DVTP4, DVTP5
PHIN PHIN
ETA0 ETA0
ETAB ETAB
DSUB DSUB
K2 K2
K2L, L2LEXP K1, LPEB
Subthreshold CIT CIT
Swing
NFACTOR CDSC
CDSCD CDSCD
CDSCB CDSCB
NFACTOR NFACTOR
Drain Satura- VSAT, DELTA VSAT, DELTA
tion Voltage
Mobility Model U0 U0 BSIM6 uses
MOBMOD=3
from BSIM4
ETAMOB - default value of
1 corresponds to
BSIM4
U0L UP
U0LEXP LPA
UA UA
EU EU
UD UD
UCS UCS
UC UC
Channel Length PCLM PCLM
Modulation and
DITS
PCLMG PCLMG
PSCBE1 PSCBE1
PSCBE2 PSCBE2
PDITS PDITS

127
 PDITSL PDITSL
PDITSD PDITSD
Velocity Satura- VSAT VSAT
tion
PTWG -
PSAT -
PSATX -
PSATB -
Rs, Rd parame- XJ XJ BSIM6 uses
ter RDSMOD=1
from BSIM4
VFBSDOFF VFBSDOFF
NRS/NRD NRS/NRD
MINZ MINZ
NSD NSD
RSH RSH
PRWG PRWG
PRWB PRWB
WR WR
RDSWMIN RDSWMIN
RSWMIN RSWMIN
RDWMIN RDWMIN
RDSW RDSW
RSW RSW
RDW RDW
DMCG DMCG
DMCI DMCI
DMDG DMDG
DMCGT DMCGT
Impact Ioniza- ALPHA0, AL- ALPHA0, ALPHA1
tion PHA0L, AL-
PHA0LEXP
BETA0 BETA0
GIDL/GISL AGIDL AGIDL
BGIDL BGIDL
CGIDL CGIDL
EGIDL EGIDL

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 AGISL AGISL
BGISL BGISL
CGISL CGISL
EGISL EGISL
C-V Model CF CF
CFRCOEFF - Taken from
BSIMSOI
CFI -
CGSO CGSO
CGDO CGDO
CGBO CGBO
CGSL CGSL
CGDL CGDL
CKAPPAS CKAPPAS
CKAPPAD CKAPPAD
ADOS, BDOS, QM0, ADOS, BDOS
ETAQM

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23 Appendix A : Smoothing Function

23.1 Polynomial Smoothing

The polynomial smoothing is used for a smooth transition between boundaries, maintaining
exact values at all the corner points. Consider the function
∆x
f (x) = x if x > (23.1)
2
−∆x
= k if x < (23.2)
2
−∆x ∆x
where k is some constant. The function is undefined for the region 2 <x< 2 . If this
region is approximated by a polynomial function, the complete function and even derivatives
can be made continuous. Now consider the more generalized case

f (x) = x if x > x1 (23.3)

= k if x < x2 (23.4)

To express (23.4) in the form of (23.2), x is linearly transformed into z. Defining

x1 + x2
x0 = (23.5)
2
∆x = x1 − x2 (23.6)

then the boundary points becomes

∆x
x1 = x0 + (23.7)
2
∆x
x2 = x0 − (23.8)
2
x−x0
Let z = ∆x . Thus the above boundary points in z domain becomes,

x1 − x0 1
z1 = = (23.9)
∆x 2
x2 − x0 1
z2 = =− (23.10)
∆x 2

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so that the function becomes
1
f (z) = z.∆x − x0 if z > (23.11)
2
1
= k if z < − (23.12)
2
the region − 21 ≤ z ≤ 1
2 is modeled by the polynomial function whose order depends on the
number of boundary conditions. For example, to have continuous derivatives upto third order,
we need seventh order polynomial as there are 8 boundary conditions.

f (z) = a.z 7 + b.z 6 + c.z 5 + d.z 4 + e.z 3 + f.z 2 + g.z + 1 (23.13)

Then boundary conditions can be applied to derivatives to determine the polynomial coeffi-
cients. For the case of continuous third order derivatives, we found that
" " !##
5 z 15 5
f (x) = x0 + ∆x. + + z2. − z2. − z2 (23.14)
64 2 16 4

while for continuous second order derivative

" " !##
3 z 3 3 z 2
f (x) = x0 + ∆x. + + z2. − z2. − (23.15)
32 2 4 4 2
x−x0
with z = ∆x . Figure 12 illustrate the concept of polynomial smoothing.
An Example : Let the function be given as

f (x) = x if x > −90 (23.16)

= −100 if x < −110 (23.17)

with the condition that third derivative to exist. From (23.6)

x0 = −100 (23.18)
∆x = 20 (23.19)
x + 100
z= (23.20)
20
and function becomes,
1
f (z) = 20.z + 100 if z > (23.21)
2
1
= − 100 if z < − (23.22)
2

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 Figure 12: Illustration of Polynomial Smoothing

Boundary Conditions
1 1
f ( ) = −90, f (− ) = −100 (23.23)
2 2
0 1 0 1
f ( ) = 20, f (− ) = 0 (23.24)
2 2
00 1 00 1
f ( ) = 0, f (− ) = 0 (23.25)
2 2
000 1 000 1
f ( ) = 0, f (− ) = 0 (23.26)
2 2
We have 8 boundary conditions. So let

f (z) = a.z 7 + b.z 6 + c.z 5 + d.z 4 + e.z 3 + f.z 2 + g.z + 1 (23.27)

Now we have 8 equations and 8 unknowns and hence all the coefficients can be derived. By
substituting (23.23-23.26) in (23.27) we get

a = 0, b = 20, c = 0
75
d = −25, e = 0, f = (23.28)
4
6300
g = 10, h = − (23.29)
64

132
Thus
75 2 6300
f (z) = 20.z 6 − 25.z 4 + .z + 10.z − (23.30)
4 64
Figure:13 shows the above function. As can be seen that due to polynomial nature, the

Figure 13: Polynomial Smoothing Function

approximated function undergoes smooth transitions around the boundary points.

133
References
[1] Y. Tsividis, Operation and Modeling of the MOS Transistor 2nd ed. Oxford, 1999.

[2] Y. S. Chauhan, M. A. Karim, S. Venugopalan, S. Khandelwal, P. Thakur, N. Pay-

davosi, A. Sachid, A. B.and Niknejad, and C. Hu, “Bsim6:symmetric bulk mosfet
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[3] J.-M. Sallese, M. Bucher, F. Krummenacher, and P. Fazan, “Inversion charge lin-
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[4] F. Pregaldiny, F. Krummenacher, B. Diagne, F. Pecheux, J.-M. Sallese, and

C. Lallement, “Explicit modeling of the double-gate mosfet with vhdl-ams,” Inter-
national Journal of Numerical Modelling: Electronic Networks, Devices and Fields,
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[5] BSIM4 user manual. [Online]. Available: http://www-device.eecs.berkeley.edu/

bsim/

[6] C. C. Hu, Modern Semiconductor Devices for Integrated Circuits. Pearson Edu-
cation, 2010.

[7] MOS Model 11 manual. [Online]. Available: http://www.nxp.com/models/simkit/

mos-models/model-11.html

[8] K. K. Hung, P. Ko, and Y. C. Cheng, “A physics-based mosfet noise model for
circuit simulator,” IEEE Transaction on Electron Devices, vol. 37, no. 5, pp. 1323–
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[9] A. J. Scholten, R. Langevelde, L. F. Tiemeijer, and D. B. M. Klaassen, “Compact

modeling of noise in cmos,” in CICC, 2006.

[10] R. A. Bianchi, G. Bouche, and O. Roux-ditBuisson, “Accurate modeling of trench

isolation induced mechanical stress effect on mosfet electrical performance,” in 2007
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[11] T. Hook, J. Brown, P. Cottrell, E. Adler, D. Hoyniak, J. Johnson, and R. Mann,

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[12] Compact Model Council. [Online]. Available: http://www.geia.org/index.asp?bid=
597

135
24 Ackowledgements
We deeply appreciate the feedback we received from (in alphabetical order):
Shantanu Agnihotri(IIT Kanpur)
Maria Anna Chalkiadaki(EPFL)
Kaiman Chan (TI)
Brian Chen (Accelicon)
Sergey Cherepko (ADI)
Geoffrey Coram (ADI)
Krishnanshu Dandu (TI)
Anupam Dutta (IBM)
Christian Enz (EPFL)
Keith Green (TI)
Andre Juge (ST)
Tracey Krakowski (TI)
Francois Krummenacher (EPFL)
Pragya Kushwaha (IIT Kanpur)
Waikit Lee (TSMC)
Samuel Mertens (Agilent)
Saurabh Sirohi (IBM)
Jing Wang (IBM)
Joddy Wang (Synopsys)
Wenli Wang (Cadence)
Josef Watts (IBM)
Richard Williams (IBM)
Weimin Wu (TI)
Jane Xi (Synopsys)
Jushan Xie (Cadence)
Chandan Yadav(IIT Kanpur)

136
Fang Yu (Synopsys)
Fulong Zaho (Cadence)

Manual created: July 20, 2015

137