A FEASIBILITY STUDY OF HIGH-VOLTAGE COMPARATORS USING

SILICON METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS

A Master’s Thesis
Presented to
The Academic Faculty

By

Blake Capella

In Partial Fulfillment
of the Requirements for the Degree
Master of Science in the
School of Electrical and Computer Engineering

Georgia Institute of Technology

August 2022

© Blake Capella 2022

 A FEASIBILITY STUDY OF HIGH-VOLTAGE COMPARATORS USING
SILICON METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS

Thesis committee:

Dr. Shyh-Chiang Shen Dr. Gabriel Alfonso Rincón-Mora

Electrical and Computer Engineering Electrical and Computer Engineering
Georgia Institute of Technology Georgia Institute of Technology

Dr. James Kenney

Electrical and Computer Engineering
Georgia Institute of Technology

Date approved: June 7, 2022

This achievement is dedicated to my parents, Debi and Craig. I am eternally grateful for
their presence in my life, and without their never-ending support, none of this would have
been possible.
 ACKNOWLEDGMENTS

To begin, I would like to express my gratitude to Cameron Pike and his colleagues at
GIRD for their continued feedback and support throughout the project. Additionally, the
expertise and equipment from James Steinberg and other employees at the ECE senior
design lab greatly expedited work on this research, and I am grateful for all of their
assistance. To my peers, Henri Bouchard and Helen Yoo, I am eternally grateful for the
support in handling the wide variety of challenges this project provided. I would also like
to thank my thesis comittee, Dr. Rincón-Mora and Dr. Kenney, for their feedback on
this report. Finally, I would like to acknowledge the support of my research advisor and
committee chair Dr. Shen, for without his guidance I would have been at a loss.
The project or effort depicted here has been supported by the U.S. Army Research
Office, and the content of the information does not necessarily reflect the position or the
policy of the Government, and no official endorsement should be inferred.

iv
 TABLE OF CONTENTS

Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x

List of Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv

Chapter 1: Introduction and Background . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Proposed Research . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Prior Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.1 Dynamic Comparators . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.2 GaN HEMT Comparators . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3.1 Differential Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3.2 Commercial Comparators . . . . . . . . . . . . . . . . . . . . . . . 12

1.3.3 Silicon MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.3.4 RF Matching Theory . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chapter 2: LDMOS-based Differential Amplifier Design and Implementation . 19

v
 2.1 Design and Simulation of Prototype Differential Amplifiers . . . . . . . . . 19

2.1.1 Transistor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.2 Model Verification . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.1.3 Preliminary Design Simulation . . . . . . . . . . . . . . . . . . . . 28

2.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.2.1 Lab Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.2.2 Test Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.2.3 Prototype 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.2.4 Prototype 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.3 LDMOS-Based Differential Amplifier Design and Implementation . . . . . 35

2.3.1 Impedance Matching Considerations . . . . . . . . . . . . . . . . . 35

2.3.2 Feedback Loop Design Considerations . . . . . . . . . . . . . . . . 35

2.3.3 Trade-off Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.3.4 Performance Optimization . . . . . . . . . . . . . . . . . . . . . . 37

2.3.5 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . 38

Chapter 3: Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.1 Prototype Differential Amplifiers . . . . . . . . . . . . . . . . . . . . . . . 40

3.1.1 Exploratory Simulations . . . . . . . . . . . . . . . . . . . . . . . 40

3.1.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2 LDMOS-Based Differential Amplifier . . . . . . . . . . . . . . . . . . . . 44

3.2.1 Negative Feedback Calculations . . . . . . . . . . . . . . . . . . . 44

3.2.2 Trade-off Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 45

vi
 3.2.3 Performance Optimization . . . . . . . . . . . . . . . . . . . . . . 46

3.2.4 Preliminary Measurements . . . . . . . . . . . . . . . . . . . . . . 47

Chapter 4: Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Appendix A: Prototype Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Appendix B: Reference Design [26] . . . . . . . . . . . . . . . . . . . . . . . . 55

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

vii
 LIST OF TABLES

1.1 COTS Silicon Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1 MRFE6VP5150N Electrical Characteristics . . . . . . . . . . . . . . . . . 20

2.2 BSS84AKS Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 21

2.3 DMN67D7L Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 22

2.4 Substrate Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.5 PA Simulation Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.6 Reported LDMOS Performance in a Broadband Amplifier . . . . . . . . . . 25

2.7 Simulated LDMOS Performance in a Broadband Amplifier . . . . . . . . . 26

2.8 NMOS Verification Parameters . . . . . . . . . . . . . . . . . . . . . . . . 27

2.9 PMOS Verification Parameters . . . . . . . . . . . . . . . . . . . . . . . . 27

2.10 Preliminary Design Trace Dimensions . . . . . . . . . . . . . . . . . . . . 29

2.11 Preliminary Design Simulation Configuration . . . . . . . . . . . . . . . . 30

2.12 Test and Measurement Equipment . . . . . . . . . . . . . . . . . . . . . . 30

2.13 Prototype 1 PCB Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.14 Prototype 2 PCB Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.15 Prototype 2 Design Configuration . . . . . . . . . . . . . . . . . . . . . . . 34

2.16 Trade-off Analysis Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36

viii
2.17 Final Design Simulation Configuration . . . . . . . . . . . . . . . . . . . . 38

2.18 Prototype 3 PCB Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.1 Feedback Resistance Trade-off Analysis . . . . . . . . . . . . . . . . . . . 45

3.2 Bias Current Trade-off Analysis . . . . . . . . . . . . . . . . . . . . . . . 45

3.3 Bias Voltage Trade-off Analysis . . . . . . . . . . . . . . . . . . . . . . . 46

B.1 PA Reference Trace Dimensions . . . . . . . . . . . . . . . . . . . . . . . 55

ix
 LIST OF FIGURES

1.1 Differential Amplifier Symbol . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 Differential Amplifier Topology . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4 Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.5 CMOS Device Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.6 LDMOS Device Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.7 Transmission Line Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1 PA Reference Design Schematic . . . . . . . . . . . . . . . . . . . . . . . 23

2.2 PA ADS Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.3 BSS84AKS Model Verification . . . . . . . . . . . . . . . . . . . . . . . . 27

2.4 DMN67D7L Model Verification . . . . . . . . . . . . . . . . . . . . . . . 28

2.5 Preliminary Design Simulation Schematic . . . . . . . . . . . . . . . . . . 29

2.6 Prototype 1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.7 KiCAD Schematic of Prototype 2 . . . . . . . . . . . . . . . . . . . . . . 33

2.8 ADS Schematic of Prototype 2 . . . . . . . . . . . . . . . . . . . . . . . . 34

2.9 ADS Schematic of the Final Design . . . . . . . . . . . . . . . . . . . . . 37

2.10 KiCAD Schematic of Prototype 3 . . . . . . . . . . . . . . . . . . . . . . 39

x
3.1 Prototype 1 Large-Signal Measurement . . . . . . . . . . . . . . . . . . . 42

3.2 Final Design Forward and Reverse Gain . . . . . . . . . . . . . . . . . . . 46

3.3 Final Design Input and Output Reflection Coefficients . . . . . . . . . . . . 47

3.4 Prototype 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.5 Prototype 3 Large-signal Measurement . . . . . . . . . . . . . . . . . . . . 48

A.1 Prototype 1 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

A.2 Prototype 1 Photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

A.3 Prototype 2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

A.4 Prototype 2 Photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

A.5 Prototype 3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

A.6 Prototype 3 Photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

B.1 Broadband Reference PA Schematic . . . . . . . . . . . . . . . . . . . . . 55

B.2 Reference Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . 56

xi
 LIST OF ACRONYMS

ADS Advanced Design System

CMOS complimentary metal-oxide-semiconductor field effect transistors

CMRR common-mode rejection ratio

COTS commercial-off-the-shelf

EDA electronic design automation

ESD electrostatic discharge

FM frequency modulation

GaN Gallium Nitride

HB harmonic balance

HF high frequency

IC integrated circuit

LDMOS laterally-diffused MOSFET

LVDS low voltage differential signalling

MIS-HEMT metal-insulator-semiconductor high electron mobility transistors

MOSFET metal-oxide-semiconductor field effect transistor

NMOS n-channel MOSFET

PA power amplifier

PCB printed circuit board

PECL positive emitter coupled logic

PMOS p-channel MOSFET

RF radio frequency

TTL transistor-transistor logic

xii
UHF ultra high frequency

VDMOS vertically diffused MOSFET

VHF very high frequency

xiii
 SUMMARY

The overall trend of transistor scaling has resulted in distinct, application specific
manufacturing processes. Two of these specialized devices, scaled complimentary
metal-oxide-semiconductor field effect transistors (CMOS) and power transistors, typically
have inversely related performance in speed, power handling, and size. This work develops
a novel comparator circuit to explore the potential benefits of integrating these two
technology schemes to achieve improved power handling capabilities for signal processing
and communication systems through the development of a Silicon-based high-voltage
comparator. The study produced a final circuit with a flat-band gain of 20dB across
the high frequency (HF) range with a projected input voltage tolerance above 10V. The
development process indicates that the physical characteristics of the power transistor,
a laterally-diffused MOSFET (LDMOS), constrains frequency response and therefore,
ultimately, comparator performance. Although the demonstrated device does not achieve
the target performance, the investigation suggests that integration of the power transistors
at the integrated circuit (IC) level is a promising approach to producing a competitive
high-voltage Silicon-based comparator.

xiv
 CHAPTER 1
INTRODUCTION AND BACKGROUND

As digital interfaces become more ubiquitous in everyday life, it becomes easy to remove
numeric data at the user’s end from the corresponding physical phenomena. One clear
example of this comes from the cellular communication network, where the transmission
of data between users is a direct result of electromagnetic wave modulation. Governed by
the Maxwell-Heaviside equations, the phenomena of electromagnetic wave propagation is
an inherently analog process. Communications systems enable the transmission of digital
data through an analog medium through the use of several stages of signal processing, with
the exact configuration determined by the application. This complex signal digitization
process is required at any technological interface with the natural world and relies heavily
on a single class of electronic circuit, the comparator. Comparators are electrical circuits
that compare two analog values (e.g., voltages or currents) and output a digital signal
indicating which of the two values is greater. When a comparator is used to compare
an input signal to a given threshold, it is performing a one-bit quantization. This function is
combined with additional circuit elements to build the complex analog-to-digital converters
that enable digital data processing. In addition, comparators can be used discretely to
perform a host of useful measurement functions. These include detecting the zero crossings
of AC signals, threshold or null detection, or in band-pass non-linearities. Comparators
also see widespread use in various other fields including within switching power supplies,
linear voltage regulators, feedback controllers, monitoring systems, and protection circuits
among other mixed-signal applications.
The simplest topology for a comparator is that of a single stage differential amplifier.
Most commercial products build more complex architectures from this foundation to
improve performance at an acceptable cost in cost and area. When designing a comparator,

1
the differential gain is maximized so that when receiving a relatively small difference
in input voltages, the amplifier rapidly reaches a saturated output voltage. For designs
at the IC level, a transistor’s critical dimensions can be controlled to further optimize
performance for high-speed or high-load applications. Although transistor scaling has
provided significant performance improvements and increases in chip densities, current
leading-edge process nodes introduce additional complexity and costs that make these
devices unsuited for application in most analog ICs. Instead, comparators are typically
constructed with either complimentary metal-oxide-semiconductor field effect transistor
(MOSFET) or bipolar junction transistors fabricated in legacy process nodes.
Although these process nodes are not at the forefront of device fabrication, comparators
still see significant benefits from a decreased scale, especially as comparator speeds rise.
As voltage levels and device dimensions (tox , L, W ) have been reduced, both latency
and energy dissipation are reduced [1]. However, these improvements come at a cost.
The reduction of device dimensions significantly decrease a scaled transistor’s power
handling ability. This resulting specialization has required a separate fabrication process
for switching transistors designed for high power applications such as in radio frequency
(RF) power amplifier (PA) or power converters. This alternate device is typically referred to
as a power transistor or power MOSFET. Although comparators designed with these scaled
or general purpose transistors satisfy a wide range of design needs, these devices have not
achieved high speed performance while maintaining high maximum input voltages.
A brief survey of products from two leading manufacturers, Texas Instruments (TI) and
Analog Devices Inc. (ADI), can be seen in Table 1.1. These devices were chosen to span
the application spaces currently occupied by commercial products.
Generally, both supply voltage range and voltage input range are monotonically
decreasing functions of propagation delay. This trend is not surprising, as the designed
reduction of supply voltage levels is a key design consideration for a smaller and faster
ICs. At the IC level, transistor scaling provides lower RC delay and improves frequency

2
Table 1.1: A representative collection of commercial comparators [2][3][4][5][6][7][8][9]
Part Number Single Supply Range Voltage Input Range Propagation Delay
LM397 25V 30V 440ns
LMV331 10V 11V 200ns
CMP401 3.3V 9V 33ns
TL3116 2V 7V 10ns
AD8561 7V 3V 7ns
ADCMP60X 3V 2.9V 3.5ns
ADCMP55X 2.1V 1.5V 0.5ns

response, yet decreases the allowable input voltage range.

1.1 Proposed Research

Increasingly, with the popularization of heterogeneous integration, circuits including both

scaled and power transistors have attracted attention for performance improvements that
result from each processes inherent advantages [10]. Although this integration has been
seen in power electronics, where its advantages are clear, the concept remains to be
investigated for many different applications, including comparators. The objective of the
proposed research is to study the feasibility of implementing a high-voltage comparator
for communication systems using Silicon power transistor technology. In this case,
LDMOS technology provides an appealing alternative for CMOS in producing high speed
comparators with improved voltage handling capabilities. This silicon-based technology
platform has been commercially developed for use as an RF power amplifier, yet the
platform’s high gain, gate-source input voltage range, and frequency response offer unique
design opportunities for silicon-based high-voltage comparator design. As RF power
amplifiers, LDMOS transistors are designed to operate well at high frequencies, yet their
laterally extended drain-source connection and improved gate-source isolation contribute
drain-source voltage handling capabilities above 50V and gate-source voltage handling
on the order of 10V respectively. LDMOS comparators are well positioned to create
a new class of comparator occupying an entirely undeveloped performance area with a
wide common-mode and differential input voltage range capable of retaining high-speed

3
(< 10nS) performance.
The produced circuit is intended to operate both in communication systems and general
purpose applications, therefore in this study the performance specifications will be targeted
to the HF frequency range (3-30MHz). At the upper limit of this band, the propagation
delay can be estimated to result in sufficiently fast performance (< 10nS) to enter the
target application space. A successful design is defined as a circuit that is unconditionally
stable up to 100MHz with input and output matching better than -10dB across the HF
range. Additionally, the circuit must achieve a minimum flat-band gain of 40dB. With
most commercially available products achieving gains between 60dB and 80dB in multiple
stages, the design goal for this single stage design leaves room for future gain improvements
through the additional stages.

1.2 Prior Work

Upon review of current literature, there were not found any explicit examples studying the
feasibility of applying of Silicon power transistors or LDMOS to design a more robust
comparator. This section will present a brief review of the state of the art in comparator
development.

1.2.1 Dynamic Comparators

As technology becomes more ubiquitous, the number of battery powered comparator

applications has increased significantly. This results in an increased focus on reduced
power consumption with minimal impact on performance. Active research over the past
decade has heavily focused on the development of dynamic comparators for low-power
high-speed applications including high performance (e.g. Flash) ADCs [11] [12]. The
dynamic, or clocked, comparator architecture uses a clocked signal input to improve the
power efficiency of the circuit by allowing the complete deactivation of the comparator
circuit with simple digital control signals. Additionally, the conventional dynamic

4
comparator architecture features zero static power consumption, further improving power
efficiency. A variation on this design, the double tail dynamic comparator, stacks less
transistors and therefore can operate at even lower supply voltages [13]. Many of these
designs include regenerative feedback mechanisms to further boost the comparator’s speed,
making the comparators useful for high-speed ADCs. Due to the intended low-power
applications, these architectures are implemented in scaled CMOS technology, supporting
the design trend towards decreased operating voltages in a small footprint. Although
these trends have resulted in significant performance improvements in mixed signal
conditioning and high-speed low-power ADCs, the gains from this research area are
inherently unsuitable for the development of a comparator with high maximum input
voltages.

1.2.2 GaN HEMT Comparators

Gallium Nitride (GaN) is receiving increasing attention in the power electronics field
for its high electron-mobility and inherently high voltage-handling abilities. This has
led to widespread adoption of GaN power transistors as the main switches in various
forms of power converters. One area of research focuses on creating complete power
converter systems in the GaN material system to avoid the heterogeneous integration
of GaN power switches and sub-circuits traditionally based in Silicon [14]. Many of
these Silicon mixed-signal functional units rely on comparator functionality, leading to
the development of integrated GaN metal-insulator-semiconductor high electron mobility
transistors (MIS-HEMT) comparators over the past few years. These devices have
demonstrated maximum input voltages on the order of 10V, similar to those targeted by our
study [15] [16]. The application of a specialized power transistor in a comparator circuit
serves a clear analogy towards the proposed research, however the system level application
in an all-GaN power platform significantly differs from application in communication
systems or signal processing. Due to the immaturity of the process technology, GaN’s

5
inherent advantages are limited to power electronics and incapable of achieving the suite
of performance requirements for the target applications.

1.3 Background

This section will discuss in more detail several of the key technologies underlying
the research into a high-speed, high-voltage silicon comparator, including: differential
amplifiers, commercial comparators, Silicon MOSFETs, and RF impedance matching
theory.

1.3.1 Differential Amplifiers

A differential amplifier is a circuit that takes two input signals and outputs an amplified
version of their difference. According to the topology of the amplifier circuit, one signal is
denoted as the positive input (vin+ ) while the second is denoted as the negative input (vin− ).
This relation is defined in the following equation, where A is defined as the voltage gain in
volts per volt.

vout = A(vin+ − vin− ) (1.1)

At the highest level, a differential amplifier can be drawn with the following symbol,
which generalizes Equation 1.1. Note that most differential amplifiers operate with two
power rails, V + and V −, which partially define the upper and lower bounds of the output
signal.
At the transistor level, a differential amplifier is typically composed of either CMOS
transistors or in high-speed applications, BJTs. Moving forward, we will consider the
CMOS differential amplifier for its high voltage handling potential. A schematic of the
foundational components of a CMOS differential amplifier can be seen in Figure 1.2.
This topology can be divided into three functional units: the differential or

6
Figure 1.1: Schematic symbol for a differential amplifier including split voltage supply
rails

Figure 1.2: The fundamental differential amplifier topology with biasing omitted for clarity.

source-connected pair (Q1 ,Q2 ), the current mirror (Q3 ,Q4 ), and finally the biasing current
source or tail transistor (Q5 ). The theory of operation behind a differential amplifier heavily
depends on the physical dimension matching of paired devices, in this case either those
composing the differential pair or current mirror. Any deviations in physical parameters
will result in performance degradation, and therefore our discussion will occur under the
assumption of identically matched transistors.
Analysis of this circuit will begin with the differential pair biased by an ideal current
source and loaded by two resistors (RD ), as seen in Figure 1.3. In the absence of inputs to
Q1 and Q2 , these perfectly matched transistors will evenly split the bias current I between
their two legs. This results in an identical voltage drop across the drain resistance on both

7
transistors, therefore producing a differential output of 0V. In small-signal analysis, in any
case where an identical stimulus is provided to vin+ and vin− , called a common-mode
input, the bias current will remain balanced between the two loads. In other words, an ideal
differential amplifier will ignore common mode inputs. This is one of the key features of
a differential amplifier, common-mode rejection, and makes it attractive in noise-sensitive
applications.

Figure 1.3: A differential pair biased by an ideal current source with biasing omitted for
clarity

If on the other hand, the input signal differs between the two inputs, such as the
following balanced differential input:

vid
vin+ = (1.2)
2
−vid
vin− =
2

the circuit will produce a non-zero output.

The small signal amplification, Ad , can be determined through classical small signal
analysis techniques. First, it should be noted that for a complimentary differential input,
the signal at the shared source will not change, acting as a virtual ground. After replacing

8
the MOSFETs with their equivalent T-models, it becomes clear that the output voltages,
vd1 and vd2 , will result from the currents id1 and id2 . These in turn, are determined by the
MOSFET’s transconductance, gm , which relates the small signal input gate-source voltage
to the corresponding increase in gate current. After accounting for sign conventions,

−gm1 vid
vd1 = (1.3)
2
gm2 vid
vd2 =
2

If this output is taken differentially as shown in Figure 1.3, the gain becomes

vd1 − vd2
Ad = = gm RD (1.4)
vid

Alternatively, if the output is taken in a single ended fashion, the gain reduces to

vd2
Ad = = (1/2)gm RD (1.5)
vid

The behavior of a differential amplifier can be visualized by considering the balance of

the bias current between the two legs of the amplifier. In the case where no input is applied
to either transistor, the bias current I is split evenly between the two transistors.
Consider the unbalanced application of a differential input on the circuit from
Figure 1.3.

vin+ = vid (1.6)

vin− = 0

It can be seen from inspection that the differential input voltage is the difference in
gate-source voltages. If the input is applied to Q1 , then

9
 vid = vGS1 − vGS2 (1.7)

If the differential input is positive, vGS1 will be greater than vGS2 , and therefore iD1 will
carry more than half of the bias current, I. As vid increases further, eventually a limit will
be reached once Q1 carries the entire bias current, iD1 = I. In this case, Q2 will be turned
off by a corresponding increase in source voltage, vS .
It follows that to use the differential pair as a linear amplifier, the input signal must
be kept small to avoid this saturation. In large-signal operation, this behavior is the
cornerstone of comparator action. The amplifier can be designed so that the two saturation
states produce outputs equivalent to a logical high or logical low signal for a given logic
scheme (e.g. CMOS, low voltage differential signalling (LVDS)). This design, when fed
an unbalanced differential input, will indicate the greater of the two signals with its output.
As comparators operate in the large-signal regime, their performance metrics differ
from the numerous small-signal measurements typically used to define differential
amplifiers. Some key metrics used to define the large-signal performance of a comparator
are slew rate, input offset voltage (VIO ), saturation voltage, output jitter and propagation
delay. The slew rate is defined as the maximum rate of change of the comparator’s output,
typically measured in volts per microsecond, and can be partially derived from the small
signal differential gain. The input offset voltage, on the other hand, measures the input
voltage differential required to trigger an output swing. The comparator’s saturation voltage
is the output voltage for either a high or low signal, and depending on the circuit its
magnitude can be as high as the supply voltages. Output jitter is defined as a timing error
at the output’s switching point, and can be caused by thermal noise. Finally propagation
delay is defined as the time between the reception a pulsed input and this signal’s output
from the comparator.
The critical difference between the circuit under analysis so far and the presented
differential amplifier topology in Figure 1.2 is the addition of a current mirror. A current

10
mirror is a set of matched transistors with a connected gate and source, which is additionally
connected to the drain of Q3, defined as the input to the current mirror. The schematic of a
current mirror is presented in Figure 1.4.

Figure 1.4: The current mirror formed by the matched devices Q2 and Q3

When applied to a differential pair, the produced circuit (Figure 1.2) behaves so that
when a current id3 is drawn from the supply, the established gate-source voltage vgs3,4 will
recreate this current in id4 . A common-mode input results in an equal and opposite current
being fed into Q2.

id4 = id2 (1.8)

io = id4 − id2

In other words, for a common mode input, the output of the current mirror cancels the
current contributed from the differential pair at vout . For differential inputs, the balanced
input and resulting virtual ground provides different results. In this case, the small signal
currents add together.

io = id4 + id2 = 2i (1.9)

11
 This factor of two allows a single ended output that avoids the gain penalty
demonstrated in Equation 1.5.
Comparators typically build on the core design illustrated in Figure 1.2 with additional
output stages, hysteresis circuitry (e.g. cross-coupled mirrors, mirror folding) or
regenerative feedback circuitry for high-speed applications.

1.3.2 Commercial Comparators

The diverse market of discrete silicon comparators can be roughly organized into three
categories based on the performance metric they have been designed to prioritize. First,
precision comparators are designed to minimize input voltage offset, achieving offsets
on the order of hundreds of micro-volts [17]. The next category is ”ultra-fast” or
high-speed comparators, which contains designs focused on minimizing propagation delay.
Many high-speed comparators achieve propagation delays on the order of a nanosecond,
although some devices have begun to achieve delays of hundreds of pico-seconds in
specific signalling schemes [7] [18]. The final category contains designs optimized for low
power applications. These devices can achieve power consumption levels on the order of
micro-watts [19]. Beyond these three core design specializations, circuits are designed with
a number of secondary features. These typically include hysteresis, internal references,
known power-up states, rail-to-rail inputs and outputs, small form factors, shutdown modes,
and strobe pins.
Among this wide market, designs vary by output logic interfaces. For general purpose
products, the circuits typically utilize open collector or push-pull output stages. For specific
digital applications, comparators can be designed for use with CMOS, transistor-transistor
logic (TTL) or the more specialized high-speed positive emitter coupled logic (PECL) and
low-power LVDS output logic interfaces.

12
1.3.3 Silicon MOSFETs

Generally speaking, two classes of MOSFET fabrication processes and devices exist.
The first are the transistors specialized for application in digital logic circuits, typically
fabricated in a CMOS process. The second class, power MOSFET transistors, apply low
carrier concentration drift regions, vertical orientations, specialized geometry, material
changes and other techniques to improve the power handling ability of a device. Although
vertical power transistors exist and are popular for many power electronics applications,
the planar LDMOS will be the focus here due to the improved small signal performance
of a planar device and the CMOS process compatibility required for application in
an effective, manufacturable high-voltage silicon comparator. These two variations in
MOSFET technologies will be further explored here.

CMOS

The label CMOS refers to a MOSFET fabrication process that produces complimentary
and symmetrical pairs of p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS)
transistors for digital logic circuits. Among many other applications, CMOS is the
semiconductor technology used to fabricate the transistors that constitute modern day
microprocessors, microcontrollers, and memory chips. The CMOS process has been
extensively developed, as described by Moore’s Law, to scale down transistors using the
framework established by Dennard’s 1974 paper [1]. This scaling allows engineers to
place more transistors into a fixed area, increasing functionality, further reduce costs, and
lower latency and energy dissipation. For thirty years, this resulted in a steady reduction in
device dimensions (tox , L, W , see Figure 1.5) and for a time, reduction in voltage levels in
exchange for performance benefits.
Although device scaling for digital logic has been a driver of of a mature MOSFET
fabrication process, many modern IC chips do not utilize transistors from cutting edge
nodes. This is, in part, due to the fact that as device dimensions (i.e. channel lengths)

13
 Figure 1.5: Sample device geometry for an CMOS transistor [20]

have approached the nanometer scale, manufacturing costs and complexity have increased
exponentially [21]. Instead, many analog IC chips are instead fabricated on trailing edge
or legacy CMOS fabrication plants.

LDMOS

LDMOS transistors are type of power MOSFET that evolved out of the vertically
diffused MOSFET (VDMOS) for use in RF power amplifiers. The LDMOS is a
planar device created using an augmented CMOS process. These augmentations include
double-diffusion, an extended gate-drain region and gate-drain field plate shielding.

Figure 1.6: Sample device geometry for an LDMOS transistor [22]

The double diffusion process, shared with VDMOS, results in a lightly doped n-type

14
drift region between the source and drain, reducing the avalanche breakdown onset voltage.
The gate-drain extension increases the device’s breakdown voltage (typ. 70V or 120V)
while field plate shielding significantly reduces the strength of generated fields, both
reducing the gate-drain feedback capacitance and improving device reliability by reducing
the acceleration of hot carriers [23]. Overall, LDMOS have seen widespread use in power
ICs due to the avoidance of short channel, hot carrier and snap-back breakdown issues
[24]. Since its introduction in 1977, the LDMOS has become a leading technology for
a wide variety of RF power applications due to its combination of high voltage handling
ability, high linearity, and low capacitance. The development of LDMOS technology has
been driven by its widespread adoption for base-station applications but its uses have
grown to include, broadcast, frequency modulation (FM), very high frequency (VHF),
ultra high frequency (UHF), industrial scientific, medical and radar applications [23].
This combination of voltage handling and linear performance make the LDMOS an ideal
component for the development of a high-voltage comparator.

1.3.4 RF Matching Theory

Although circuit theory is powerful, it is unable to model electrical behaviour when the
wavelength of an AC signal approaches the physical dimensions of the circuit. This requires
a distributed circuit model, which has lead to the expansion of transmission line theory. For
a unit distance (∆z) of transmission line, the electrical properties can be captured with four
parameters: series resistance (R), series inductance (L), shunt conductance (G), and shunt
capacitance (C) as depicted in Figure 1.7.
Applying Kirchoff’s voltage and current laws to this unit circuit produces a set of two
differential equations named the telegrapher equations. The simultaneous solution of these
two equations produces wave equations for both current and voltage. These in turn produce
traveling wave equations,

15
 Figure 1.7: Transmission Line Model [25]

V (z) = Vo+ e−γz − Vo− eγz (1.10)

I(z) = Io+ e−γz − Io− eγz

p
γ = α + jβ = (R + jωL)(G + jωC)

which when applied to Ohm’s Law,

Zo = V+ /I+ (1.11)

produce an expression for a transmission line’s characteristic impedance (Zo ) [25].

p
Zo = (R + jωL)/(G + jωC) (1.12)

It is a result from classical electromagnetics that a wave incident upon a boundary

with non-uniform characteristic impedance will be subject to reflection. The scattering (S)
matrix relates voltage waves incident onto electrical ports to those reflected from the ports.

[V − ] = [S][V + ] (1.13)

Vi−
Sij = (1.14)
Vj+
Vk+ =0f ork̸=j

The diagonal of this matrix produces the reflection coefficients of an electrical port (Γi ),

16
effectively quantifying the magnitudes of incident and reflected waves of a given network.
For microwave transistor amplifiers, several matching techniques have been
established. The process of designing a matching network follows a typical procedure
beginning with the determination of the stable regions of operation in the load (ΓL ) and
source plane (ΓS ) as provide by load and source stability circles. When designing for
maximum gain, the conjugate matching technique is then performed. A conjugate match
occurs when:

Γin = Γ∗S (1.15)

Γout = Γ∗L

Assuming a lossless match is achieved, where no power is lost at the interface, the
maximum amplifier gain will result. One limitation of conjugate matching is the trade-off
between the magnitude of the reflection coefficient and the resulting bandwidth of that
match. In other words, to achieve the requisite lossless match the performance is limited to
a narrow band of frequencies. By introducing a mismatch, the match’s bandwidth can be
expanded or a specific gain value can be achieved. Design for a specific gain is typically
accomplished by plotting constant-gain circles on the ΓL and ΓS planes with the help of
a simulation tool. A helpful metric in evaluating the impact of a mismatch on gain is the
maximum available gain (MAG) or, if in a stable region, maximum stable gain (MSG).

|S21 |
M SG = (1.16)
|S12 |

These metrics compute the power gain possible in the case of an ideal match at the input
and output of the circuit. Many of these techniques rely on the assumption of an amplifier
behaving unilaterally, where |S12 | is small enough to ignore in calculations. The error from
this assumption can be approximated using the unilateral figure of merit, U . If the error is
on the order of 0.1dB, the unilateral approximation can be justified.

17
 |S12 ||S21 ||S11 ||S22 |
U= (1.17)
(1 − |S11 |2 )(1 − |S22 |2 )
1 G 1
2
< <
(1 + U ) GU nilateral (1 − U )2

The techniques for establishing a broadband match are more involved and include
compensated matching networks, resistive matching networks, negative feedback, balanced
amplifier topologies and distributed amplifier systems.

18
 CHAPTER 2
LDMOS-BASED DIFFERENTIAL AMPLIFIER DESIGN AND
IMPLEMENTATION

The objective of the study was to evaluate the feasibility of applying LDMOS to
high-voltage comparator design. This was accomplished through the development of a
basic differential amplifier (Figure 1.2) where transistors Q1 and Q2 were replaced with
LDMOS while standard n-channel and p-channel MOSFETs were used for the current
source and current mirror respectively. The differential amplifiers were implemented and
tested in small-signal and large-signal regimes to evaluate the circuit’s performance.
The study began with a part selection for the LDMOS, PMOS, and NMOS.
After verifying the device models, the base differential amplifier topology and biasing
configuration were determined through simulation. These activities led to the development
of the first prototype. Due to the discrepancy between the intended application for the
power amplifier transistors versus this project’s use case, simulation and measurement
were performed concurrently to evaluate the applicability of simulated results to physical
differential amplifier performance. The behavior recorded from the initial prototypes
informed the final stage of design and simulation, which focused on S-parameter analysis
and associated metrics to improve performance in the RF domain.

2.1 Design and Simulation of Prototype Differential Amplifiers

2.1.1 Transistor Selection

LDMOS

The search for a commercial-off-the-shelf (COTS) LDMOS focused on three metrics:

gate-source voltage range, drain-source breakdown voltage, and turn-off frequency. The

19
criteria for gate-source voltage range was set to improve the input voltage range over
existing sub-10nS comparator designs by an order of magnitude. The drain-source
breakdown voltage was selected to minimize DC power consumption by restricting the
part search to LDMOS with the lowest commercially available supply voltages (i.e. 50V).
Finally, devices with turn-off frequencies below 10GHz were not considered to ensure high
speed operation of the comparator was not limited at the device level.
To achieve these targets, the search focused on LDMOS designed for wide-band PA
applications with special interest in dual package arrangements. A dual package device
ideally minimizes the stochastic process mismatches between the two devices forming the
amplifier’s differential pair.
The search for an LDMOS ended with the selection of MRFE6VP5150N RF power
LDMOS transistors from NXP. The product is a dual package LDMOS featuring
unmatched inputs and outputs, integrated stability enhancements and electrostatic
discharge (ESD) protection, and a low thermal resistance TO-270WBG-4 package. In PA
applications, this LDMOS typically achieves 26dB of power gain at a drain efficiency of
70.3% when tested at 230MHz. A brief outline of its electrical characteristics is collected
in table below.

Table 2.1: MRFE6VP5150N Characteristics

Parameter Value
VGS,range 16V
V(br)DS 133V
Characterized Bias Point (VDD , Iq ) 50V, 100mA
Advertised Bandwidth 1.8-600MHz
Vth (typ.) 2.4V
Reverse Transfer Capacitance Crss (typ.) 0.8pF
Output Capacitance, Coss (typ.) 45.4pF
Input Capacitance, Ciss (typ.) 96.7pF

20
PMOS

The p-channel MOSFETs were similarly selected for a V(br)DS greater than 50V and high
bandwidth of operation (> 10GHz), as characterized by its cutoff frequency, fT . The
gate capacitance, commonly reported in device data sheets, was used to approximate the
transistor bandwidth. If a forward trans-conductance of 150mS is assumed and a minimum
cutoff frequency set at 10GHz, the small signal input capacitance must be less than 2nF.
Ideally, the selected PMOS will be in a dual package, increasing the likelihood of device
matching.
The PMOS was selected for a breakdown voltage (VDS,max ) above 50V and a wide
bandwidth of operation. The selected part was the automotive-grade BSS84AKS dual
P-channel Trench MOSFET from Nexperia in a small SOT363 package. A brief outline
of its electrical characteristics is shown in the table below.
Table 2.2: PMOS Characteristics

Parameter Value
VGS,max -20V
Vth (typ.) -1.6V
VDS,max -50V
ID,max -160mA
Propogation Delay (typ.) 18nS
Forward transconductance (typ.) 150mS
Reverse Transfer Capacitance Crss (typ.) 1.3pF
Output Capacitance, Coss (typ.) 4.5pF
Input Capacitance, Ciss (typ.) 24pF

NMOS

The n-channel MOSFETs tail transistor was selected for a maximum current carrying
capacity of 200mA. Assuming the LDMOS has a standard 50V supply voltage, this
maximum current produces 10W of power dissipation. In this study, the differential
amplifier will be designed to minimize power dissipation and the 10W of capacity provided
by the tail transistor is sufficient. The prescribed continuous forward current rating must

21
also correspond with the expected LDMOS bias current, and therefore NMOS selection
should occur after an LDMOS has been chosen.
The n-channel tail transistor was selected for a maximum continuous current of 200mA
in a surface mount package. The DMN67D7L n-channel MOSFET from Diodes Inc.
features low on-resistance, low gate threshold, and low input capacitance for fast switching
speeds, all in an SOT23 package. A brief outline of its operating characteristics is shown
in the table below.

Table 2.3: NMOS Characteristics

Parameter Value
Vth 0.8-2.5V
VDS,max 60V
ID,max 210mA
Propogation Delay (typ.) 4.3nS
Reverse Transfer Capacitance Crss (typ.) 2.5pF
Output Capacitance, Coss (typ.) 4.1pF
Input Capacitance, Ciss (typ.) 22pF

2.1.2 Model Verification

Simulation activities took place using Keysight’s Advanced Design System (ADS). Models
provided by the manufacturers were imported into ADS and individually verified through
comparison between simulated performance and values reported in data sheets.

LDMOS

To verify the LDMOS model, a reference design was replicated in ADS. In this case, a
broadband PA reference design was chosen (Figure 2.1).
Resistors, inductors and capacitors were simply represented by their corresponding
default ADS models, while all transmission lines were modeled using ADS’s ”MLIN”
model. The substrate was defined to match the 0.03” RO4350B substrate noted in the
reference design’s bill of materials (Figure B.2), and the associated model parameters

22
 Figure 2.1: Reference design taken from the LDMOS data sheet [26]

are reported in Table 2.4. Transmission line dimensions and coaxial cable (COAX1 or
TL1) parameters are reported in Table B.1. The completed ADS schematic can be seen in
Figure 2.2.

Table 2.4: Substrate Model Parameters

Parameter Value
H 30 mil
ϵr 3.66
µr 1
σ 1e50
T 1.4 mil
T anD 0.0037

Figure 2.2: The ADS circuit schematic created from the provided reference design [26]

Two classes of simulations were run on the reference design, a decision motivated
by the two sets of characterization data provided in the data sheet. Designed for RF PA
applications, the performance characteristics provided by the manufacturer were circuit
level and tied to specific reference designs. When a comparator is abstracted into larger

23
 Table 2.5: PA Simulation Configuration

Parameter Value
Vdd 50V
Vgg 2.64V
Port Terminations 50Ω

electrical systems, it is assumed that the circuit will perform similarly over a wide range of
frequencies. Following this, from the two reference designs provided by NXP, a 230MHz
narrow-band design and a broadband 87.5-108.5MHz design, the broadband design was
selected (Figure 2.1). For this design, the manufacturer both plots power gain (dB), output
power (W), and drain efficiency versus across a wide range of frequencies and tabulates
this data at three specific points, as recorded in Table 2.6.
The simulation approached these two sets of data separately. First, power gain
data from the data sheet was be replicated using an S-parameter simulation from 10 to
100MHz, capturing the model’s behavior across a wide range of frequencies. Due to
the minimal technical detail on the gate-source biasing arrangement of the reference, the
ADS optimization engine was used to determine the requisite biasing voltages to produce
a 100mA bias current under a 50V supply voltage. Simulation configuration details are
shown in Table 2.5.
Next, a first order harmonic balance (HB) simulation was run at the three frequencies
listed in Table 2.6 (87MHz, 98MHz, and 108MHz) at a fixed 32dBm input to create
a detailed image of model performance across the target band . From this series of
simulations, the power gain (dB), drain efficiency (%), and output power (W) were
recorded.
Output power was calculated with the following formula:

∗
ℜ(Vload Iload )
Pout,W = (2.1)
2

After conversion to dBm,

24
 Pout,dBm = 10log(Pout,W ) + 30 (2.2)

The power gain was calculated as

GaindB = Pout,dBm − Pin (2.3)

Where Pin is a variable defined in the simulation, in this case 32dBm. To calculate the
drain efficiency, the DC input power is required. This was calculated using the following
formula:

PDC = ℜ(Vdd ∗ Iq ) (2.4)

Finally the efficiency can be obtained by taking the magnitude of the output power
versus DC input power

Pout,W
ηD = (2.5)
PDC

The MRFE6VP5150N model provided by NXP is composed of two parts. The first is
the ADS 2022 RF High-Power base model, with a device-specific MRFE6VP5150N RF
High-Power non-linear F ET 2 model. The power gain (dB), output power (W), and drain
efficiency versus across a wide range of frequencies is reported in the data sheet. This
performance is summarized in Table 2.6.

Table 2.6: Reported LDMOS Performance in a Broadband Amplifier

f (MHz) G (dB) ηD (%) Pout

87.5 22.7 74.6 187
98 22.8 77.1 191
108 22.5 77.8 179

When compared to reported values, the S-parameter simulation shows less consistency
across frequency with a net gain variation of approximately 2dB across the band versus the

25
reported 0.5dB. Simulated behavior, although demonstrating more significant variations,
matches reported trends with a maximum between 95 and 100MHz and a minimum at
108MHz. On average, the power gain across the band is simulated to be an average of 1dB
below the reported value.
These results are further supported by the harmonic balance simulation, with increased
variation across frequency and decreased magnitude of the power gain. The results in
Table 2.7 show an idealized drain efficiency around 16% above reported values. This
increase in efficiency trickles down into a 8W to 13W increase in output power at 98MHz
and 87MHz respectively. The 108MHz simulation sees a significant decrease in both output
power and power gain, dropping below values reported in Table 2.6, further supporting the
claim that the model sees more severe performance variations with frequency than the
corresponding physical circuit.

Table 2.7: Simulated LDMOS Performance in a Broadband Amplifier

f (MHz) G (dB) ηD (%) Pout

87 21.0 93.9 201
98 20.9 92.4 199
108 18.9 93.7 124

The results from these two simulations led the researchers to conclude that the model
is a sufficient representation of the physical device to continue to the next design phase.

PMOS and NMOS

The PMOS and NMOS model verification compared the device’s reported ID − VDS
behaviour to simulated values. The range of VDS and VGS were selected to match the ranges
reported in the data sheet, and are presented in Table 2.9 and Table 2.8 for the PMOS and
NMOS respectively.
The NMOS simulation was configured simply, using a FET curve tracer macro within
ADS. Due to the inverted nature of PMOS biasing and operation, the simulation was
specially configured to produce IV curves in the first quadrant, matching those reported

26
by the manufacturer.

Table 2.8: NMOS Verification Parameters

Parameter Starting Value Final Value Points
VGS 2.5V 4.5V 5
VDS 0V 5V 41

Table 2.9: PMOS Verification Parameters

Parameter Starting Value Final Value Points
VGS -2.5V -4V 4
VDS 0V -4V 41

The model of BSS84AKS provided by Nexperia is a SPICE parameter file. The DC IV

curves were simulated per Table 2.9 and compared against values reported in the data sheet
in Figure 2.3. Comparing the two IV curves, the model demonstrates a lack of channel
length modulation, or output trans-conductance, in the saturation region. Additionally,
the model underestimates currents at higher gate-source voltages, as seen by the 30mA
difference in saturation current for a gate-source voltage of -3.5V.

Figure 2.3: BSS84AKS data sheet IV curves (Left) versus simulation (Right)

The model of DMN67D7L provided by Diodes Inc is a SPICE parameter file. The
DC IV curves were simulated per Table 2.8 and similarly compared in Figure 2.4. In
this case, the threshold voltage of the model appears to be lower than that of the typical
device whose IV curves are reported in the data sheet. Although the manufacturer does

27
not provide a typical threshold voltage, the minimum value is reported to be 0.8V and
the maximum 2.5V (Table 2.3), suggesting the curves reported in the data sheet represent
the maximum case. It can therefore be expected that on average, that the simulated drain
currents will be larger than the values reported in the data sheet for a given gate-source
voltage. Additionally, at either high gate voltages (> 4V ) or high drain-source voltages
(> 4V ) the model overestimates drain current.

Figure 2.4: DMN67D7L data sheet IV curves (Left) versus simulation (Right)

2.1.3 Preliminary Design Simulation

After the verification of the individual device models in the previous stage, a preliminary
design was simulated to evaluate the basic performance of a single stage differential
amplifier. The design was synthesized from the imported models, and the core differential
amplifier topology was produced by adapting the PA reference design simulation discussed
in the previous section. This modified circuit is displayed in Figure 2.5 with trace
dimensions in Table 2.10.
The ADS optimization engine was used to adjust transmission line dimensions for
maximum gain in operation at the upper limit of the target frequency, 30MHz, while
substrate parameters were held constant. In this initial simulation, an ideal current source
was used in place of the selected NMOS to reduce design complexity. At this point, the
supply voltage and biasing current were carried over from the LDMOS biasing conditions
reported in the data sheet as a supply voltage of 50V and drain current of 100mA. This

28
 Figure 2.5: The ADS schematic for the preliminary design verification

Table 2.10: Preliminary Design Trace Dimensions

Trace W (mil) L (mil)

Z1 2582 4925
Z2 2868 82.2
Z3 2980 4177
Z4 2487 681
Z5 337 2824
Z6 775 855
Z7 77.6 58.5
Z8 55.8 563
Z9 47.8 4000
Z10 875 50.2

preliminary design was simulated to obtain its DC biasing voltages and S-parameters
between 10MHz and 100MHz. Details on the simulation configuration is included as
Table 2.11.

2.2 Circuit Implementation

The goal of this design stage was the measurement of the basic circuit’s differential
amplification, common mode rejection, non-linear behavior and biasing voltages.
All designs were realized using KiCAD, an open-source electronic design automation
(EDA) software. Footprints for the NMOS, PMOS and additional components were taken
from online repositories and verified before their use in the layout. Alternatively, the

29
 Table 2.11: Preliminary Design Simulation Configuration
Parameter Value
Vdd 50V
Vgg 0.47V
Port Terminations 50Ω
Start Frequency 10MHz
Stop Frequency 100MHz
HB Fundamental Frequency 30MHz
HB Harmonic Order 1

LDMOS footprint was custom designed from the mechanical drawings included in the
datasheet. PCBs were assembled using an LKPF Protoflow S reflow oven. Trace widths
were calculated using ADS’s LineCalc ultility for a characteristic impedance of 50Ω at
30MHz as a coplanar waveguide with topside and backside ground pours.

2.2.1 Lab Equipment

The equipment used for test and measurement is recorded in Table 2.12 below.

Table 2.12: Test and Measurement Equipment

Function Manufacturer Model Description
Power Supply Agilent E3630A Triple Output DC Supply
High Voltage Power Supply Agilent E3634A DC Supply, 50V, 4A
Function Generator Agilent 33522A 30MHz Function Generator
Multimeter Agilent 34401A 6 1/2 Digit Multimeter
Oscilloscope Tektronix DPO5104 Digital Phosphor Oscilloscope, 1GHz, 20Gs/s, 4ch
Network Analyzer Agilent E5071C Vector Network Analyzer, 9kHz to 20GHz

2.2.2 Test Configurations

Test configurations remained fairly constant across tests and prototypes. All signal
connections were made using male-male SMA cables with accompanying SMA-BNC
adapters at either the oscilloscope or function generator when necessary. Power was
provided using male banana connectors and MiniGrabber test clips. The clips enable
safe connection to the standard 0.100” header pins used on the printed circuit board
(PCB)’s power delivery network. Oscilloscope connections were set to 50Ω impedance,
DC coupling, except where declared otherwise.

30
2.2.3 Prototype 1

This prototype focused on verifying the fundamental behavior of an LDMOS based single
stage differential amplifier in DC, small signal, and large signal regimes. To this end, the
prototype was stripped to its core components: differential pair, current mirror load, tail
transistor, and newly introduced resistive DC biasing networks. This decision notably omits
the distributed impedance matching network on the input or output of the amplifier. The
schematic and layout of the design as captured in the EDA software is shown in Figure 2.6
and Figure A.1 respectively.

Figure 2.6: Schematic of Prototype 1

Table 2.13: Prototype 1 PCB Parameters

Parameter Value
Layers 2
Substrate Material FR4
Substrate Thickness 23.6mil
Trace Width 37.7mil
Copper Thickness 1oz

DC measurements took place on versions of the prototype board where the DC blocking
capacitors were replaced with 0Ω shorts and gate voltages were provided by off-board
power supplies. For these tests, the circuit was unloaded, as the PCBs were not connected

31
to the function generator or oscilloscope. DC measurements began at a supply voltage of
25V as a precaution, before continuing to the full 50V supply. The critical node voltages
measured by digital multi-meter probe were both LDMOS drains (Vd1 , Vd2 ), their tied
source (VS ), and the LDMOS gate voltages (Vg1 , Vg2 ).
For small-signal measurements, the output of the differential amplifier was AC coupled
to the oscilloscope’s channel two. The node connected to the gates of the PMOSs forming
the current mirror was connected to channel three. The function generator was teed off at
channel one, which was set to high impedance and connected to the prototype’s positive
input (vin,+ ). In this case, the other input was left floating. The sinusoidal input of the
function generator was a kept at a single low frequency (3kHz) and amplitude (10mVpp ).
The gain was calculated using the oscilloscope’s ’Amplitude’ measurement function.
To improve the understanding of the circuit’s behaviour under large input voltages,
large-signal tests continue from the previous measurement configuration, incrementally
increasing the amplitude of the input wave until saturation is observed at the output. Above
this level, LC oscillations interfere with measurement. At this point, the 1.6Vpp input is
changed to a square wave. In this configuration, rise and fall times were measured using
the oscilloscope’s measurement functions.
Details on measurement equipment, lab configuration, as well as PCB design and
assembly can all be found in the appendix.

2.2.4 Prototype 2

Insights from the production of the first prototype led directly to the development of a
second, improved prototype. A critical design change between iterations is the inclusion
of a configurable negative supply voltage for the tail transistor and DC biasing network
simplification. The PCB layout was redesigned to simplify power routing, increase power
via dimensions, and accommodate a change in board thickness. The new design schematic
and layout can be seen in Figure 2.7 and Figure A.3 respectively.

32
 Figure 2.7: Schematic of Prototype 2

Table 2.14: Prototype 2 PCB Parameters

Parameter Value
Layers 2
Substrate Material FR4
Substrate Thickness 63mil
Trace Width 75.2mil
Copper Thickness 1oz

The series of DC and small signal tests were repeated for this design iteration. DC
voltage measurements now included the gate bias voltage of the tail transistor, Q5 , yet
otherwise remained the same. However, in this case, AC small signal measurements were
taken by hand using horizontal cursors due to the presence of significant output noise.
Additionally, measurements were expanded to include several frequency points, one per
decade from 1kHz to 10MHz.
After collecting data from the two prototypes, there was sufficient evidence that further
design efforts were necessary to reach the performance targets. This design re-work began
with the simulation of prototype two in ADS for a stability analysis motivated by laboratory
results. The simulated prototype two schematic is included in Figure 2.8 with associated
simulation parameters recorded in Table 2.15.

33
 Figure 2.8: ADS Schematic of Prototype 2

Table 2.15: Prototype 2 Simulation Configuration

Parameter Value
Vdd 50V
Vss -5V
Port Terminations 50Ω
Start Frequency 10MHz
Stop Frequency 100MHz

The stability analysis was performed using both Rollet’s stability factor (K) as well as
load and source stability circles. The Rollet stability factor is derived from the S-parameters
using the following equations (assuming |∆| < 1):

1 − |S11 |2 − |S22 |2 + |∆|2

K= (2.6)
2|S12 ||S21 |

∆ = S11 S22 − S12 S21

If both K > 1 and |∆| < 1, then the circuit is unconditionally stable at that frequency.
The K factor can be easily computed in ADS using the ’stab fact()’ command, whose only
argument are the S-parameters.
An alternate method for analyzing the stability of a circuit is to use load and source

34
stability circles. These circles are plotted on the load and source impedance or reflection
coefficient planes on smith charts. If the center of the smith chart is included inside the
stability circle, and |S11 | < 1 for the source plane or |S22 | < 1 for the load plane, then
the region inside of the circle is the stable region. If either of these conditions are false,
then the region inside the circle is the unstable region. The load and source stability circles
can be easily calculated in ADS using the ’l stab circle()’ or ’s stab circle()’ commands,
whose arguments are the S-parameters and number of points constituting the circle.

2.3 LDMOS-Based Differential Amplifier Design and Implementation

The results of prototype two’s stability analysis directly informed the final stages of circuit
design.

2.3.1 Impedance Matching Considerations

S-parameter simulations of prototype two indicated poor input and output matching.
Several matching network design procedures were attempted to improve circuit
performance. At the target HF frequencies, the distributed element matching requires
excessively large trace dimensions (as seen in Table 2.10) and therefore avoided for
this design. Instead, first, a broadband match was designed combining narrow-band,
discrete element simultaneous conjugate matching on a smith chart with subsequent ADS
optimization. For a decade-wide match, this process was not able to achieve the target
reflection coefficients below -10dB. Finally, a broadband match was designed using input
resistive matching aided by gain bandwidth extension by negative feedback. This design
additionally results in circuit stabilization due to the shunting resistance at the input port.

2.3.2 Feedback Loop Design Considerations

The results of the stability and impedance matching simulations motivated the design of a
negative feedback network. The feedback factor, β, was calculated using classic feedback

35
 ′
theory for gain bandwidth extension. In this equation, f is the extend gain bandwidth, f is
the original gain bandwidth, AOL is the open loop gain, and β is the feedback factor.

′
f = f (1 + AOL β) (2.7)

The result of this calculation was implemented using a resistive feedback network that
assumed a 50Ω termination on the reference input (e.g. vin− ). The feedback resistor was
accompanied by a DC blocking capacitor, which controls the amount of feedback at low
frequencies and an inductor, which controls the amount of feedback at high frequencies.
The inductor is particularly useful for preventing phase inversion.

2.3.3 Trade-off Analysis

At this point, the topology was set and a trade-off analysis was conducted to optimize the
design parameters and circuit performance. The four variables included in this analysis and
their default values are recorded in Table 2.16.

Table 2.16: Trade-off analysis parameters and default values

Parameter Default Value

I 91mA
VDD 50V
Rstb 220Ω
Rf b 200Ω

During the analysis, one parameter was varied while the others were held constant.
the resulting variations in flat-band gain, gain bandwidth, and minimum noise figure were
recorded. The gain bandwidth was calculated from the -3dB point from the flat-band
gain. The minimum noise figure (N Fmin ) is a value provided by ADS based on the
device models provided to the simulation. The thermal noise analysis took place at a
simulation temperature of 18.65◦ C and a model temperature of 25◦ C. For the analysis
of feedback resistance, a quantity is included defined as Rstb,max which represents the
maximum stabilization resistance that still results in unconditional stability between 10

36
and 100MHz.

2.3.4 Performance Optimization

After this analysis, the design was optimized to best achieve the design targets. This circuit
can be seen in Figure 2.9. This LDMOS-based differential amplifier design features an
asymmetrically split voltage supplies (Vss and Vdd , see Table 2.17) with simple resistive
divider biasing networks composed of R1 with R2, R3 with R4, and R5 with R6 for Q1 ,
Q2 and Q5 respectively. These biasing networks are accompanied by 10nF DC blocking
capacitors (C1, C2, C6) and 3.3uH AC chokes (L1, L2) chosen to block a 30MHz AC
signal from entering the power supply network. The design also exhibits a stabilization
resistor, R9, that doubles as a broadband resistive match. Negative feedback was supplied
by C7, R8 and L3 while the reference input was terminated by C2 and R7 for symmetry.
Finally, bypass capacitors C3, C4, and C5 were chosen to bypass any power supply noise
between 1MHz and 100MHz.

Figure 2.9: ADS Schematic of the final design

37
 Table 2.17: Final Design Simulation Configuration
Parameter Value
Vdd 25V
Vss -5V
Port Terminations 50Ω
Start Frequency 10MHz
Stop Frequency 100MHz
IT 66.6mA

Table 2.18: Prototype 3 PCB Parameters

Parameter Value
Layers 2
Substrate Material Rogers RO4350B
Substrate Thickness 30mil
Trace Width 66mil
Copper Thickness 1oz

2.3.5 Circuit Implementation

The finalized design was recreated in EDA software. For this design, the substrate
material was upgraded to match the material listed in the original LDMOS reference
design. This change minimizes variations in dielectric constant and therefore improves RF
performance. This design also returns to a thinner substrate to minimize trace widths for
routing considerations. The board’s layout was also optimized to remove any extraneous
trace stubs and simplify electrical paths. The circuit layout is reported in Figure A.5.
DC and small signal tests were repeated for this prototype. Due to project constraints,
measurements are cursory but still provide valuable insight into amplifier performance as
compared to simulation.

38
Figure 2.10: Schematic of Prototype 3

39
 CHAPTER 3
RESULTS AND DISCUSSION

3.1 Prototype Differential Amplifiers

3.1.1 Exploratory Simulations

The preliminary design was adapted from the broadband power amplifier reference design
provided by NXP for operation around 30MHz and simulated for its S-parameters between
10MHz and 100MHz. The simulations illustrate forward gain above 20dB and a unity
gain frequency of approximately 40MHz. The gain roll-off is log-linear, suggesting one or
more poles created in the interaction of distributed elements, device models, and passive
components rest near 40MHz. A very narrow band of reflection coefficients of a magnitude
below 0dB occurs at 30MHz and indicates that the ADS optimization engine created a
narrow-band match through the modulation of transmission line dimensions to maximize
gain at 30MHz. Although the s-parameter results provide insight into the frequency domain
performance of the preliminary design, the non-physical dimensions of the microstrip
transmission lines and unrealistic passive component values reduce the applicability of
these results to a commercial design.
Instead, the simulation contributes valuable information on the necessary DC biasing
levels for the first prototype. The bias point remained at a quiescent current of 100mA with
a 50V supply. Analysis of DC measurements indicate that the target gate-source voltage
for the LDMOS is 2.6V for these conditions. Notably, the ideal current source establishes
a negative drain-source voltage of -2.17V. This suggests that the NMOS used as a current
source in prototypes requires either a high DC drain-source resistance or negative voltage
supply to operate in saturation.

40
3.1.2 Measurement Results

The key difference between the two developed prototypes lie in their biasing networks.
Testing of the first prototype indicated the tail transistor was not operating in saturation
mode due to an insufficient drain-source voltage. This was accommodated in the second
prototype through the addition of a negative supply at the source of Q5 . Additionally,
the second prototype features a simplified fixed value resistive biasing network where the
first prototype offered either biasing from either a power supply or variable resistor divider
arrangements.

Version 1

First, DC voltage measurements were taken of the prototype circuit. The measured source
voltage, VS , of 80mV shows that the tail transistor, Q5 , is not operating in saturation. This
supports the behaviour seen in simulation. Measurements also demonstrate that the circuit
has a drain voltage mismatch of 1.7V. Although improvements were attempted by adjusting
on-board potentiometers and LDMOS gate biasing voltages, the granularity of control was
too course to compensate completely. The source of the drain voltage mismatch could
possibly result at either the device or circuit level. Due to the intended application as a
power amplifier, the two LDMOS within the MRFE6VP5150N’s package are not matched
devices and their gate-source threshold voltages are not well controlled. The data sheet
reports a range in gate threshold voltages 0.5V above and below the typical value of 2.4V,
making it likely the devices are not well matched. Additionally, poor control over the value
of passive components and any design asymmetry exacerbates this challenge, which was
noted for improvement in the next design iteration.
Next, small-signal testing of the prototype demonstrates the proper function of the
differential amplifier with a high differential gain of 52dB. The common-mode rejection
ratio (CMRR) was measured by providing two in phase signals to the differential amplifier
inputs. With a common-mode gain of 14dB, the CMRR was calculated to be 38dB. Given

41
the mismatches discovered in DC testing, this result is within expectations.
Finally, large-signal testing was performed. The test configuration from small-signal
differential gain measurements was maintained with the amplitude of the input signal
slowly increased until output saturation was observed. At an input amplitude of amplitude
of 700mVpp and the amplifier’s output shows clean comparator action as the output switches
between ±10V . The screen capture of this case is shown in Figure 3.1, where the input
sinewave is shown in yellow and the amplifier’s output is shown in purple.

Figure 3.1: Large-signal output saturation of prototype one with the 3kHz sinusoidal input
(yellow) and resulting output signal (purple) both at 3V/div

Additionally, undesired low-pass filtering on the input square wave was observed at
3kHz. After analyzing the prototype, this filtering was determined to be a result of the
decision to short the DC blocking capacitors. This was also noted for correction in the
following design iteration. Despite the filtering preventing testing in the target frequency
range, rise and fall times of 5.1µS and 4.3µS were measured at an input frequency of 3kHz.

Version 2

After the second prototype was developed, testing began with DC measurements. The
simplification of the resistive biasing network and change to a supply-derived biasing
scheme resulted in a reduced drain voltage mismatch of 400mV. Additionally, the
reconfiguration of the tail transistor layout to allow a negative 5V supply successfully

42
places Q5 in saturation with a source voltage, VDS5 of -4.95V.
With these improvements, prototype two was tested in the target HF band. However,
as small-signal testing began, undesired oscillations were observed between 90MHz and
100MHz. These oscillations were likely a result of improper bypassing that occurred
in response to the filtering observed in prototype one. In small-signal testing at
low frequencies, these oscillations present themselves as noise, introducing significant
measurement uncertainty. As the input frequency increases, the oscillations can be seen
more clearly. At frequencies around 30MHz, the oscillations create destructive interference
and subsequently, signal distortion. The presence of these oscillations was an indicator
of conditional stability and suggested a return to more in depth design and simulation
activities.
Despite the interference introduced by the improper bypassing, the small-signal gain
was calculated by hand at a several frequencies. The range of data collection was limited
by the effects of the oscillations to 5kHz and 1MHz, with measurement uncertainty
increasing beyond these bounds. Although the second prototype successfully enabled test
and measurement in the HF band, the gain was significantly reduced to approximately a
flat-band value of 23dB between 100kHz and 1MHz.
The results of the second prototype testing motivated further investigation in simulation.
To this end, the circuit design was simulated in ADS. The simulated -3dB gain bandwidth
matches the measured value at high frequencies, with roll-off occurring at 1MHz. At lower
frequencies, however, the roll-off ends one decade earlier at 10kHz. Additionally, the
simulated flat-band gain is approximately 34dB, 11dB greater than measured performance.
This is partially explained by measurement interference caused by the instability and
oscillations documented in the previous section. The simulated reflection coefficients show
a near 0dB match up to 10MHz, with a small match up to 100MHz peaking at -2.3dB
around 30MHz for both the input and output coefficients.
It is clear from these results that poor impedance matching at the input and output

43
degrades circuit performance. Additionally, gain degradation begins at 1MHz and severely
impacts performance in the target region. Both of these facts motivate negative feedback
for bandwidth extension.
The S-parameter simulation enables the use of several well established stability metrics.
First, stability was analyzed using Rollet’s stability factor. The results indicate that
unconditional stability only exists below 72kHz and between 6.6MHz and 55MHz. This
result is further supported by load and source stability circles, which were generated
between 1MHz and 40MHz. The circles corresponding to the 1-5MHz band on the load
stability circle move within the unit smith chart, indicating a wide range of load conditions
that produce instability. When the analysis is extended to 100MHz, the frequency of
measured oscillations, the results also indicate conditional stability between 90MHz and
100MHz.
Given the poor input matching over the desired band, low gain bandwidth and circuit
instability, the team decided to pursue resistive stabilization at the input calculated through
inspection of the admittance input stability circle smith chart. If the stabilizing resistance
is selected to be near 50Ω, this additional circuitry provides the added benefit of improving
input and output matching.

3.2 LDMOS-Based Differential Amplifier

3.2.1 Negative Feedback Calculations

The simulation results indicate the second prototype’s current bandwidth, f , is 13.8MHz
and its open loop gain, AOL is ideally 35dB. Applying Equation 2.7, the gain bandwidth can
be extended to 30MHz by introducing a feedback factor, β of 0.02. Assuming the reference
input, defined as vin− here, is terminated by 50Ω, a resistive divider feedback network can
be formed by connecting a 2.45kΩ resistor from the output back to vin+ . This fairly crude
calculation provides a starting point for the tuning of both shunt or stabilizing resistance
and feedback resistor through ADS. A DC blocking capacitor of 1nF was included to block

44
low frequency components, while simulation indicated that a 680nH inductor limited the
influence of negative feedback above 30MHz.

3.2.2 Trade-off Analysis

The results of a trade-off analysis can be seen in the following tables beginning with the
combined impact of feedback and stabilization resistance on gain, bandwidth, and noise
figure.

Table 3.1: Feedback Resistance Trade-off Analysis

Parameter Low Extreme High Extreme
Rf b 7Ω 200Ω 600Ω Open
Rstb,max 100Ω 220Ω 480Ω 1.43kΩ
Flat-band Gain 2.9dB 16.3dB 23.5dB 33dB
Bandwidth 200MHz 100MHz 50MHz 14MHz
N Fmin 6.2dB 5.3dB 3.9dB 2.5dB

The results of this investigation indicate that as stabilization resistance approaches

50Ω, power dissipation increases, gain decreases, the low frequency match improves, and
noise figure increases. Table 3.1 demonstrates that as the amount of feedback increases,
a corresponding decrease in feedback resistance Rf b , gain decreases and bandwidth
increases. This result follows the behaviour dictated by feedback theory (Equation 2.7).
Next, the impact of circuit bias on performance was examined.

Table 3.2: Bias Current Trade-off Analysis

Parameter Low Extreme Control High Extreme
Iq 3.4mA 31mA 91mA 198mA
N Fmin 8.9dB 5.5dB 5.6dB 5.3dB
Flatband Gain 4.5dB 14.4dB 16.3dB 17.3dB
Bandwidth 20MHz 56MHz 100MHz ¿100MHz

The analysis indicates that as bias current increases, power dissipation increases, gain
increases, bandwidth increases, and noise figure weakly decreases. Similarly, as supply
voltages increase, power dissipation increases, gain weakly increases, and bandwidth
increases.

45
 Table 3.3: Bias Voltage Trade-off Analysis
Parameter Low Extreme Control High Extreme
VDD 0V 15V 50V 100V
N Fmin 6.4dB 5.3dB 5.3dB 5.3dB
Flat-band Gain 15dB 16.2dB 16.3dB 16.9dB
Bandwidth 10MHz 75MHz 100MHz 100MHz

3.2.3 Performance Optimization

The results of the trade-off analysis were taken to produce a comparator that meets the
performance targets. In other words, a design with minimal power dissipation, maximum
flat-band gain, input and output matching below -10dB, and unconditional stability between
10 and 100MHz. It is clear from Table 3.3 that a moderate reduction in supply voltage will
only result in a minor decrease in bandwidth. Therefore, the supply voltage can be reduced
to 25V and the associated bandwidth can be recovered by introducing more negative
feedback. To realize this, the stabilization resistance was chosen through simulation to
be 90.9Ω and the feedback resistance to be 625Ω.
The S-parameters of the final design are shown in Figure 3.2 and Figure 3.3. Notably,
after reaching the target bandwidth, the comparator’s flat-band gain is only 20dB. However,
both bandwidth and matching performance meets the design target.

Figure 3.2: The simulated forward and reverse gain (S21 , S12 ) of the final design

46
Figure 3.3: The simulated input and output reflection coefficients (S11 , S22 ) of the final
design

The stability analysis is shown in Figure 3.4 and confirms the circuit’s unconditional
stability between 10 and 100MHz.

Figure 3.4: Stability factor of the final design across frequency

3.2.4 Preliminary Measurements

The third PCB most notably includes the addition of the negative feedback loop and
stabilization resistor. It also includes a ”hybrid” 1206/0805 pad at R1 to enable assembly
with two parallel 1W 180Ω resistors to further improve the circuit’s power handling

47
capabilities.
DC measurements of the board confirm simulated values and the design achieves the
intended bias point. Sample small-signal measurements at 10MHz and 30MHz demonstrate
gains of 18.6dB and 13.8dB respectively. Although comprehensive testing could not be
completed, this result indicates more significant gain degradation than the simulated results.
Large-signal testing was performed at an input frequency of 1MHz with an amplitude
of 1Vpp . The circuit produces a 7Vpp output with a rise time of 21.4nS and a fall time of
18.9nS. Inspection of the waveform in the time domain, , illustrate slow transitions that are
likely the cause of insufficient gain.

Figure 3.5: Large-signal output saturation of prototype three with a 1MHz sinusoidal input
(green, 500mV/div) and resulting output signal (yellow, 1V/div)

48
 CHAPTER 4
CONCLUSIONS

This study was designed to explore the feasibility of producing a high-voltage, HF

comparator by leveraging LDMOS technology designed for PA applications. To this
end, the conditions for a successful design were defined in the HF frequency band to a
propagation delay below 10nS, unconditional stability up to 100MHz, a flat-band gain
above 60dB, an input and output match better than -10dB, and a maximum gate-source
input voltage above 10V. Although the simulated design achieves the targeted gain
bandwidth and input voltage tolerance, concessions had to be made in maximum gain and
subsequently propagation delay.
In the development process, a comprehensive trade-off analysis performed in simulation
captures the applicable design space for the given design. These results are supported
by several rounds of measurements, and can serve as a powerful reference for the
design of similar circuits in the future. These laboratory measurements also revealed
several challenges arising from the application of discretely packaged, COTS, devices
including poor device matching and dimension control. Throughout the study, the
circuit demonstrated poor high frequency performance and instability, likely as a result
of increased small-signal capacitance and inductance introduced by the LDMOS, its
packaging, and requisite biasing arrangements. The accommodation of these factors
ultimately resulted in degraded amplifier performance for the target application.
Despite demonstrating a differential gain reaching as high as 50dB at kilohertz
frequencies, the introduction of a necessary DC biasing network and associated energy
storage elements capped low frequency gain at approximately 35dB between 1kHz and
1MHz. At these frequencies, the propagation delay can be expected to be on the order of
hundreds of nanoseconds, placing it among a saturated commercial market of lower speed

49
COTS comparators with input voltage ranges above 10V. Although it has been shown that
the gain bandwidth can be extended into the target frequency range (3-30MHz), the design
trade-off between high bandwidth and gain in this case attaches a step performance and
complexity penalty unique to this design. Without the bandwidth extension, the proposed
design competes against traditional analog IC comparators at an increased cost and size
while losing the novelty of high input voltage tolerance, resulting in the conclusion that
this design is not well suited for the target application. Given further design efforts and
optimizations, it is the opinion of the team that a competitive LDMOS-based differential
amplifier design still remains possible. However, it is clear from simulated and measured
circuit performance that the physical characteristics of these LDMOS does constrain an
LDMOS-based design’s frequency response, and ultimately, its comparator performance.
Despite the poor performance of a discrete element LDMOS comparator, the concept
has yet to be explored at the IC level. Due to the compatible LDMOS and CMOS processes,
an LDMOS based IC comparator overcomes many of the technical challenges faced by
dissimilar material systems and processes. By designing at the IC level, engineers will
gain significantly more control over device dimensions, reduced interconnect lengths and
parasitics, significantly improved transistor matching, and simplified biasing arrangements.
Without the added complexity of re-purposing application specific COTS parts, this suite of
benefits is highly motivating for the development of an IC level LDMOS based high-speed,
high-voltage silicon comparator.

50
Appendices
 APPENDIX A
PROTOTYPE LAYOUTS

A.1 Prototype 1

Figure A.1: Layout of Prototype 1

Figure A.2: Photo of Prototype 1

52
A.2 Prototype 2

Figure A.3: Layout of Prototype 2

Figure A.4: Photo of Prototype 1

53
A.3 Final Design

Figure A.5: Layout of Prototype 3

Figure A.6: Photo of Prototype 3

54
 APPENDIX B
REFERENCE DESIGN [26]

Figure B.1: Reference broadband (87.5MHz-108MHz) power amplifier schematic

provided by NXP

Table B.1: PA Reference Trace Dimensions

Instance W (mil) L (mil)

Z1,Z2 80 280
Z3 80 680
Z4 170 310
Z5,Z6 200 270
Z7,Z8 630 380
Z9,Z10 180 240
Z11,Z12 27 2060
Z13,Z14 150 680
Z15,Z16 240 210
Z17 150 480
Parameter Value
TL1 Inner Diameter 36 mil
Outer Diameter 131 mil
Length 360 mil
Effective Permittivity 2.1
Loss tangent 0.002

55
Figure B.2: Bill of materials for the reference schematic

56
 REFERENCES

[1] R. Dennard, F. Gaensslen, H.-N. Yu, V. Rideout, E. Bassous, and A. LeBlanc,

“Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE
Journal of Solid-State Circuits, vol. 9, no. 5, pp. 256–268, 1974. DOI: 10.1109/JSSC.
1974.1050511.

[2] LM397: Single General-Purpose Voltage Comparator. Texas Instruments, 2016.

[Online]. Available: https : / / www . ti . com / lit / ds / symlink / lm397 . pdf ? ts =
1643080792055.

[3] LMV331, LMV393, LMV339. ST Microelectronics, 2011. [Online]. Available: https:

//www.st.com/resource/en/datasheet/cd00258546.pdf.

[4] “Miniaturized comparators offer portable applications benefits,” 2010. [Online].

Available: https://www.planetanalog.com/miniaturized-comparators-offer-portable-
applications-benefits/.

[5] ADCMP380: Ultra Low-Power Voltage Comparator with Reference. Analog

Devices, 2021. [Online]. Available: https://www.analog.com/media/en/technical-
documentation/data-sheets/adcmp380.pdf.

[6] TL3116, TL3116Y Ultra-fast low-power precision comparators. Texas Instruments,

1997. [Online]. Available: https : / / www. ti . com / lit / ds / symlink / tl3116 . pdf ? ts =
1643056614337.

[7] AD8561: Ultrafast 7ns Single Supply Comparator. Analog Devices, 2016, p. 2.
[Online]. Available: https://www.analog.com/media/en/technical-documentation/
data-sheets/ad8561.pdf.

[8] ADCMP600/ADCMP601/ADCMP602: Rail-to-Rail, Very Fast, 2.5V to 5.5V Single-

Supply TTL/CMOS Comparators. Analog Devices, 2011. [Online]. Available: https:
//www.analog.com/media/en/technical- documentation/data- sheets/ADCMP600
601 602.pdf.

[9] ADCMP551/ADCMP552/ADCMP553: Single-Supply, High Speed PECL/LVPECL

Comparators. Analog Devices, 2015. [Online]. Available: https://www.analog.com/
media/en/technical-documentation/data-sheets/ADCMP551 552 553.pdf.

[10] H. W. Then, M. Radosavljevic, K. Jun, et al., “Gallium Nitride and Silicon

Transistors on 300 mm Silicon Wafers Enabled by 3-D Monolithic Heterogeneous
Integration,” IEEE Transactions on Electron Devices, vol. 67, no. 12, pp. 5306–5314,
2020. DOI: 10.1109/TED.2020.3034076.

57
[11] S. Chevella, D. O’Hare, and I. O’Connell, “A Low-Power 1-V Supply Dynamic
Comparator,” IEEE Solid-State Circuits Letters, vol. 3, pp. 154–157, 2020. DOI:
10.1109/LSSC.2020.3009437.

[12] R. Sangeetha, A. Vidhyashri, M. Reena, R. B. Sudharshan, S. govindan, and J.

Ajayan, “An Overview Of Dynamic CMOS Comparators,” in 2019 5th International
Conference on Advanced Computing & Communication Systems (ICACCS), 2019,
pp. 1001–1004. DOI: 10.1109/ICACCS.2019.8728470.

[13] S. Babayan-Mashhadi and R. Lotfi, “Analysis and Design of a Low-Voltage

Low-Power Double-Tail Comparator,” IEEE Transactions on Very Large Scale In-
tegration (VLSI) Systems, vol. 22, no. 2, pp. 343–352, 2014. DOI: 10.1109/TVLSI.
2013.2241799.

[14] A. M. H. Kwan, X. Liu, and K. J. Chen, “Integrated gate-protected HEMTs and

mixed-signal functional blocks for GaN smart power ICs,” in 2012 International
Electron Devices Meeting, 2012, pp. 7.3.1–7.3.4. DOI: 10 . 1109 / IEDM . 2012 .
6478997.

[15] A. Li, M. Cui, Y. Shen, et al., “Monolithic comparator and sawtooth generator of
AlGaN/GaN MIS-HEMTs with threshold voltage modulation for high-temperature
applications,” IEEE Transactions on Electron Devices, vol. 68, no. 6, pp. 2673–2679,
2021. DOI: 10.1109/TED.2021.3075425.

[16] R. Sun, Y. C. Liang, Y.-C. Yeo, C. Zhao, W. Chen, and B. Zhang, “All-GaN power
integration: Devices to functional subcircuits and converter ICs,” IEEE Journal of
Emerging and Selected Topics in Power Electronics, vol. 8, no. 1, pp. 31–41, 2020.
DOI : 10.1109/JESTPE.2019.2946418.

[17] AD790: Fast, Precision Comparator. Analog Devices, 2014, p. 3. [Online].

Available: https : / / www. analog . com / media / en / technical - documentation / data -
sheets/AD790.pdf.

[18] ADCMP567: Dual Ultrafast Voltage Comparator. Analog Devices, 2020, p. 3.

[Online]. Available: https://www.analog.com/media/en/technical-documentation/
data-sheets/adcmp567.pdf.

[19] ADCMP380: Ultra Low-Power Voltage Comparator with Reference. Analog

Devices, 2021. [Online]. Available: https://www.analog.com/media/en/technical-
documentation/data-sheets/adcmp380.pdf.

[20] R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, 4th ed. McGraw-Hill
New York, 2010, p. 149.

58
[21] M. T. Bohr and I. A. Young, “CMOS Scaling Trends and Beyond,” IEEE Micro,
vol. 37, no. 6, pp. 20–29, 2017. DOI: 10.1109/MM.2017.4241347.

[22] T. Grasser, Hot Carrier Degradation in Semiconductor Devices. Springer, 2014,

ch. 11, pp. 309–339.

[23] S. J. C. H. Theeuwen and J. H. Qureshi, “LDMOS Technology for RF Power

Amplifiers,” IEEE Transactions on Microwave Theory and Techniques, vol. 60,
no. 6, pp. 1755–1763, 2012. DOI: 10.1109/TMTT.2012.2193141.

[24] R. K. Williams, M. N. Darwish, R. A. Blanchard, R. Siemieniec, P. Rutter, and Y.

Kawaguchi, “The Trench Power MOSFET—Part II: Application Specific VDMOS,
LDMOS, Packaging, and Reliability,” IEEE Transactions on Electron Devices,
vol. 64, no. 3, pp. 692–712, 2017. DOI: 10.1109/TED.2017.2655149.

[25] D. M. Pozar, Microwave Engineering. John Wiley & Sons, 2011.

[26] MRFE6VP5150 RF Power LDMOS Transistors. NXP, 2014. [Online]. Available:

https://www.nxp.com/docs/en/data-sheet/MRFE6VP5150N.pdf.

59