SEQUENTIAL LOGIC – FSM CIRCUIT

Question :- This is a Moore state machine with two states, one input, and one output.
Implement this state machine. Notice that the reset state is B.

module top_module(
input clk,
input areset, // Asynchronous reset to state B
input in,
output out);//

parameter A=0, B=1;

reg state, next_state;

// This is a combinational always block

always @(*) begin
case(state)
1'b0 : next_state <= in ? A : B ;
1'b1 : next_state <= in ? B : A;
endcase
end
// This is a sequential always block
always @(posedge clk, posedge areset) begin
if(areset)
state <= B;
else
state <= next_state;
end

// Output logic
assign out = (state == 1'b1) ? 1'b1 : 1'b0 ;

endmodule

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 SEQUENTIAL LOGIC – FSM CIRCUIT

Question :- This is a Moore state machine with two states, one input, and one output.
Implement this state machine. Notice that the reset state is B.

module top_module(clk, reset, in, out);

input clk;
input reset; // Synchronous reset to state B
input in;
output out;//

// Fill in state name declarations

parameter A = 0, B = 1;
reg present_state, next_state;

always @(posedge clk) begin

if (reset) present_state <= B;
else present_state <= next_state;
end

always @(*) begin

case (present_state)
B : next_state <= (in == 1) ? B : A;
A : next_state <= (in == 1) ? A : B;
endcase
end

assign out = (present_state == B);

endmodule

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 SEQUENTIAL LOGIC – FSM CIRCUIT

This is a Moore state machine with two states, two inputs, and one output.
Implement this state machine.

module top_module(
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out); //

parameter OFF=0, ON=1;

reg state, next_state;

always @(*) begin

// State transition logic
case(state)
OFF : next_state <= j ? ON : OFF ;
ON : next_state <= k ? OFF : ON ;
endcase
end

always @(posedge clk, posedge areset) begin

// State flip-flops with asynchronous reset
if(areset)
state <= OFF;
else
state <= next_state;
end

// Output logic
assign out = (state == ON);

endmodule

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 SEQUENTIAL LOGIC – FSM CIRCUIT

This is a Moore state machine with two states, two inputs, and one output. Implement this
state machine.

module top_module(
input clk,
input reset, // Synchronous reset to OFF
input j,input k, output out);

parameter OFF=0, ON=1;

reg state, next_state;

always @(*) begin

// State transition logic
case(state)
OFF : next_state <= j ? ON : OFF ;
ON : next_state <= k ? OFF : ON ;
endcase
end

always @(posedge clk) begin

// State flip-flops with asynchronous reset
if(reset)
state <= OFF;
else
state <= next_state;
end
// Output logic
assign out = (state == ON);
endmodule

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 SEQUENTIAL LOGIC – FSM CIRCUIT

Question :- The following is the state transition table for a Moore state machine with one
input, one output, and four states. Use the following state encoding: A=2'b00, B=2'b01,
C=2'b10, D=2'b11.
Implement only the state transition logic and output logic (the combinational logic portion)
for this state machine. Given the current state (state), compute the next_state and output
(out) based on the state transition table.
Next state
State Output
in=0 in=1

A A B 0

B C B 0

C A D 0

D C B 1

module top_module(
input in,input rst,clk, input [1:0] state,
output [1:0] next_state,output out);

parameter A=0, B=1, C=2, D=3;

always@(posedge clk)
begin
if(rst)
state <= A;
else
state <= next_state;
end

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 SEQUENTIAL LOGIC – FSM CIRCUIT

// State transition logic: next_state = f(state, in)

always @(*) begin
case(state)
A : next_state = (in == 1) ? B : A;
B : next_state = (in == 1) ? B : C;
C : next_state = (in == 1) ? D : A;
D : next_state = (in == 1) ? B : C;
endcase
end

// Output logic: out = f(state) for a Moore state machine

assign out = (state == D);
endmodule

Question :- The following is the state transition table for a Moore state machine with one
input, one output, and four states. Use the following one-hot state encoding: A=4'b0001,
B=4'b0010, C=4'b0100, D=4'b1000.
Derive state transition and output logic equations by inspection assuming a one-hot
encoding. Implement only the state transition logic and output logic (the combinational
logic portion) for this state machine. (The testbench will test with non-one hot inputs to
make sure you're not trying to do something more complicated).

Next state
State Output
in=0 in=1

A A B 0

B C B 0

C A D 0

D C B 1

module top_module(
input in,
input [3:0] state,
output [3:0] next_state,
output out); //

parameter A=0, B=1, C=2, D=3;

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 SEQUENTIAL LOGIC – FSM CIRCUIT

// State transition logic: Derive an equation for each

state flip-flop.
assign next_state[A] = (state[A] & ~in) | (state[C] &
~in);
assign next_state[B] = (state[A] & in) | (state[B] & in)
| (state[D] & in);
assign next_state[C] = (state[B] & ~in) | (state[D] &
~in);
assign next_state[D] = state[C] & in;

// Output logic:
assign out = (state[D]);

endmodule

Question :- The following is the state transition table for a Moore state machine with one
input, one output, and four states. Implement this state machine. Include an asynchronous
reset that resets the FSM to state A.
Next state
State Output
in=0 in=1

A A B 0

B C B 0

C A D 0

D C B 1

module top_module(
input clk, input in,input areset,
output out);

reg [1:0] state , next_state;

parameter A=0,B=1,C=2,D=3;

// State transition logic

always@*
begin
case(state)
A : next_state <= in ? B : A;
B : next_state <= in ? B : C;

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 SEQUENTIAL LOGIC – FSM CIRCUIT

C : next_state <= in ? D : A;
D : next_state <= in ? B : C;
endcase
end
// State flip-flops with asynchronous reset
always@(posedge clk ,posedge areset)
begin
if(areset)
state <= A;
else
state <= next_state ;
end
// Output logic
assign out = (state ==D) ;
endmodule

Question :- The following is the state transition table for a Moore state machine with one
input, one output, and four states. Implement this state machine. Include a synchronous
reset that resets the FSM to state A. (This is the sameas previous problem but with a
synchronous reset.)
module top_module(
input clk,in,reset,
output out); //

reg [1:0] state , next_state;

parameter A=0,B=1,C=2,D=3;
// State transition logic
always@*
begin
case(state)
A : next_state <= in ? B : A;

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 SEQUENTIAL LOGIC – FSM CIRCUIT

B : next_state <= in ? B : C;
C : next_state <= in ? D : A;
D : next_state <= in ? B : C;
endcase
end
// State flip-flops with asynchronous reset
always@(posedge clk)
begin
if(reset)
state <= A;
else
state <= next_state ;
end

// Output logic
assign out = (state ==D) ;

endmodule

Also include an active-high synchronous reset that resets the state machine to a state
equivalent to if the water level had been low for a long time (no sensors asserted, and all
four outputs asserted).
module top_module (
input clk, input reset,input [3:1] s,
output fr3, fr2,fr1,dfr );
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 SEQUENTIAL LOGIC – FSM CIRCUIT

localparam [2:0]
A = 3'd0, //water level:below s1

B0 = 3'd1, //s1~s2, and previous level is higher

B1 = 3'd2, //s1~s2, and previous level is lower

C0 = 3'd3, //s2~s3, and previous level is higher

C1 = 3'd4, //s2~s3, and previous level is lower

D = 3'd5; //above s3

reg [2:0] state, next_state;

always @(posedge clk) begin

if(reset) state <= A;
else state <= next_state;
end

always @(*) begin

case(state)
A : next_state = (s[1]) ? B1 : A;
B0 : next_state = (s[2]) ? C1 : ((s[1]) ? B0 :
A);
B1 : next_state = (s[2]) ? C1 : ((s[1]) ? B1 :
A);
C0 : next_state = (s[3]) ? D : ((s[2]) ? C0 :
B0);
C1 : next_state = (s[3]) ? D : ((s[2]) ? C1 :
B0);
D : next_state = (s[3]) ? D : C0;
default : next_state = 3'bxxx;
endcase
end

always @(*) begin

case(state)
A : {fr3, fr2, fr1, dfr} = 4'b1111;
B0 : {fr3, fr2, fr1, dfr} = 4'b0111;
B1 : {fr3, fr2, fr1, dfr} = 4'b0110;
C0 : {fr3, fr2, fr1, dfr} = 4'b0011;
C1 : {fr3, fr2, fr1, dfr} = 4'b0010;
D : {fr3, fr2, fr1, dfr} = 4'b0000;
default : {fr3, fr2, fr1, dfr} = 4'bxxxx;
endcase
end

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 SEQUENTIAL LOGIC – FSM CIRCUIT

endmodule

Question :- The game Lemmings involves critters with fairly simple brains. So simple that we
are going to model it using a finite state machine.

In the Lemmings' 2D world, Lemmings can be in one of two states: walking left or walking
right. It will switch directions if it hits an obstacle. In particular, if a Lemming is bumped on
the left, it will walk right. If it's bumped on the right, it will walk left. If it's bumped on both
sides at the same time, it will still switch directions.
Implement a Moore state machine with two states, two inputs, and one output that models
this behaviour.

module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right); //

always@(posedge clk,posedge areset) begin

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 SEQUENTIAL LOGIC – FSM CIRCUIT

if(areset) begin
walk_left <= 1'b1;
walk_right <= 1'b0 ; end
else begin
if(bump_left && ~bump_right)begin
walk_left <= 1'b0;
walk_right <= 1'b1; end
else if (bump_right && ~bump_left)begin
walk_left <= 1'b1;
walk_right <= 1'b0;end
else if(bump_right && bump_left)begin
walk_right <= ~walk_right ;
walk_left <= ~walk_left; end
else begin
walk_right <= walk_right ;
walk_left <= walk_left; end
end
end
endmodule

Question :- In addition to walking left and right, Lemmings will fall (and presumably go
"aaah!") if the ground disappears underneath them.

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 SEQUENTIAL LOGIC – FSM CIRCUIT

In addition to walking left and right and changing direction when bumped, when ground=0,
the Lemming will fall and say "aaah!". When the ground reappears (ground=1), the Lemming
will resume walking in the same direction as before the fall. Being bumped while falling does
not affect the walking direction, and being bumped in the same cycle as ground disappears
(but not yet falling), or when the ground reappears while still falling, also does not affect the
walking direction.
Build a finite state machine that models this behaviour.

module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah );

parameter [1:0] WL = 2'B00,WR =2'B01,FL = 2'B10,FR =2'B11;

reg[1:0] ps ,ns;

always@(posedge clk , posedge areset) begin

if(areset)
ps <= WL ;
else
ps <= ns;
end

always@* begin
case(ps)
2'b00 : ns <=(~ground)? FL : (( bump_left )? WR : WL );
2'b01 : ns <=(~ground)? FR : (( bump_right )? WL : WR );
2'b10 : ns <=(ground)? WL : FL ;
2'b11 : ns <=(ground)? WR : FR ;
endcase
end

assign walk_left = (ps == WL);

assign walk_right = (ps == WR);

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 SEQUENTIAL LOGIC – FSM CIRCUIT

assign aaah = ((ps== FL) || (ps == FR));

endmodule

Question :- In addition to walking and falling, Lemmings can sometimes be told to do useful
things, like dig (it starts digging when dig=1). A Lemming can dig if it is currently walking on
ground (ground=1 and not falling), and will continue digging until it reaches the other side
(ground=0). At that point, since there is no ground, it will fall (aaah!), then continue walking
in its original direction once it hits ground again. As with falling, being bumped while digging
has no effect, and being told to dig when falling or when there is no ground is ignored.

(In other words, a walking Lemming can fall, dig, or switch directions. If more than one of
these conditions are satisfied, fall has higher precedence than dig, which has higher
precedence than switching directions.)
Extend your finite state machine to model this behaviour.

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 SEQUENTIAL LOGIC – FSM CIRCUIT

module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk
left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);

localparam [2:0] WALK_L = 3'b000,

WALK_R = 3'b001,
FALL_L = 3'b010,
FALL_R = 3'b011,
DIG_L = 3'b100,
DIG_R = 3'b101;

reg [2:0] state, next;

always @(posedge clk or posedge areset) begin

if(areset) state <= WALK_L;
else state <= next;
end

always @(*) begin

case(state)
WALK_L : begin
if(!ground) next = FALL_L;
else begin
if(dig) next = DIG_L;
else begin
if(bump_left) next = WALK_R;

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 SEQUENTIAL LOGIC – FSM CIRCUIT

else next = WALK_L;

end
end
end
WALK_R : begin
if(!ground) next = FALL_R;
else begin
if(dig) next = DIG_R;
else begin
if(bump_right) next = WALK_L;
else next = WALK_R;
end
end
end
FALL_L : next = (ground) ? WALK_L : FALL_L;
FALL_R : next = (ground) ? WALK_R : FALL_R;
DIG_L : next = (ground) ? DIG_L : FALL_L;
DIG_R : next = (ground) ? DIG_R : FALL_R;
endcase
end

assign walk_left = (state == WALK_L);

assign walk_right = (state == WALK_R);
assign aaah = ((state == FALL_L) || (state == FALL_R));
assign digging = ((state == DIG_L) || (state == DIG_R));

endmodule

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 SEQUENTIAL LOGIC – FSM CIRCUIT

Question :- Although Lemmings can walk, fall, and dig, Lemmings aren't invulnerable. If a
Lemming falls for too long then hits the ground, it can splatter. In particular, if a Lemming
falls for more than 20 clock cycles then hits the ground, it will splatter and cease walking,
falling, or digging (all 4 outputs become 0), forever (Or until the FSM gets reset). There is no
upper limit on how far a Lemming can fall before hitting the ground. Lemmings only splatter
when hitting the ground; they do not splatter in mid-air.

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 SEQUENTIAL LOGIC – FSM CIRCUIT

Extend your finite state machine to model this behaviour.

module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk
left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);

localparam [2:0] WALK_L = 3'b000,

WALK_R = 3'b001,
FALL_L = 3'b010,
FALL_R = 3'b011,
DIG_L = 3'b100,
DIG_R = 3'b101,
SPLATTER = 3'b110;

reg [2:0] state, next;

reg [6:0] count;

always @(posedge clk or posedge areset) begin

if(areset) state <= WALK_L;
else if(state == FALL_R || state == FALL_L) begin

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 SEQUENTIAL LOGIC – FSM CIRCUIT

count <= count + 1;

state <= next;
end
else begin
state <= next;
count <= 0;
end
end

always @(*) begin

case(state)
WALK_L : begin
if(!ground) next = FALL_L;
else begin
if(dig) next = DIG_L;
else begin
if(bump_left) next = WALK_R;
else next = WALK_L;
end
end
end
WALK_R : begin
if(!ground) next = FALL_R;
else begin
if(dig) next = DIG_R;
else begin
if(bump_right) next = WALK_L;
else next = WALK_R;
end
end
end
FALL_L : begin
if(ground) begin
if(count > 19) next = SPLATTER;
else next = WALK_L;
end
else next = FALL_L;
end
FALL_R : begin
if(ground) begin
if(count > 19) next = SPLATTER;
else next = WALK_R;
end
else next = FALL_R;
end
DIG_L : next = (ground) ? DIG_L : FALL_L;
DIG_R : next = (ground) ? DIG_R : FALL_R;
SPLATTER : next = SPLATTER;
endcase
end
assign walk_left = (state == WALK_L);
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 SEQUENTIAL LOGIC – FSM CIRCUIT

assign walk_right = (state == WALK_R);

assign aaah = ((state == FALL_L) || (state == FALL_R));
assign digging = ((state == DIG_L) || (state == DIG_R));
endmodule

Question :- Given the following state machine with 1 input and 2 outputs:

Suppose this state machine uses one-hot encoding,

where state[0] through state[9] correspond to the states S0 though S9, respectively. The
outputs are zero unless otherwise specified.
Implement the state transition logic and output logic portions of the state machine (but not
the state flip-flops). You are given the current state in state[9:0] and must
produce next_state[9:0] and the two outputs. Derive the logic equations by inspection
assuming a one-hot encoding. (The testbench will test with non-one hot inputs to make sure
you're not trying to do something more complicated).

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 SEQUENTIAL LOGIC – FSM CIRCUIT

module top_module(
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2 );

localparam S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4,
S5 = 5, S6 = 6, S7 = 7, S8 = 8, S9 = 9;

//states
assign next_state[S0] = (state[S0] & !in) | (state[S1] &
!in) | (state[S2] & !in) | (state[S3] & !in) |
(state[S4] & !in) | (state[S7] &
!in) | (state[S8] & !in) | (state[S9] & !in);
assign next_state[S1] = (state[S0] & in) | (state[S8] &
in) | (state[S9] & in);
assign next_state[S2] = state[S1] & in;
assign next_state[S3] = state[S2] & in;
assign next_state[S4] = state[S3] & in;
assign next_state[S5] = state[S4] & in;
assign next_state[S6] = state[S5] & in;
assign next_state[S7] = (state[S6] & in) | (state[7] &
in);
assign next_state[S8] = state[S5] & !in;
assign next_state[S9] = state[S6] & !in;

//output
assign out1 = state[8] | state[9];
assign out2 = state[7] | state[9];

endmodule

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 SEQUENTIAL LOGIC – FSM CIRCUIT

Question :- The PS/2 mouse protocol sends messages that are three bytes long. However,
within a continuous byte stream, it's not obvious where messages start and end. The only
indication is that the first byte of each three byte message always has bit[3]=1 (but bit[3] of
the other two bytes may be 1 or 0 depending on data).
We want a finite state machine that will search for message boundaries when given an input
byte stream. The algorithm we'll use is to discard bytes until we see one with bit[3]=1. We
then assume that this is byte 1 of a message, and signal the receipt of a message once all 3
bytes have been received (done).
The FSM should signal done in the cycle immediately after the third byte of each message
was successfully received.

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 SEQUENTIAL LOGIC – FSM CIRCUIT

module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done );

localparam [1:0] BYTE1 = 2'b00,

BYTE2 = 2'b01,
BYTE3 = 2'b10,
DONE = 2'b11;

reg [1:0] state, next;

// State transition logic (combinational)

always @(*) begin
case(state)
BYTE1 : next = (in[3]) ? BYTE2 : BYTE1;
BYTE2 : next = BYTE3;
BYTE3 : next = DONE;
DONE : next = (in[3]) ? BYTE2 : BYTE1;
endcase
end

// State flip-flops (sequential)

always @(posedge clk) begin
if(reset)
state <= BYTE1;
else
state <= next;
end

// Output logic
assign done = (state == DONE);

endmodule

Question :- Now that you have a state machine that will identify three-byte messages in a
PS/2 byte stream, add a datapath that will also output the 24-bit (3 byte) message
whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the
second byte, etc.).out_bytes needs to be valid whenever the done signal is asserted. You
may output anything at other times (i.e., don't-care).
For example:

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 SEQUENTIAL LOGIC – FSM CIRCUIT

module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done); //

localparam [1:0] BYTE1 = 2'b00,

BYTE2 = 2'b01,
BYTE3 = 2'b10,
DONE = 2'b11;

reg [1:0] state, next;

reg [23:0] data;

// State transition logic (combinational)

always @(*) begin
case(state)
BYTE1 : next = (in[3]) ? BYTE2 : BYTE1;
BYTE2 : next = BYTE3;
BYTE3 : next = DONE;
DONE : next = (in[3]) ? BYTE2 : BYTE1;
endcase
end

// State flip-flops (sequential)

always @(posedge clk) begin
if(reset) state <= BYTE1;
else state <= next;
end

// New: Datapath to store incoming bytes.

always @(posedge clk) begin
if (reset) data <= 24'b0;
else data <= {data[15:8], data[7:0], in};
end

// Output logic
assign done = (state == DONE);
assign out_bytes = (done) ? data : 23'b0;

endmodule

Question :- In many (older) serial communications protocols, each data byte is sent along
with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One
common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at
logic 1 when nothing is being transmitted (idle).
Design a finite state machine that will identify when bytes have been correctly received
when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then

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 SEQUENTIAL LOGIC – FSM CIRCUIT

verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM
must wait until it finds a stop bit before attempting to receive the next byte.

Some timing diagrams

module top_module(
input clk,
input in,
input reset, // Synchronous reset
output done );

localparam [2:0] IDLE = 3'b000,

START = 3'b001,
RECEIVE = 3'b010,
WAIT = 3'b011,
STOP = 3'b100;

reg [2:0] state, next;

reg [3:0] i;

always @(*) begin

case(state)
IDLE : next = (in) ? IDLE : START;
START : next = RECEIVE;
RECEIVE : begin
if (i == 8) begin
if (in) next = STOP;
else next = WAIT;
end
else next = RECEIVE;
end
WAIT : next = (in) ? IDLE : WAIT;
STOP : next = (in) ? IDLE : START;
endcase
end

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 SEQUENTIAL LOGIC – FSM CIRCUIT

always @(posedge clk) begin

if(reset) state <= IDLE;
else state <= next;
end

always @(posedge clk) begin

if (reset) begin
done <= 0;
i <= 0;
end
else begin
case(next)
RECEIVE : begin
done <= 0;
i = i + 1;
end
STOP : begin
done <= 1;
i <= 0;
end
default : begin
done <= 0;
i <= 0;
end
endcase
end
end
endmodule

Question :- Now that you have a finite state machine that can identify when bytes are
correctly received in a serial bitstream, add a datapath that will output the correctly-
received data byte. out_byte needs to be valid when done is 1, and is don't-care otherwise.
Note that the serial protocol sends the least significant bit first.

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done );

// Use FSM from Fsm_serial

localparam [2:0] IDLE = 3'b000,
START = 3'b001,
RECEIVE = 3'b010,
WAIT = 3'b011,
STOP = 3'b100;

reg [2:0] state, next;

reg [3:0] i;
reg [7:0] out;

always @(*) begin

case(state)
IDLE : next = (in) ? IDLE : START;
START : next = RECEIVE;
RECEIVE : begin
if (i == 8) begin
if (in) next = STOP;
else next = WAIT;
end
else next = RECEIVE;
end
WAIT : next = (in) ? IDLE : WAIT;
STOP : next = (in) ? IDLE : START;
endcase
end

always @(posedge clk) begin

if(reset) state <= IDLE;
else state <= next;
end

always @(posedge clk) begin

if (reset) begin
done <= 0;
i <= 0;
end
else begin
case(next)
RECEIVE : begin
done <= 0;
i = i + 4'h1;
end
STOP : begin
VERILOG CHANCHAL TIWARI
 SEQUENTIAL LOGIC – FSM CIRCUIT

done <= 1;
i <= 0;
end
default : begin
done <= 0;
i <= 0;
end
endcase
end
end

// New: Datapath to latch input bits.

always @(posedge clk) begin
if (reset) out <= 0;
else if (next == RECEIVE)
out[i] <= in;
end

assign out_byte = (done) ? out : 8'b0;

endmodule

Question :- We want to add parity checking to the serial receiver. Parity checking adds one
extra bit after each data byte. We will use odd parity, where the number of 1s in the 9 bits
received must be odd. For example, 101001011 satisfies odd parity (there are 5 1s),
but 001001011 does not.
Change your FSM and datapath to perform odd parity checking. Assert the done signal only
if a byte is correctly received and its parity check passes. Like the serial receiver FSM, this
FSM needs to identify the start bit, wait for all 9 (data and parity) bits, then verify that the
stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until
it finds a stop bit before attempting to receive the next byte.
You are provided with the following module that can be used to calculate the parity of the
input stream (It's a TFF with reset). The intended use is that it should be given the input bit
stream, and reset at appropriate times so it counts the number of 1 bits in each byte.
module parity (
input clk,
input reset,
input in,
output reg odd);

always @(posedge clk)

if (reset) odd <= 0;
else if (in) odd <= ~odd;

endmodule

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

Note that the serial protocol sends the least significant bit first, and the parity bit after the 8
data bits.

module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
);

// Use FSM from Fsm_serial

localparam [2:0] IDLE = 3'b000,
START = 3'b001,
RECEIVE = 3'b010,
WAIT = 3'b011,
STOP = 3'b100,
CHECK = 3'b101;

reg [2:0] state, next;

reg [3:0] i;
reg [7:0] out;
reg odd_reset;
reg odd_reg;
wire odd;

always @(*) begin

case(state)
IDLE : next = (in) ? IDLE : START;
START : next = RECEIVE;
RECEIVE : next = (i == 8) ? CHECK : RECEIVE;
CHECK : next = (in) ? STOP : WAIT;
WAIT : next = (in) ? IDLE : WAIT;
STOP : next = (in) ? IDLE : START;
endcase
end

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

always @(posedge clk) begin

if(reset) state <= IDLE;
else state <= next;
end

always @(posedge clk) begin

if (reset) begin
i <= 0;
end
else begin
case(next)
RECEIVE : begin
i = i + 4'h1;
end
STOP : begin
i <= 0;
end
default : begin
i <= 0;
end
endcase
end
end

// New: Datapath to latch input bits.

always @(posedge clk) begin
if (reset) out <= 0;
else if (next == RECEIVE)
out[i] <= in;
end

// New: Add parity checking.

parity u_parity(.clk(clk),.reset(reset | odd_reset),
.in(in),.odd(odd));

always @(posedge clk) begin

if(reset) odd_reg <= 0;
else odd_reg <= odd;
end
always @(posedge clk) begin
case(next)
IDLE : odd_reset <= 1;
STOP : odd_reset <= 1;
default : odd_reset <= 0;
endcase
end

assign done = ((state == STOP) && odd_reg);

assign out_byte = (done) ? out : 8'b0;
endmodule
VERILOG CHANCHAL TIWARI
 SEQUENTIAL LOGIC – FSM CIRCUIT

Question :- Synchronous HDLC framing involves decoding a continuous bit stream of data to
look for bit patterns that indicate the beginning and end of frames (packets). Seeing exactly
6 consecutive 1s (i.e., 01111110) is a "flag" that indicate frame boundaries. To avoid the
data stream from accidentally containing "flags", the sender inserts a zero after every 5
consecutive 1s which the receiver must detect and discard. We also need to signal an error
if there are 7 or more consecutive 1s.
Create a finite state machine to recognize these three sequences:
• 0111110: Signal a bit needs to be discarded (disc).
• 01111110: Flag the beginning/end of a frame (flag).
• 01111111...: Error (7 or more 1s) (err).

When the FSM is reset, it should be in a state that behaves as though the previous input
were 0.
Here are some example sequences that illustrate the desired operation.

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

module top_module(
input clk,
input reset, // Synchronous reset
input in,
output disc,
output flag,
output err );

localparam [3:0] NONE = 0,

ONE = 1,
TWO = 2,
THREE= 3,
FOUR = 4,
FIVE = 5,
SIX = 6,
DISC = 7,
FLAG = 8,
ERR = 9;

reg [3:0] state, next;

always @(*) begin

case (state)
NONE : next = (in) ? ONE : NONE;
ONE : next = (in) ? TWO : NONE;
TWO : next = (in) ? THREE : NONE;
THREE: next = (in) ? FOUR : NONE;
FOUR : next = (in) ? FIVE : NONE;
FIVE : next = (in) ? SIX : DISC;
SIX : next = (in) ? ERR : FLAG;
DISC : next = (in) ? ONE : NONE;
FLAG : next = (in) ? ONE : NONE;
ERR : next = (in) ? ERR : NONE;
endcase
end

always @(posedge clk) begin

if (reset)

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

state <= NONE;

else
state <= next;
end

assign disc = (state == DISC);

assign flag = (state == FLAG);
assign err = (state == ERR);

endmodule

Question :- Implement a Mealy-type finite state machine that recognizes the sequence
"101" on an input signal named x. Your FSM should have an output signal, z, that is asserted
to logic-1 when the "101" sequence is detected. Your FSM should also have an active-low
asynchronous reset. You may only have 3 states in your state machine. Your FSM should
recognize overlapping sequences.
module top_module (
input clk,
input aresetn, // Asynchronous active-low reset
input x,
output z );

localparam [1:0] IDLE = 0,

ONE = 1,
ONE_ZERO = 2;

reg [1:0] state, next;

always @(*) begin

case (state)
IDLE : begin
next = (x) ? ONE : IDLE;
z = 0;
end
ONE : begin
next = (x) ? ONE : ONE_ZERO;
z = 0;
end
ONE_ZERO : begin
if (x) begin
next = ONE;
z = 1;
end
else begin
next = IDLE;
z = 0;
end
end

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

endcase
end

always @(posedge clk or negedge aresetn) begin

if (~aresetn) state <= IDLE;
else state <= next;
end

endmodule

Question :- You are to design a one-input one-output serial 2's

complementer Moore state machine. The input (x) is a series of bits (one per clock
cycle) beginning with the least-significant bit of the number, and the output (Z) is the
2's complement of the input. The machine will accept input numbers of arbitrary
length. The circuit requires an asynchronous reset. The conversion begins
when Reset is released and stops when Reset is asserted.
For example:

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

module top_module (
input clk, input areset, input x,
output z);

parameter A=2'b00, B=2'b01, C=2'b10;

reg [1:0] state, state_next;

always @(posedge clk or posedge areset)

begin
if (areset)
state <= A;
else
state <= state_next;
end

always @(*)
begin
case (state)
A: begin
if (x) state_next <= B;
else state_next <= A;
end
B: begin
if (x) state_next <= C;
else state_next <= B;
end
C: begin
if (x) state_next <= C;
else state_next <= B;
end
default: state_next <= A;
endcase
end
assign z = (state == B);
endmodule

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

Question :-he following diagram is a Mealy machine implementation of the 2's

complementor. Implement using one-hot encoding.

module top_module (
input clk,input areset,input x,
output z );

localparam [1:0] A = 2'b01,

B = 2'b10;

reg [1:0] state, next;

always @(*) begin

case (state)
A : begin
if (x) begin
next = B;
z =1;
end
else begin

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

next = A;
z = 0;
end
end
B : begin
next = B;
z = (x) ? 1'b0 : 1'b1;
end
endcase
end

always @(posedge clk or posedge areset) begin

if (areset) state <= A;
else state <= next;
end
endmodule

Question :- Consider a finite state machine with inputs s and w. Assume that the
FSM begins in a reset state called A, as depicted below. The FSM remains in
state A as long as s = 0, and it moves to state B when s = 1. Once in state B the FSM
examines the value of the input w in the next three clock cycles. If w = 1 in exactly
two of these clock cycles, then the FSM has to set an output z to 1 in the following
clock cycle. Otherwise z has to be 0. The FSM continues checking w for the next
three clock cycles, and so on. The timing diagram below illustrates the required
values of z for different values of w.

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

Use as few states as possible. Note that the s input is used only in state A, so you
need to consider just the w input.

module top_module (
input clk,
input areset,
input x,
output z
);

localparam [1:0] A = 2'b01,

B = 2'b10;

reg [1:0] state, next;

always @(*) begin

case (state)
A : begin
if (x) begin
next = B;
z =1;
end
else begin
next = A;
z = 0;
end
end
B : begin

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

next = B;
z = (x) ? 1'b0 : 1'b1;
end
endcase
end

always @(posedge clk or posedge areset) begin

if (areset) state <= A;
else state <= next;
end
endmodule
//////////////////////////////////
module top_module (
input clk, input reset, // Synchronous reset
input s, input w,
output z);

parameter A = 0, B = 1;

reg state, next;

reg [1:0] count;
reg [1:0] count1;

always @(*) begin

case(state)
A : next = (s) ? B : A;
B : next = B;
endcase
end

always @(posedge clk) begin

if (reset) begin
state <= A;
count=0;
count1=0;
end
else begin
state <= next;

if(state==B)
begin
if(count1==3)begin
count=0;
count1=0;
end
if(w==1) count=count+1;

count1=count1+1;

end
end
VERILOG CHANCHAL TIWARI
 SEQUENTIAL LOGIC – FSM CIRCUIT

end

assign z = ((count == 2) & (count1 == 3) );

endmodule

Question :- Given the state-assigned table shown below, implement the finite-state
machine. Reset should reset the FSM to state 000.

Present state Next state Y[2:0]

Output z
y[2:0] x=0 x=1

000 000 001 0

001 001 100 0

010 010 001 0

011 001 010 1

100 011 100 1

module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);

parameter a = 0, b = 1, c = 2, d = 3, e = 4;
reg [2:0] state, next_state;

always @(*) begin

case (state)
a: next_state = x ? b : a;
b: next_state = x ? e : b;
c: next_state = x ? b : c;
d: next_state = x ? c : b;
e: next_state = x ? e : d;
endcase
end

always @(posedge clk) begin

if (reset) begin
state <= a;
end
else begin

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

state <= next_state;

end
end

assign z = (state == d || state == e);

endmodule
Question :- Given the state-assigned table shown below, implement the logic functions Y[0]
and z.

Present state Next state Y[2:0]

Output z
y[2:0] x=0 x=1

000 000 001 0

001 001 100 0

010 010 001 0

011 001 010 1

100 011 100 1

module top_module (
input clk,
input [2:0] y,
input x,
output Y0,
output z
);

reg [2:0] Y;

always@(*) begin
case({y, x})
4'b0000: Y = 3'b000;
4'b0001: Y = 3'b001;
4'b0010: Y = 3'b001;
4'b0011: Y = 3'b100;
4'b0100: Y = 3'b010;
4'b0101: Y = 3'b001;
4'b0110: Y = 3'b001;
4'b0111: Y = 3'b010;
4'b1000: Y = 3'b011;
4'b1001: Y = 3'b100;
endcase
end

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

assign z = (y == 3'b011 || y == 3'b100);

assign Y0 = Y[0];

endmodule
Question :- Consider the state machine shown below, which has one input w and one
output z.

Implement the state machine. (This part wasn't on the midterm, but coding up FSMs is good
practice).

module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);

parameter a=3'b000, b=3'b001, c=3'b010, d=3'b011,

e=3'b100, f=3'b101;
reg [2:0] state, next_state;

always@(*) begin
case({state, w})
{a, 1'b0}: next_state = b;
{a, 1'b1}: next_state = a;
{b, 1'b0}: next_state = c;
{b, 1'b1}: next_state = d;
{c, 1'b0}: next_state = e;
{c, 1'b1}: next_state = d;
{d, 1'b0}: next_state = f;

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

{d, 1'b1}: next_state = a;

{e, 1'b0}: next_state = e;
{e, 1'b1}: next_state = d;
{f, 1'b0}: next_state = c;
{f, 1'b1}: next_state = d;
default : next_state = a;
endcase
end

always@(posedge clk) begin

if(reset)
state <= a;
else
state <= next_state;
end

assign z = (state == e || state == f);

endmodule

Question :- Consider the state machine shown below, which has one input w and one
output z.

Assume that you wish to implement the FSM using three flip-flops and state codes y[3:1]
= 000, 001, ... , 101 for states A, B, ... , F, respectively. Show a state-assigned table for this
FSM. Derive a next-state expression for the flip-flop y[2].
Implement just the next-state logic for y[2]. (This is much more a FSM question than a
Verilog coding question. Oh well.)
module top_module (

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

input [3:1] y,
input w,
output Y2
);

reg [3:1] Y;

always @(*) begin

case({y, w})
4'b0000: Y = 3'b001;
4'b0001: Y = 3'b000;
4'b0010: Y = 3'b010;
4'b0011: Y = 3'b011;
4'b0100: Y = 3'b100;
4'b0101: Y = 3'b011;
4'b0110: Y = 3'b101;
4'b0111: Y = 3'b000;
4'b1000: Y = 3'b100;
4'b1001: Y = 3'b011;
4'b1010: Y = 3'b010;
4'b1011: Y = 3'b011;
endcase
end

assign Y2 = Y[2];
endmodule
Question :- Consider the state machine shown below, which has one input w and one
output z.
For this part, assume that a one-hot code is used with the state assignment 'y[6:1] =
000001, 000010, 000100, 001000, 010000, 100000 for states A, B,..., F, respectively.
Write a logic expression for the next-state signals Y2 and Y4. (Derive the logic
equations by inspection assuming a one-hot encoding. The testbench will test with
non-one hot inputs to make sure you're not trying to do something more
complicated).

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);

assign Y2 = y[1] & (~w);

assign Y4 = (y[2] & w) | (y[3] & w) | (y[5] & w) | (y[6]
& w);

endmodule

Question :- Consider the state diagram shown below.

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

Write complete Verilog code that represents this FSM. Use separate always blocks for the
state table and the state flip-flops, as done in lectures. Describe the FSM output, which is
called z, using either continuous assignment statement(s) or an always block (at your
discretion). Assign any state codes that you wish to use.

module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);

parameter a=3'b000, b=3'b001, c=3'b010, d=3'b011,

e=3'b100, f=3'b101;
reg [2:0] state, next_state;

always@(*) begin
case({state, w})
{a, 1'b0}: next_state = a;
{a, 1'b1}: next_state = b;
{b, 1'b0}: next_state = d;
{b, 1'b1}: next_state = c;
{c, 1'b0}: next_state = d;
{c, 1'b1}: next_state = e;
{d, 1'b0}: next_state = a;
{d, 1'b1}: next_state = f;
{e, 1'b0}: next_state = d;
{e, 1'b1}: next_state = e;
{f, 1'b0}: next_state = d;
{f, 1'b1}: next_state = c;

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

default : next_state = a;
endcase
end

always@(posedge clk) begin

if(reset)
state <= a;
else
state <= next_state;
end

assign z = (state == e || state == f);

endmodule

Quesstion:- The state diagram for this question is shown again below.

Assume that a one-hot code is used with the state assignment y[5:0] = 000001(A),
000010(B), 000100(C), 001000(D), 010000(E), 100000(F)
Write a logic expression for the signal Y1, which is the input of state flip-flop y[1].
Write a logic expression for the signal Y3, which is the input of state flip-flop y[3].
(Derive the logic equations by inspection assuming a one-hot encoding. The testbench will
test with non-one hot inputs to make sure you're not trying to do something more
complicated).

module top_module (

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

input [5:0] y,
input w,
output Y1,
output Y3 );

assign Y1 = y[0] & w;

assign Y3 = (y[1] & (~w)) | (y[2] & (~w)) | (y[4] & (~w))
| (y[5] & (~w));

endmodule
Question :- Consider the FSM described by the state diagram shown below:

This FSM acts as an arbiter circuit, which controls access to some type of resource by three
requesting devices. Each device makes its request for the resource by setting a signal r[i] = 1,
where r[i] is either r[1], r[2], or r[3]. Each r[i] is an input signal to the FSM, and represents
one of the three devices. The FSM stays in state A as long as there are no requests. When
one or more request occurs, then the FSM decides which device receives a grant to use the
resource and changes to a state that sets that device’s g[i] signal to 1. Each g[i] is an output
from the FSM. There is a priority system, in that device 1 has a higher priority than device 2,
and device 3 has the lowest priority. Hence, for example, device 3 will only receive a grant if

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

it is the only device making a request when the FSM is in state A. Once a device, i, is given a
grant by the FSM, that device continues to receive the grant as long as its request, r[i] = 1.
Write complete Verilog code that represents this FSM. Use separate always blocks for the
state table and the state flip-flops, as done in lectures. Describe the FSM outputs, g[i], using
either continuous assignment statement(s) or an always block (at your discretion). Assign
any state codes that you wish to use.
module top_module (
input clk,
input resetn, // active-low synchronous reset
input [3:1] r, // request
output [3:1] g // grant
);

parameter a=2'd0, b=2'd1, c=2'd2, d=2'd3;

reg [1:0] state, next_state;

always@(*) begin
case(state)
a: begin
if(r[1]) next_state = b;
else if(~r[1] & r[2]) next_state = c;
else if(~r[1] & ~r[2] & r[3])next_state = d;
else next_state = a;
end
b: begin
if(r[1]) next_state = b;
else next_state = a;
end
c: begin
if(r[2]) next_state = c;
else next_state = a;
end
d: begin
if(r[3]) next_state = d;
else next_state = a;
end
endcase
end
always@(posedge clk) begin
if(~resetn)
state <= a;
else
state <= next_state;
end

assign g[1] = (state == b);

assign g[2] = (state == c);
assign g[3] = (state == d);

VERILOG CHANCHAL TIWARI

 SEQUENTIAL LOGIC – FSM CIRCUIT

endmodule

Question:- Consider a finite state machine that is used to control some type of motor. The
FSM has inputs x and y, which come from the motor, and produces outputs f and g, which
control the motor. There is also a clock input called clk and a reset input called resetn.
The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a
beginning state, called state A. When the reset signal is de-asserted, then after the next
clock edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to
monitor the x input. When x has produced the values 1, 0, 1 in three successive clock cycles,
then g should be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has
to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM
should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within
two clock cycles, then the FSM should set g = 0 permanently (until reset).
module top_module (
input clk,
input resetn, // active-low synchronous reset
input x,
input y,
output reg f,
output reg g
);

parameter A=4'd0, f1=4'd1, tmp0=4'd2, tmp1=4'd3,

tmp2=4'd4, g1=4'd5, g1p=4'd6, tmp3=4'd7, g0p=4'd8;
reg [3:0] state, next_state;

always@(*) begin
case(state)
A: begin
if(resetn)
next_state = f1;
else
next_state = A;
end
f1: next_state = tmp0;
VERILOG CHANCHAL TIWARI
 SEQUENTIAL LOGIC – FSM CIRCUIT

tmp0: begin
if(x)
next_state = tmp1;
else
next_state = tmp0;
end
tmp1: begin
if(~x)
next_state = tmp2;
else
next_state = tmp1;
end
tmp2: begin
if(x)
next_state = g1;
else
next_state = tmp0;
end
g1: begin
if(y)
next_state = g1p;
else
next_state = tmp3;
end
tmp3: begin
if(y)
next_state = g1p;
else
next_state = g0p;
end
g1p: begin
if(~resetn)
next_state = A;
else
next_state = g1p;
end
g0p: begin
if(~resetn)
next_state = A;
else
next_state = g0p;
end
endcase
end

always@(posedge clk) begin

if(~resetn)
state <= A;
else
state <= next_state;
end
VERILOG CHANCHAL TIWARI
 SEQUENTIAL LOGIC – FSM CIRCUIT

always@(posedge clk) begin

case(next_state)
f1: f <= 1'b1;
g1: g <= 1'b1;
tmp3: g <= 1'b1;
g1p: g <= 1'b1;
g0p: g <= 1'b0;
default: begin
f <= 1'b0;
g <= 1'b0;
end
endcase
end

endmodule

VERILOG CHANCHAL TIWARI