Moore design

module edgeDetector ( // heading always @(stateMoore_reg, level) // combinational logic

input wire clk, reset, begin
input wire level, case(stateMoore_reg)
output reg Moore_tick zeroMoore: if (level)
); stateMoore_next = edgeMoore;
parameter [1:0] // state encoding edgeMoore:
zeroMoore = 2'b00, begin
edgeMoore = 2'b01, Moore_tick = 1'b1;
oneMoore = 2'b10; if (level)
stateMoore_next = oneMoore;
reg [1:0] stateMoore_reg, stateMoore_next; else
stateMoore_next = zeroMoore;
always @(posedge clk, posedge reset) // sequential logic end
begin oneMoore:
if(reset) begin if (~level)
stateMoore_reg <= zeroMoore; stateMoore_next = zeroMoore;
end endcase
else begin end
stateMoore_reg <= stateMoore_next; endmodule
end
end
 Mealy design
module edgeDetector (
input wire clk, reset, always @(stateMealy_reg, level)
input wire level, begin
output reg Mealy_tick // store current state as next
); stateMealy_next = stateMealy_reg; // required: when no case
statement is satisfied
parameter // 2 states are required for Mealy
zeroMealy = 1'b0, Mealy_tick = 1'b0; // set tick to zero (so that 'tick = 1' is available for
oneMealy = 1'b1; 1 cycle only)
case(stateMealy_reg)
reg stateMealy_reg, stateMealy_next; zeroMealy: // set 'tick = 1' if state = zero and level = '1'
if(level)
always @(posedge clk, posedge reset) begin // if level is 1, then go to state one,
begin stateMealy_next = oneMealy; // otherwise remain in same
if(reset) // go to state zero if reset state.
begin Mealy_tick = 1'b1;
stateMealy_reg <= zeroMealy; end
end oneMealy:
else // otherwise update the states if(~level) // if level is 0, then go to zero state,
begin stateMealy_next = zeroMealy; // remain in one state.
stateMealy_reg <= stateMealy_next; endcase
end end
end
General FSM Design Process with Verilog
 Example 4: Simple traffic light using Moore FSM
module traffic_light( // Next state logic (combinational)
input clk, // Clock signal always @(*) begin
input reset, // Reset signal case (state)
RED: next_state = GREEN; // Transition from RED to GREEN
output reg [2:0] light // Traffic light output: Red, Yellow, GREEN: next_state = YELLOW; // Transition from GREEN to YELLOW
Green ); YELLOW: next_state = RED; // Transition from YELLOW to RED
default: next_state = RED; // Default state
// State encoding endcase
localparam RED = 2'b00; // Red light state end
localparam GREEN = 2'b01; // Green light state
localparam YELLOW = 2'b10; // Yellow light state // Output logic
always @(posedge clk or posedge reset) begin
if (reset)
// State and next state registers light <= 3'b100; // Default output for RED light on reset
reg [1:0] state, next_state; else begin
case (state)
// State transition logic (sequential) RED: light <= 3'b100; // Red light ON
always @(posedge clk or posedge reset) begin GREEN: light <= 3'b001; // Green light ON
if (reset) YELLOW: light <= 3'b010; // Yellow light ON
default: light <= 3'b100; // Default to RED
state <= RED; // Reset to the RED light state endcase
else end
state <= next_state; // Update state at each clock cycle end
end endmodule
module traffic_light( // Next State Logic (Combinational)
input clk, // Clock signal always @(*) begin
input reset, // Reset signal case (state)
output reg [2:0] light // Traffic light output: Red, Yellow, Green RED: next_state = GREEN; // Transition from RED to GREEN
); GREEN: next_state = YELLOW; // Transition from GREEN to YELLOW
YELLOW: next_state = RED; // Transition from YELLOW to RED
// One-Hot State Encoding default: next_state = RED; // Default state
localparam RED = 3'b100; // Red light state endcase
localparam GREEN = 3'b010; // Green light state end
localparam YELLOW = 3'b001; // Yellow light state
// Output Logic (Moore Output Based on State)
// State and Next State Registers always @(posedge clk or posedge reset) begin
reg [2:0] state, next_state; if (reset)
light <= RED; // Default output for RED light on reset
// State Transition Logic (Sequential) else
always @(posedge clk or posedge reset) begin light <= state; // State directly drives output
if (reset) end
state <= RED; // Reset to the RED light state
else endmodule
state <= next_state; // Update state at each clock cycle
end