ELECTONICS C CYCLE
ELECTONICS C CYCLE
Complex and
Generation Performance
Requirements
Deterministic
Triggering
Behaviour
Embedded Systems Vs
General Computing
Systems
General Computing System Embedded Systems
combination of generic hardware and General combination of special purpose hardware and
Purpose Operating System embedded OS for executing a specific set of
applications
Contain a General Purpose Operating System (GPOS) May or may not contain an operating system for
functioning
Applications are alterable (programmable) by user The firmware of the embedded system is pre-
programmed and it is non-alterable by end-user
Performance is the key deciding factor on the Application specific requirements (like performance,
selection of the system. Always ‘Faster is Better’ power requirements, memory usage etc) are the key
deciding factors
Embedded Systems Vs
General Computing
Systems
General Computing System Embedded Systems
Less/not at all tailored towards reduced operating Highly tailored to take advantage of the power saving
power requirements, options for different levels of modes supported by hardware and Operating System
power management.
Response requirements are not time critical For certain category of embedded systems like
mission critical systems, the response time
requirement is highly critical
Need not be deterministic in execution behavior Execution behavior is deterministic for certain type of
embedded systems like ‘Hard Real Time’ systems
Classificatio
n of
Embedded
Systems
Based on Generation
Second Generation
• built around 16 bit microprocessors. 8 bit and 16 bit
microcontrollers. More complex and powerful
Data Acquisition systems, SCADA systems
Classification of
Embedded Systems based
on Generation
Third Generation
• Application and domain specific processors/controllers like
Digital Signal Processors(DSP) and Application Specific
Integrated Circuits(ASICs)
• Instruction set more complex and powerful
• Instruction Pipelining
Fourth Generation
• System on Chip, Reconfigurable processors and multicore
processors
• High performance, tight integration and miniaturization
Classification Based on
Complexity and
Performance
Telecom: Cellular
Computer Networking
Telephones, Telephone Computer Peripherals: Health Care: Different
Systems: Network
switches, Handset Printers, Scanners, Fax Kinds of Scanners, EEG,
Routers, Switches, Hubs,
Multimedia Applications machines etc. ECG Machines etc.
Firewalls etc.
etc.
Memory
Communication Interface
System
I/p Ports Core O/p Ports
(Sensors)
(Actuators)
Other supporting
Integrated Circuits &
subsystems
Embedded System
Real World
General Purpose and Domain Specific
Embedded System Processors
• Microprocessors
• Microcontrollers
• Digital Signal Processors
Microprocessor Microcontroller
• Silicon chip representing a CPU, performs • Highly integrated chip contains CPU, scratch
arithmetic and logical operations pad RAM, on chip ROM/flash memory, I/O
• Dependent Unit ports
• General purpose in design and operation • Self contained unit
• Doesn’t contain I/O port • Application oriented and domain specific
• Limited power saving options compared to • Contains multiple built in I/O ports
microcontrollers • Includes lot of power saving features
Microcontroller
Architectures
Harvard Architecture
Von Neumann Architecture
Harvard vs Von Neumann Architectures
Separate buses for instruction and data Single shared bus for instruction and
fetching data fetching
Easier to pipeline, so high performance Low performance Compared to
Comparatively high cost Harvard Architecture
No memory alignment problems Cheaper
Since data memory and program memory Allows self modifying codes
are stored physically in different Since data memory and program
locations, no chances for accidental memory are stored physically in same
corruption of program memory chip, chances for accidental
corruption of program memory
Lesser no. of instructions Greater no. of
RISC vs Instruction Pipelining and Instructions
CISC increased execution
speed
Generally no instruction
pipelining feature
Processo Orthogonal Instruction
Set
Non Orthogonal
Instruction Set
rs Operations are performed Operations are
on registers only, the only performed on registers
memory operations are or memory depending
load and store on the instruction
Large number of registers Limited no. of general
are available purpose registers
Programmer needs to write Instructions are like
RISC vs more code to execute a task
since the instructions are
macros in C language
simpler ones
CISC Variable length
Instructions
Processo Single, Fixed length
Instructions
More silicon usage since
rs Less Silicon usage and pin
more additional decoder
logic is required to
count implement the complex
instruction decoding
Harvard Architecture
Can be Harvard or Von-
Neumann Architecture
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