LP2980-N

SNOS733Q – APRIL 2000 – REVISED NOVEMBER 2023

LP2980-N Micropower, 50-mA, Ultra-Low-Dropout Regulator in SOT-23 Package

1 Features 3 Description
• VIN range (new chip): 2.5 V to 16 V The LP2980-N is a fixed-output, wide-input, low-
• VOUT range (new chip): dropout (LDO) voltage regulator supporting an input
– 1.2 V to 5.0 V (fixed, 100-mV steps) voltage range from 2.5 V to 16 V and up to 50 mA of
• VOUT accuracy: load current. The LP2980-N supports an output range
– ±0.5% for A-grade legacy chip of 1.2 V to 5.0 V (new chip).
– ±1% for standard-grade legacy chip Additionally, the LP2980-N (new chip) has a 1%
– ±0.5% for new chip (A grade and standard output accuracy across load and temperature that
grade) can meet the needs of low-voltage microcontrollers
• Output accuracy over load, and temperature: ±1% (MCUs) and processors.
(new chip)
• Output current: Up to 50 mA In the new chip, wide bandwidth PSRR performance
• Low IQ (new chip): 69 μA at ILOAD = 0 mA is 75 dB at 1 kHz and 45 dB at 1 MHz to help
• Low IQ (new chip): 380 μA at ILOAD = 50 mA attenuate the switching frequency of an upstream
• Shutdown current over temperature: DC/DC converter and minimize post regulator filtering.
– 0.01 μA (typ) for legacy chip The internal soft-start time and current-limit protection
– 1.12 μA (typ) for new chip reduce inrush current during start up, thus minimizing
• Output current limiting and thermal protection input capacitance. Standard protection features, such
• Stable with 2.2-µF ceramic capacitors (new chip) as overcurrent and overtemperature protection, are
• High PSRR (new chip): included.
– 75 dB at 1 kHz, 45 dB at 1 MHz
The LP2980-N is available in a 5-pin, 2.9-mm × 1.6-
• Operating junction temperature: –40°C to +125°C
mm SOT-23 (DBV) package.
• Package: 5-pin SOT-23 (DBV)
Package Information
2 Applications PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
• Residential breakers LP2980-N DBV (SOT-23, 5) 2.9 mm × 2.8 mm
• Solid state drives (SSD)
• Electricity meters (1) For more information, see the Mechanical, Packaging, and
Orderable Information.
• Appliances (2) The package size (length × width) is a nominal value and
• Building automation includes pins, where applicable.

VIN VOUT 250

1mA 10mA 50mA
IN OUT
200
Dropout (mV)

LP2980-N
150
CIN COUT
ON/ 100
OFF
GND GND 50

GND 0
-75 -50 -25 0 25 50 75 100 125 150
GND Temperature (°C)
Typical Application Circuit Dropout Voltage vs Temperature (New Chip)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7 Application and Implementation.................................. 18
2 Applications..................................................................... 1 7.1 Application Information............................................. 18
3 Description.......................................................................1 7.2 Typical Application.................................................... 20
4 Pin Configuration and Functions...................................2 7.3 Power Supply Recommendations.............................23
5 Specifications.................................................................. 3 7.4 Layout....................................................................... 23
5.1 Absolute Maximum Ratings........................................ 3 8 Device and Documentation Support............................24
5.2 ESD Ratings............................................................... 3 8.1 Device Support......................................................... 24
5.3 Recommended Operating Conditions.........................3 8.2 Device Nomenclature................................................24
5.4 Thermal Information....................................................4 8.3 Receiving Notification of Documentation Updates....24
5.5 Electrical Characteristics.............................................4 8.4 Support Resources................................................... 24
5.6 Typical Characteristics................................................ 7 8.5 Trademarks............................................................... 24
6 Detailed Description......................................................14 8.6 Electrostatic Discharge Caution................................24
6.1 Overview................................................................... 14 8.7 Glossary....................................................................24
6.2 Functional Block Diagram......................................... 14 9 Revision History............................................................ 25
6.3 Feature Description...................................................14 10 Mechanical, Packaging, and Orderable
6.4 Device Functional Modes..........................................17 Information.................................................................... 25

4 Pin Configuration and Functions

VIN 1 5 VOUT

GND 2

ON/OFF 3 4 N/C

Figure 4-1. DBV Package, 5-Pin SOT-23 (Top View)

Table 4-1. Pin Functions

PIN
TYPE DESCRIPTION
NO. NAME
Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See the
1 IN I
Input and Output Capacitor Requirements section for more information.
2 GND — Common ground (device substrate).
Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low
3 ON/OFF I disables the device. High and low thresholds are listed in the Electrical Characteristics table.
Tie this pin to VIN if unused.
4 N/C — Do not connect.
Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to
5 OUT O
ground(1). See the Input and Output Capacitor Requirements section for more information.

(1) The nominal output capacitance must be greater than 1 μF. Throughout this document, the nominal derating on these capacitors is
50%. Make sure that the effective capacitance at the pin is greater than 1 μF.

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
Continuous input voltage range (for legacy chip) –0.3 16 V
VIN
Continuous input voltage range(for new chip) –0.3 18 V
Output voltage range (for legacy chip) –0.3 9 V
VOUT VIN + 0.3 or 9
Output voltage range(for new chip) –0.3 V
(whichever is smaller)
ON/OFF pin voltage range (for legacy chip) –0.3 16 V
VON/OFF
ON/OFF pin voltage range (for new chip) –0.3 18 V
Current Maximum output Internally limited A
Operating junction, TJ –55 150 °C
Temperature
Storage, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltages with respect to GND.

5.2 ESD Ratings

VALUE VALUE
(Legacy (New UNIT
Chip) Chip)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 ±3000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500 ±1000

(1) JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply input voltage (for legacy chip) 2.2 16 V
VIN
Supply input voltage (for new chip) 2.5 16 V
Output voltage (for legacy chip) 1.2 10.0 V
VOUT
Output voltage (for new chip) 1.2 5 V
Enable voltage (for legacy chip) 0 VIN V
VON/OFF
Enable voltage (for new chip) 0 16 V
IOUT Output current 0 50 mA
CIN (1) Input capacitor 1
Output capacitor (for legacy chip) 2.2 4.7 µF
COUT
Output capacitance (for new chip) (1) 1 2.2 200
TJ Operating junction temperature –40 125 °C

(1) All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF
minimum for stability.

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5.4 Thermal Information

Legacy Chip New Chip
THERMAL METRIC (2) (1) DBV (SOT23-5) DBV (SOT23-5) UNIT
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 205.4 178.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 78.8 77.9 °C/W
RθJB Junction-to-board thermal resistance 46.7 47.2 °C/W
ψJT Junction-to-top characterization parameter 8.3 15.9 °C/W
ψJB Junction-to-board characterization parameter 46.3 46.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.
(2) Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be
further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO
thermal performance application report.

5.5 Electrical Characteristics

specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0
µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Legacy chip
(standard −1.0 1.0
grade)
IL = 1mA
Legacy chip
−0.5 0.5
(A grade)
New chip −0.5 0.5
Legacy chip
(standard −1.5 1.5
grade)
∆VOUT Output voltage tolerance 1 mA ≤ IL ≤ 50 mA %
Legacy chip
−0.75 0.75
(A grade)
New chip −0.5 0.5
Legacy chip
(standard −3.5 3.5
grade)
1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
−2.5 2.5
(A grade)
New chip −1.0 1.0
Legacy chip 0.007 0.014
VO(NOM) + 1 V ≤ VIN ≤ 16 V
New chip 0.002 0.014
ΔVOUT(ΔVIN) Line regulation %/V
Legacy chip 0.007 0.032
VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C
New chip 0.002 0.032

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5.5 Electrical Characteristics (continued)

specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0
µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Legacy chip 1 3
IOUT = 0 mA
New chip 1 2.75
Legacy chip 5
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
New chip 3
Legacy chip 7 10
IOUT = 1 mA
New chip 11.5 14
Legacy chip 15
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
New chip 17
VIN - VOUT Dropout voltage(1) mV
Legacy chip 40 60
IOUT = 10 mA
New chip 98 115
Legacy chip 90
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
New chip 148
Legacy chip 120 150
IOUT = 50 mA
New chip 120 145
Legacy chip 225
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
New chip 184
Legacy chip 65 95
IOUT = 0 mA
New chip 69 95
Legacy chip 65 125
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
New chip 120
Legacy chip 75 110
IOUT = 1 mA
New chip 78 110
Legacy chip 170
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
New chip 140
Legacy chip 120 220
IGND GND pin current IOUT = 10 mA uA
New chip 175 210
Legacy chip 400
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
New chip 250
Legacy chip 350 600
IOUT = 50 mA
New chip 380 440
Legacy chip 900
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
New chip 650
Legacy chip 0 1
VON/OFF < 0.18 V, –40°C ≤ TJ ≤ 125°C
New chip 1.12 2.25
VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C 2.2 2.4
VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C New chip 1.9 2.07 V
VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130
Legacy chip 150
IO(SC) Short output current RL = 0 Ω (steady state)
New chip 150
mA
Legacy chip 110 150
IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state)
New chip 110 150

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5.5 Electrical Characteristics (continued)

specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0
µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ Legacy chip 0.55 0.18
≤ 125°C New chip 0.15
VON/OFF ON/OFF input voltage V
High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ Legacy chip 1.6 1.4
125°C New chip 1.6

VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V,–40°C ≤ TJ ≤ Legacy chip 0 -1

125°C New chip -0.9
ION/OFF ON/OFF input current uA
VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ Legacy chip 5 15
125°C New chip 2.20
f = 1 kHz, COUT = 10 µF Legacy chip 63
ΔVO/ΔVIN Ripple rejection f = 1 kHz, COUT = 10 µF New chip 75 dB
f = 100 kHz, ILOAD = 50mA New chip 45
Bandwidth = 300 Hz to 50 kHz, COUT = 10uF, VOUT =
Legacy chip 160
3.3V, ILOAD = 50mA
Bandwidth = 300 Hz to 50 kHz, COUT = 2.2uF, VOUT = µVRM
Vn Output noise voltage New chip 140
3.3V, ILOAD = 50mA S

Bandwidth = 10 Hz to 100 kHz, COUT = 2.2uF, VOUT =

New chip 50
3.3V, ILOAD = 50mA
Tsd+ Thermal shutdown Shutdown, temperature increasing 170
New chip °C
Tsd- threshold Reset, temperature decreasing 150

(1) Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured
with a 1-V differential. VDO is measured with VIN = VOUT(nom) - 100mV for fixed output devices.

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5.6 Typical Characteristics

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, COUT = 2.2 µF for the legacy chip, and COUT = 4.7 µF for the new chip (unless otherwise noted)

3.315

3.31 VIN = 4.3 V

VOUT = 3.3 V
3.305 Iout = 1mA
CO = 4.7uF
3.3

VOUT (V)
3.295

3.29

3.285

3.28
-75 -50 -25 0 25 50 75 100 125 150
Temp C

VIN = 4.3 V, VOUT = 3.3 V

Figure 5-1. Output Voltage vs Temperature (Legacy Chip) Figure 5-2. Output Voltage vs Temperature (New Chip)
4

3.5

2.5
VOUT ( V )

1.5

1
RLOAD
0.5 3.3 k
66 
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VIN ( V )

Figure 5-3. Output Voltage vs VIN (Legacy Chip) Figure 5-4. Output Voltage vs VIN (New Chip)
160 220
IOUT TEMPERATURE
140 1 mA 50 mA IOUT = 50 mA -55 C 25 C 150 C
200
-40 C 85 C
DROPOUT VOLTAGE ( mV )

DROPOUT VOLTAGE ( mV )

120 0 C 125 C
180
100
160
80
140
60
120
40

20 100

0 80
2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16
VIN ( V ) VIN ( V )

Figure 5-5. Dropout Voltage vs VIN (New Chip) Figure 5-6. Dropout Voltage vs VIN and Temperature (New Chip)

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5.6 Typical Characteristics (continued)

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, COUT = 2.2 µF for the legacy chip, and COUT = 4.7 µF for the new chip (unless otherwise noted)

200
Iout
1mA 50mA
10mA
150

Dropout (mV)
100

50

0
-75 -50 -25 0 25 50 75 100 125 150
Temperature (°C)

Figure 5-7. Dropout Voltage vs Temperature (Legacy Chip) Figure 5-8. Dropout Voltage vs Temperature (New Chip)
200
VO = 3.3 V
175 CO = 4.7 F

150
Dropout (mV)

125

100

75

50 Temperature
-55 °C 25 °C 150 °C
25 -40 °C 85 °C
0 °C 125 °C
0
0 5 10 15 20 25 30 35 40 45 50
IOUT (mA)

Figure 5-9. Dropout Voltage vs Load Current (Legacy Chip) Figure 5-10. Dropout Voltage vs Load Current (New Chip)
1400
Load Current
1200 0 10mA
1mA 50mA

1000
IGND (A)

800

600

400

200

0
-75 -50 -25 0 25 50 75 100 125 150
Temperature C

Figure 5-11. Ground Pin Current vs Temperature (Legacy Chip) Figure 5-12. Ground Pin Current vs Temperature (New Chip)

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5.6 Typical Characteristics (continued)

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, COUT = 2.2 µF for the legacy chip, and COUT = 4.7 µF for the new chip (unless otherwise noted)

700
Temperature
600 -55 °C 0 °C 85 °C 150 °C
-40 °C 25 °C 125 °C

500

400

IG (A)
300

200
VIN = 4.3 V
100 VOUT = 3.3 V
CO = 4.7uF
0
0 10 20 30 40 50
IL (mA)

Figure 5-13. Ground Pin Current vs Load Current (Legacy Chip) Figure 5-14. Ground Pin Current vs Load Current (New Chip)
1
Temperature
-55 °C 25 °C 150 °C
0.8 -40 °C 85 °C
0 °C 125 °C
0.6
IQ (mA)

0.4 VO = 3.3 V
CO = 4.7uF

0.2

-0.2
0 2 4 6 8 10 12 14 16
VIN

Figure 5-15. Input Current vs VIN (Legacy Chip) Figure 5-16. Input Current vs Input Voltage (New Chip)
5 3000
4 VIN = 6 V VO 2700
VO = 3.3 V I SC
3 2400
2 2100

Output Current - (mA)

Output Voltage - (V)

1 1800
0 1500
-1 1200
-2 900
-3 600
-4 300
-5 0
-6 -300
0 200 400 600 800 1000
200s/div

VIN = 6 V
Figure 5-17. Short-Circuit Current vs Time (Legacy Chip) Figure 5-18. Short-Circuit Current vs Time (New Chip)

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5.6 Typical Characteristics (continued)

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, COUT = 2.2 µF for the legacy chip, and COUT = 4.7 µF for the new chip (unless otherwise noted)

165
VIN = 4.3 V
COUT = 4.7 F

CURRENT LIMIT ( mA )
164

163

162

161
-55 -25 5 35 65 95 125 150
TEMPERATURE (C)

Figure 5-19. Short-Circuit Current vs Temperature (Legacy Figure 5-20. Short-Circuit Current vs Temperature (New Chip)
Chip)
5 3000
VIN = 16 V VO 2700
4
VOUT = 3.3 V I SC
3 2400

Short Ckt Current - (mA)

2 2100
Output Voltage - (V)

1 1800
0 1500
-1 1200
-2 900
-3 600
-4 300
-5 0
-6 -300
0 200 400 600 800 1000
200s/div

Figure 5-21. Short-Circuit Current vs Time (Legacy Chip) Figure 5-22. Short-Circuit Current vs Time (New Chip)

Figure 5-23. Output Impedance vs Frequency (Legacy Chip) Figure 5-24. Output Impedance vs Frequency (Legacy Chip)

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5.6 Typical Characteristics (continued)

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, COUT = 2.2 µF for the legacy chip, and COUT = 4.7 µF for the new chip (unless otherwise noted)

10
COUT
5
2.2F
10F
2
1

NOISE (V / Hz)

0.5

0.2
0.1
0.05

0.02
0.01
0.005
1x101 1x102 1x103 1x104 1x105 1x106 1x107
FREQUENCY (Hz)

VOUT = 3.3 V, IOUT = 50 mA

Figure 5-25. Output Noise Density (Legacy Chip) Figure 5-26. Output Noise Density vs COUT (New Chip)
10
IL
5
1mA
50mA
2
1
NOISE (V / Hz)

0.5

0.2
0.1
0.05

0.02
0.01
0.005
1x101 1x102 1x103 1x104 1x105 1x106 1x107
FREQUENCY (Hz)

VOUT = 3.3 V, COUT = 2.2 μF

Figure 5-27. Output Noise Density vs IOUT (New Chip) Figure 5-28. Ripple Rejection (Legacy Chip)
120 120
110 COUT 110
2.2F
100 10F 100
RIPPLE REJECTION (dB)

RIPPLE REJECTION (dB)

90 90
80 80
70 70
60 60
50 50
40 40
30 30
IL
20 20 1mA
10 10 50mA
0 0
1x101 1x10 2
1x103
1x10 4
1x10 5
1x10 6
1x10 7
1x101 1x102 1x103 1x104 1x105 1x106 1x107
FREQUENCY (Hz) FREQUENCY (Hz)

VOUT = 3.3 V, IOUT = 50 mA VOUT = 3.3 V, COUT = 2.2 μF

Figure 5-29. Ripple Rejection vs COUT (New Chip) Figure 5-30. Ripple Rejection vs IOUT (New Chip)

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5.6 Typical Characteristics (continued)

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, COUT = 2.2 µF for the legacy chip, and COUT = 4.7 µF for the new chip (unless otherwise noted)

Figure 5-31. Input to Output Leakage vs Temperature (Legacy Figure 5-32. Output Reverse Leakage vs Temperature (Legacy
Chip) Chip)

Figure 5-33. Output Reverse Leakage vs Temperature (New Figure 5-34. Turn-On Waveform (Legacy Chip)
Chip)

VON/OFF VOUT

5V

VOUT (V)

0V

VON/OFF (V)
5V
0V
200s/div →
VOUT = 3.3 V, IOUT = 50 mA
Figure 5-35. Turn-On Waveform (New Chip) Figure 5-36. Turnoff Waveform (Legacy Chip)

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5.6 Typical Characteristics (continued)

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, COUT = 2.2 µF for the legacy chip, and COUT = 4.7 µF for the new chip (unless otherwise noted)

VON/OFF VOUT

5V

VOUT (V)

0V

VON/OFF (V)
5V
0V
10 ms/div →
VOUT = 3.3 V, IOUT = 50 mA
Figure 5-37. Turnoff Waveform (New Chip) Figure 5-38. ON/OFF Pin Current vs VON/OFF (Legacy Chip)
0.4 0.8

0.2 0.6

0.4
0
ION/OFF (A)

ION/OFF (A)

0.2
-0.2
0
-0.4
-0.2
TEMP (C) TEMP (C)
-0.6 -55 0 85 150 -0.4 -55 0 85 150
-40 25 125 -40 25 125
-0.8 -0.6
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
VON/OFF (V) V0N/OFF (V)

VIN = 16 V VIN = 4.3 V

Figure 5-39. ON/OFF Pin Current vs VON/OFF (New Chip) Figure 5-40. ON/OFF Pin Current vs VON/OFF (New Chip)

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6 Detailed Description
6.1 Overview
The LP2980-N is a fixed-output, low-noise, high PSRR, low-dropout regulator that offers exceptional, cost-
effective performance for both portable and nonportable applications. The LP2980-N has an output tolerance
of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 50 mA of
continuous load current.
This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output
pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line
and load transient performance. The operating ambient temperature range of the device is –40°C to +125°C.
6.2 Functional Block Diagram

VIN Current VOUT

Limit

R1
UVLO

R2
+
–
GND

ON/OFF Internal Bandgap Output

Controller Reference Pull-down

VREF = 1.2 V GND

Thermal GND
Shutdown
GND

6.3 Feature Description

6.3.1 Output Enable
The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the
ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled when the ON/OFF pin
voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is
not needed, connect the ON/OFF pin to the input of the device.
For the new chip, the device has an internal pulldown circuit that activates when the device is disabled by pulling
the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin to actively discharge the output
voltage.
6.3.2 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.

V
RDS ON = I DO (1)
RATED

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6.3.3 Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme
limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device
turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the
output current fault condition continues, the device cycles between current limit and thermal shutdown. For more
information on current limits, see the Know Your Limits application note.
Figure 6-1 shows a diagram of the current limit.
VOUT

Brick-wall
VOUT(NOM)

0V

0 mA IRATED ICL

Figure 6-1. Current Limit

6.3.4 Undervoltage Lockout (UVLO)

For the new chip, the device has an independent undervoltage lockout (UVLO) circuit that monitors the input
voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from
turning off if the input drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics
table.

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6.3.5 Output Pulldown

The new chip has an output pulldown circuit. The output pulldown activates in the following conditions:
• When the device is disabled (VON/OFF < VON/OFF(LOW))
• If 1.0 V < VIN < VUVLO
Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can flow from the output to the input. This reverse current flow
can cause damage to the device. See the Reverse Current section for more details.
6.3.6 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis makes sure that the
device resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off
when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can
be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large
output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

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6.4 Device Functional Modes

6.4.1 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
• The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet
decreased to less than the enable falling threshold
6.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
6.4.3 Disabled
The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum
ON/OFF pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor
is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Application Information

7.1.1 Recommended Capacitor Types
This section describes the recommended capacitors for both the new chip and the legacy chip.
7.1.1.1 Recommended Capacitors for the Legacy Chip
The ESR of a good-quality tantalum capacitor is almost directly centered in the middle of the stable range of the
ESR curve (approximately 0.5 Ω–1 Ω). The temperature stability of tantalum capacitors is typically very good,
with a total variation of only approximately 2:1 over the temperature range of –40°C to +125°C (ESR increases
at colder temperatures). Avoid off-brand capacitors because some poor-quality tantalum capacitors are available
with ESR values greater than 10 Ω, which usually causes oscillation problems. One caution regarding tantalum
capacitors is that if used on the input, the ESR is low enough to be destroyed by a surge current if the capacitor
is powered up from a low impedance source (such as a battery) that has no limit on inrush current. In this case,
use a ceramic input capacitor that does not have this problem.
Ceramic capacitors are generally larger and more costly than tantalum capacitors for a given amount of
capacitance. These capacitors also have a very low ESR that is quite stable with temperature. However, the
ESR of a ceramic capacitor is typically low enough to make an LDO oscillate. A 2.2-μF ceramic capacitor
demonstrated an ESR of approximately 15 mΩ when tested. If used as an output capacitor, this ESR can cause
instability (see the ESR curves in the Typical Characteristics section). If a ceramic capacitor is used on the
output of an LDO, place a small resistor (approximately 1 Ω) in series with the capacitor. If used as an input
capacitor, no resistor is needed because there is no requirement for ESR on capacitors used on the input.
7.1.1.2 Recommended Capacitors for the New Chip
The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at
the input and output. Multilayer ceramic capacitors have become the industry standard for these types of
applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ
X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature,
whereas using Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage
and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and
output capacitors listed in the Recommended Operating Conditions table account for an effective capacitance of
approximately 50% of the nominal value.
7.1.2 Input and Output Capacitor Requirements
For the legacy chip, an input capacitor (CIN) ≥1 μF is required (the amount of capacitance can be increased
without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no
more than half an inch from the input pin and returned to a clean analog ground.
For the new chip, although an input capacitor is not required for stability, good analog design practice is to
connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient
response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher
value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is
located several inches from the input power source.

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Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor
within the range specified in the Recommended Operating Conditions table for stability.
7.1.3 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper area available for heat-spreading.
The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods
for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate
the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface
temperature 1 mm from the device package (TB) to calculate the junction temperature.

TJ = TT + ψJT × PD (2)

where:
• PD is the dissipated power
• TT is the temperature at the center-top of the device package

TJ = TB + ψJB × PD (3)

where:
• TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application note.
7.1.4 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).

PD = (VIN – VOUT) × IOUT (4)

Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage
required for correct output regulation.

For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).

TJ = TA + (RθJA × PD) (5)

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Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application
note, RθJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB
board layout optimization.
7.1.5 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the
long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V.
• If the device has a large COUT and the input supply collapses with little or no load current
• The output is biased when the input supply is not established
• The output is biased above the input supply
If reverse current flow is expected in the application, use external protection to protect the device. Reverse
current is not limited in the device, so external limiting is required if extended reverse voltage operation is
anticipated.
Figure 7-1 shows one approach for protecting the device.
Schottky Diode

Internal Body Diode

IN OUT
CIN COUT

GND

GND GND

GND

Figure 7-1. Example Circuit for Reverse Current Protection Using a Schottky Diode

7.2 Typical Application

Figure 7-2 shows the standard usage of the LP2980-N as a low-dropout regulator.

VIN 1 5 VOUT
1 μF 2.2 μF
LP2980-N

GND 2 GND

ON/OFF 3 4 N/C

NOTE: Do not make connections to NC pin.

Figure 7-2. LP2980-N Typical Application

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7.2.1 Design Requirements

For this design, use the minimum COUT value for stability (which can be increased without limit for improved
stability and transient response). The ON/OFF pin must be actively terminated. Connect this pin to VIN if the
shutdown feature is not used.
For the new chip, Table 7-1 summarizes the design requirements for Figure 7-2.
Table 7-1. Design Parameter
PARAMETER DESIGN REQUIREMENT
Input voltage 12 V
Output voltage 3.3 V
Output current 50 mA

7.2.2 Detailed Design Procedure

7.2.2.1 ON/OFF Input Operation
The LP2980-N is shut off by driving the ON/OFF input low, and turned on by pulling the ON/OFF input high. If
this feature is not used, the ON/OFF input must be tied to VIN to keep the regulator output on at all times (the
ON/OFF input must not be left floating).
To provide proper operation, the signal source used to drive the ON/OFF input must be able to swing above and
below the specified turn-on and turn-off voltage thresholds that specify an ON or OFF state (see the Electrical
Characteristics table).
For the legacy chip, the turn-on (and turn-off) voltage signals applied to the ON/OFF input must have a slew rate
greater than 40 mV/μs.
For the new chip, there is no restriction on the slew rate of the voltage signals applied to the ON/OFF input. Both
fast and slow ramping voltage signals can be used to drive the ON/OFF pin.

Note
For the legacy chip only, the ON/OFF function does not operate correctly if a slow-moving signal is
used to drive the ON/OFF input.

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7.2.3 Application Curves

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)

3.82 300
3.76 ILOAD = 50 mA VOUT 250
VOUT = 3.3 V ILOAD
3.7 200

OUTPUT VOLTAGE ( V )

LOAD CURRENT ( mA )
3.64 150
3.58 100
3.52 50
3.46 0
3.4 -50
3.34 -100
3.28 -150
3.22 -200
3.16 -250
3.1 -300
0 20 40 60 80 100 120 140 150
TIME ( s )

dI/dt = 1 A/μs
Figure 7-3. Load Transient Response (Legacy Chip) Figure 7-4. Load Transient Response (New Chip)
3.41 6.5 9
VOUT = 3.3 V VOUT COUT = 2.2uF VIN
3.39 IOUT = 50 mA VIN 6 RLOAD = 5k VOUT
VIN = 1 V 7
OUTPUT VOLTAGE ( V )

INPUT VOLTAGE ( V )

3.37 5.5
VOLTAGE (V)

5
3.35 5

3.33 4.5
3

3.31 4
1
3.29 3.5

3.27 3 -1
0 40 80 120 160 200 240 280 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
TIME ( s ) TIME (ms)

VOUT = 3.3 V, ΔVIN = 1 V, IOUT = 50 mA, dV/dt = 1 V/μs VOUT = 5 V, dV/dt = 1 V/μs
Figure 7-5. Line Transient Response (New Chip) Figure 7-6. Start-Up (New Chip)

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7.3 Power Supply Recommendations

A power supply can be used at the input voltage within the ranges given in the Recommended Operating
Conditions table.
7.4 Layout
7.4.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the circuit board and as near
as practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitors, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,
copper surface. Using vias and long traces to create LDO circuit connections is strongly discouraged and
negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and
thereby reduces load-current transients, minimizes noise, and increases circuit stability. Use a ground reference
plane that is either embedded in the PCB or located on the bottom side of the PCB opposite the components.
This reference plane provides accuracy of the output voltage, shields noise, and behaves similar to a thermal
plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet
thermal requirements.
7.4.2 Layout Example

VIN VOUT
Input IN OUT Output
Capacitor Capacitor

GND
Ground

ON/OFF
ON/OFF NC

Figure 7-7. LP2980-N Layout Example

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8 Device and Documentation Support

8.1 Device Support
8.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
8.2 Device Nomenclature
Table 8-1. Available Options(1)
PRODUCT VOUT

LP2980cxxxzX-y.y/NOPB c is the accuracy specification. xxx is the package designator. z is the package quantity.
X is for a large-quantity reel and non-X is for a small-quantity reel.
Legacy chip
y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
A is for higher accuracy and non-A is for standard grade.
xxx is the package designator. z is the package quantity.
LP2980AxxxzX-y.y/M3 X is for a large-quantity reel and non-X is for a small-quantity reel.
New chip y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process
technology.

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.

8.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision P (August 2016) to Revision Q (November 2023) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Changed entire document to align with current family format............................................................................ 1
• Added M3 devices to document......................................................................................................................... 1
• Updated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and
Thermal Information for M3-suffix(new chip)...................................................................................................... 4
• Added Device Nomenclature section............................................................................................................... 24

Changes from Revision O (June 2015) to Revision P (August 2016) Page

• Changed minor wording in Description for clarity............................................................................................... 1
• Changed "...an output tolerance of %..." to "...an initial output voltage tolerance of ±0.5%..." ........................ 14
• Deleted "Very high accuracy 1.23-V reference" .............................................................................................. 14
• Changed "150 mA" to "50 mA" to correct typo from reformat (2 places)..........................................................14
• Changed "...only 1 µA" to "...less than 1 µA"....................................................................................................14
• Changed "... pulled low" to "...pulled to less than 0.18 V" ............................................................................... 14

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LP2980AIM5-2.5/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L0NA Samples

LP2980AIM5-3.0/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L02A Samples

LP2980AIM5-3.3/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L00A Samples

LP2980AIM5-4.7/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L37A Samples

LP2980AIM5-5.0/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L01A Samples

LP2980AIM5X-2.5/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L0NA Samples

LP2980AIM5X-3.0/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L02A Samples

LP2980AIM5X-3.3/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L00A Samples

LP2980AIM5X-4.7/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L37A Samples

LP2980AIM5X-5.0/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L01A Samples

LP2980IM5-2.5/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L0NB Samples

LP2980IM5-3.0/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 L02B Samples

LP2980IM5-3.3/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 L00B Samples

LP2980IM5-3.8/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L21B Samples

LP2980IM5-4.7/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L37B Samples

LP2980IM5-5.0/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 L01B Samples

LP2980IM5X-2.5/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L0NB Samples

LP2980IM5X-3.0/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 L02B Samples

LP2980IM5X-3.3/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 L00B Samples

LP2980IM5X-5.0/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 L01B Samples

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Apr-2024

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-May-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP2980AIM5-2.5/NOPB SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980AIM5-3.0/NOPB SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980AIM5-3.3/NOPB SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980AIM5-4.7/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980AIM5-5.0/NOPB SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980AIM5X-2.5/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980AIM5X-3.0/NOPB SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980AIM5X-3.3/NOPB SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980AIM5X-4.7/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980AIM5X-5.0/NOPB SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980IM5-2.5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980IM5-3.0/NOPB SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980IM5-3.3/NOPB SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980IM5-3.8/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980IM5-4.7/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980IM5-5.0/NOPB SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-May-2024

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP2980IM5X-2.5/NOPB SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980IM5X-3.0/NOPB SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980IM5X-3.3/NOPB SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP2980IM5X-5.0/NOPB SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-May-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP2980AIM5-2.5/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LP2980AIM5-3.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LP2980AIM5-3.3/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LP2980AIM5-4.7/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP2980AIM5-5.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LP2980AIM5X-2.5/NOPB SOT-23 DBV 5 3000 208.0 191.0 35.0
LP2980AIM5X-3.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LP2980AIM5X-3.3/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LP2980AIM5X-4.7/NOPB SOT-23 DBV 5 3000 208.0 191.0 35.0
LP2980AIM5X-5.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LP2980IM5-2.5/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP2980IM5-3.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LP2980IM5-3.3/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LP2980IM5-3.8/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP2980IM5-4.7/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP2980IM5-5.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LP2980IM5X-2.5/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LP2980IM5X-3.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

Pack Materials-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-May-2024

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP2980IM5X-3.3/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LP2980IM5X-5.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

Pack Materials-Page 4
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 4X 0 -15 (1.1) TYP
0.00
1.45
0.90
4X 4 -15

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/K 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/K 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/K 08/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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