QB Unit 2 Answers
QB Unit 2 Answers
UNIT - II
1) 1 MARK
c)Define Quantization?
Ans: Quantization refers to the use of a finite set of amplitude levels
and the selection of a level nearest to a particular sample value of the
message signal as the representation for it.
2) 3 MARKS
2Пfm=6280; 2Пfc=3.14x107;
3.14𝑥107
Carrier frequency, fc= =5MHz
2𝛱
𝜇2
The total power of AM wave=PTotal= PC(1+ )
2
𝐴𝐶 2 (400)2
PC= = = 133.33W
2𝑅 2𝑥600
0.42
PTotal= 133.33 (1 + )=144W
2
Ans:
3) 5 MARKS
Step 4: Detection and multiplexing the odd and even bit sequences
The symbol timing recovery circuit recover the clock at the symbol rate
or a multiple of symbol rate from the integrated output signal.This clock
is required to convert the continuous time received signal into a discrete
time sequence of data symbols.At the end of the clock period T S, the
output value of integrator is taken(sampled). The output values of the two
integrators are taken(sampled) at the offset of one bit period Tb. The
decision device detects the bit as bit’1’if the output value exceeds the
decision threshold else the bit is detected as bit ‘0’. After detection the
odd and even sequences are combined by the multiplexer.
Bandwidth=2(Δf+fm)= 2(200+2k)=2x2200=4400=4.4kHz
PCM is digital pulse modulation system. This means that the PCM output
is in the coded digital form. It is in the form of digital pulses of constant
amplitude, width and position. The information is transmitted in the form
of "code words". A PCM system consists of a PCM encoder (transmitter)
and a PCM decoder (receiver).The essential operations in the PCM
transmitter are sampling, quantizing and encoding.
Amplitude Shift Keying(ASK):
Following is the diagram for ASK modulated waveform along with its
input.
Frequency Shift Keying(FSK):
Following is the diagram for FSK modulated waveform along with its
input.
Binary Phase Shift Keying(BPSK):
4) 10 MARKS
A)Explain a method to generate AM signal?
V2(t)=k1[m(t)+Accos(2πfCt)]+k2[m(t)+Ac cos(2πfct)]2
⇒V2(t)=k1m(t)+k1Accos(2πfct)+k2m 2(t)+k 2Ac 2cos22πfct+2k2m(t)Ac
cos(2πfct)
⇒V2(t)=k1m(t)+k2m2 (t)+k2 AC2
cos2(2πfct)+k1Ac[1+(2k2/k1)m(t)]cos(2πfct)
The last term of the above equation represents the desired AM wave and
the first three terms of the above equation are unwanted. So, with the help
of band pass filter, we can pass only AM wave and eliminate the first
three terms.
Therefore, the output of square law modulator is
s(t)=k1Ac[1+(2k2/k1)m(t)]cos(2πfct) which is an AM wave
The standard equation of AM wave is
s(t) = k1A c (1+ µ cos(2πf mt)) cos(2πf ct)
where µ=(2k2/k1)= modulation index
A sample and hold circuit shown in fig (a) is used to produce Flat top
sampled PAM. The working principle of this circuit is quite easy.
The sample and Hold (S/H) circuit consists of two field effect transistors
(FET) switches and a capacitor.
The sampling switch is closed for a short duration by a short pulse
applied to the gate G1 of the transistor.
During this period, the capacitor ‘C’ is quickly charged upto a voltage
equal to the instantaneous sample value of the incoming signal x(t).
Now, the sampling switch is opened and the capacitor ‘C’ holds the
charge.
The discharge switch is then closed by a pulse applied to gate G2 of the
other transistor.
Due to this, the capacitor ‘C’ is discharged to zero volts. The discharges
switch is then opened and thus capacitor has no voltage.
Hence, the output of the sample and hold circuit consists of a sequence of
flat top samples as shown in fig(b) below
Pulse Width Modulation (PWM):
The width of the pulse varies in this method, but the amplitude of the
signal remains constant. Amplitude limiters are used to make the
amplitude of the signal constant. These circuits clip off the amplitude to a
desired level, and hence the noise is limited.Thus, the PWM system is
more immune to noise than the PAM signal.
PWM OUTPUT
BFSK TRANSMITTER
From the table we observe that 𝑃𝐻 (t) is same as b(t) and PL(t) is the
inverted version of b(t).The block diagram of FSK Transmitter is shown
below
We know that input sequence b (t) is same as PH(t). An inverter is added
after b (t) to get PL(t). PH(t) and PL(t) are unipolar signals. The level
shifter converts the '+1' level to √𝑃𝑆 𝑇𝑏 . Zero level is unaffected. Thus the
output of the level shifters will be either √𝑃𝑆 𝑇𝑏 (if '+1') or zero (if input is
zero). Further there are product modulators after level shifter. The two
carrier signals Ⴔ1(t) and Ⴔ2(t) are used. In one bit period of input signal
(i.e. Tb), Ⴔ1(t) or Ⴔ2(t) have integral number of cycles.
Therefore the modulated signal has continuous phase. Such BFSK signal
is shown in Fig. 6.7.2. The adder then adds the two signals.
Here note that outputs from both the multipliers are not possible at a time.
This is because PH(t) and PL(t) are complementary to each other.
Therefore if PH(t) =1, then output will be only due to upper modulator
and lower modulator output will be zero(since P L(t)=0)
BFSK RECEIVER
The following shows the block diagram of coherent BFSK receiver.
There are two correlators for two frequencies of FSK signal. These
correlators are supplied with locally generated carriers Ⴔ1(t) and Ⴔ2(t) . If
the transmitted frequency is fH, then output s1(t) will be higher than s2(t).
Hence y(t) will be greater than zero.
The decision device then decides in favour of binary ‘1’. If s 2 (t)> s1(t)
then y(t)<0 and decision device decides in favour 0f ‘0’.
Bandwidth of FSK signal=4fb Hz