584 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO.

3, MARCH 2013

temperature variation, and clamp VVDD close to a target level at 10-bit 30-MS/s SAR ADC Using a Switchback
runtime in spite of any given NBTI degradation and/or temperature Switching Method
variation within the specified ranges. As a result, active leakage Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu,
power is reduced by 8%–10%, while dynamic power is reduced by and Ying-Zu Lin
2.8%–3.7% for the given range of average die temperatures in early
chip lifetime. Finally, we demonstrated that they maintain VVDD
close to a target level even in the presence of WID spatial process
and temperature variations. VVDD clamping helps to improve Abstract— This brief presents a 10-bit 30-MS/s successive-
gate-oxide reliability. Oxide failure rate is reduced by 5% for the approximation-register analog-to-digital converter (ADC) that uses
a power efficient switchback switching method. With respect to the
fast process corner and ∼4% for the nominal and slow corners at monotonic switching method, the input common-mode voltage variation
t = 7.5 years. reduces which improves the dynamic offset and the parasitic capacitance
variation of the comparator. The proposed switchback switching method
does not consume any power at the first digital-to-analog converter
R EFERENCES switching, which can reduce the power consumption and design effort
of the reference buffer. The prototype was fabricated in a 90-nm 1P9M
[1] E. Wu and J. Suñé, “Power-law voltage acceleration: A key element for CMOS technology. At 1-V supply and 30 MS/s, the ADC achieves an
ultrathin gate oxide reliability,” J. Microelectron. Rel., vol. 45, no. 12, sequenced neighbor double reservation of 56.89 dB and consumes 0.98
pp. 1809–1834, Dec. 2005. mW, resulting in a figure-of-merit (FOM) of 57 fJ/conversion-step. The
[2] V. Huard, M. Denais, and C. Parthasarathy, “NBTI degradation: From ADC core occupies an active area of only 190 × 525 µm2 .
physical mechanisms to modelling,” J. Microelectron. Rel., vol. 46, no. 1,
pp. 1–23, Jan. 2006. Index Terms— Analog-to-digital converter (ADC), energy efficient
switching method, low input capacitance, successive approximation,
[3] R. Vattikonda, W. Wang, and Y. Cao, “Modeling and mini-
successive-approximation-register (SAR) ADC.
mization of PMOS nbti effect for robust nanometer design,” in
Proc. IEEE Design Autom. Conf., San Francisco, CA, Sep. 2006,
pp. 1047–1052. I. I NTRODUCTION
[4] S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, and S. Vrudhula,
“Predictive modeling of the NBTI effect for reliable design,” in With the feature size of CMOS devices scaled down, the prop-
Proc. IEEE Custom Integr. Circuit Conf., San Jose, CA, Sep. 2008, agation delay of logic circuit decreases significantly. Successive-
pp. 189–192. approximation-register (SAR) analog-to-digital converters (ADCs)
[5] R. Fernandez, B. Kaczer, A. Nackaerts, S. Demuynck, R. Rodriguez, have achieved several tens of MS/s to low GS/s sampling rates with 5-
M. Nafria, and G. Groeseneken, “AC NBTI studied in the 1 Hz–2 GHz to 10-bit resolutions recently [2]–[8]. The comparator and sampling
range on dedicated on-chip circuits,” in Proc. IEEE Int. Electron. Devices
Meeting, San Francisco, CA, Dec. 2006, pp. 337–340. switches are the only analog components of the SAR ADCs, and no
[6] K. T. R. Persaud and C. Kim, “Silicon odometer: An on-chip reli- building block consumes static power if preamplifiers are not used.
ability monitor for measuring frequency degradation of digital cir- Therefore, the SAR ADCs are power- and area-efficient architecture.
cuits,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 874–880, For some high-conversion-rate applications, power- and area-efficient
Apr. 2008. SAR ADCs possibly replace pipelined ADCs in nanometer-scaled
[7] A. Sinkar and N. Kim, “Analyzing and minimizing effects of temperature CMOS processes.
variation and NBTI on active leakage power of power-gated circuits,”
in Proc. IEEE Int. Symp. Quality Electron. Design, San Jose, CA, Mar.
In the past few years, several power-efficient switching sequences
2010, pp. 790–796. for the capacitive digital-to-analog converter (DAC) have been pro-
[8] P. Heydari and M. Pedram, “Analysis of jitter due to power-supply noise posed. Compared to the conventional switching sequence, the energy-
in phase-locked loops,” in Proc. IEEE Custom Integr. Circuits Conf., saving [1], monotonic [2], and Vcm -based [3] switching sequences
Orlando, FL, May 2000, pp. 443–446. reduce 69%, 81%, and 90% switching energy, respectively. Although,
[9] J. Stathis, “Percolation models for gate oxide breakdown,” J. Appl. Phys., the Vcm -based one reduces the most power consumption, it needs
vol. 86, no. 10, pp. 5757–5766, Nov. 1999. more switches and reference voltages than the monotonic one, which
[10] E. Wu, J. Suñéc, W. Laia, E. Nowaka, J. McKennaa, A. Vayshenkerb, and
increase the complexity and power consumption of the digital control
D. Harmona, “Interplay of voltage and temperature acceleration of oxide
breakdown for ultrathin gate oxides,” J. Solid State Electron., vol. 46, circuits. The monotonic switching sequence has the fewest switches
no. 11, pp. 1787–1798, Nov. 2002. and reference voltages. However, during the conversion process, the
[11] E. Wu, J. Sune, and W. Lai, “On the weibull shape factor of intrinsic common-mode voltage of the comparator input terminal varies from
breakdown of dielectric films and its accurate experimental determi- Vcm to Vrefn , as shown in Fig. 1(a). It induces dynamic offset and the
nation, Part II: Experimental results and the effects of stress condi- parasitic capacitance variation of the comparator to affect the ADC
tions,” IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2141–2150,
Dec. 2002. linearity.
[12] C. Zhuo, D. Sylvester, and D. Blaauw, “Process variation and This brief proposes a SAR ADC using a switchback switching
temperature-aware reliability management,” in Proc. IEEE Design method, which has the fewest number of switches and reference
Autom. Test Eur., Mar. 2010, pp. 580–585. voltage as the monotonic. Moreover, the proposed switching sequence

Manuscript received October 9, 2011; revised January 30, 2012; accepted

February 16, 2012. Date of publication March 22, 2012; date of current
version February 20, 2013. This work was supported in part by the
National Science Council and Himax Technologies Inc., Taiwan, under
Grant NSC-98-2221-E-006-156-MY3.
The authors are with the Department of Electrical Engineering,
National Cheng Kung University, Tainan 701, Taiwan (e-mail: pet@sscas.
ee.ncku.edu.tw; tvlsieic@eecs.northwestern.edu; ckim@korea.ac.kr; soon@
mail.ncku.edu.tw).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2012.2190117
1063–8210/$31.00 © 2012 IEEE
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 3, MARCH 2013 585

Sample Phase 1 Phase 2 Phase 3 Phase 4 Sample Phase 1 Phase 2 Phase 3 Phase 4 96CVref2 Vip-Vin > ½ Vref ? 32CVref2

Vip Vip Vrefn Vrefp Vrefn No Vrefn Vrefn Vrefn Yes Vrefn Vrefn Vrefn
C9 C8 C7' C9 C8 C7' C9 C8 C7'
Vcm Vcm Vip + Vip + Vip +
Vin - Vin - Vin -
C9 C8 C7' C9 C8 C7' C9 C8 C7'
Vin Vin Vrefp Vrefn Vrefn Vrefp Vrefn Vrefn Vrefp Vrefp Vrefn

Vrefp Vrefn Vrefn Vrefp Vrefn Vrefn Yes 0

Bout 1 1 0 1 Bout 1 1 0 1 C9 C8 C7'
0 C9 C8 C7'
(a) (b) Vip + Vip +
Vip-Vin > 0 ?
Vin - Vin -
C9 C8 C7' C9 C8 C7'
Fig. 1. (a) Waveform of monotonic switching procedure. (b) Waveform of Vrefp Vrefn Vrefn Vrefp Vrefn Vrefn No
0
switchback switching procedure. Vrefp Vrefp Vrefn Vrefp Vrefn Vrefn Vrefp Vrefn Vrefn
C9 C8 C7' C9 C8 C7' C9 C8 C7'
Vip + Vip + Vip +
Vrefp Vin - Vin - Vin -
Vrefn C9 C8 C7' C9 C8 C7' C9 C8 C7'
SPP99 SPP88 SPP77 SPP66 SPP55 SPP44 SPP33 SPP22 SPP11 Vrefn Vrefn Vrefn
No
Vrefn Vrefn Vrefn Yes Vrefn Vrefp Vrefn

Sb C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
32CVref
Vip-Vin > -½ Vref ? 96CV 2
Vrefn
2
9 ref
Bootstrapped Reference DAC Ci+1 = 2Ci, C7' = C7 + ~ + C0, and C1 = C0 = C, i = 1~8
switch Sa Csp B9 Vref = Vrefp - Vrefn
Vip Sampling
capacitor CMP SAR Fig. 3. Switchback switching procedure of 10-bit SAR ADC.
Vin
Sa Csn B0
Reference DAC
Vrefn 9 As the monotonic switching procedure, the switchback switching
Sb C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
SNN99 SNN88 SNN77 SNN66 SNN55 SNN44 SNN33 SNN22 SNN11 procedure only switches a capacitor in each bit cycle, which reduces
Vrefn both charge transfer in the capacitive DAC network and the transitions
Vrefp of the control circuit and switch buffer, resulting in smaller power
Ci+1 = 2Ci and C1 = C0 where i = 1~8 dissipation. Moreover, the common-mode voltage of the switchback
switching procedure would be downward just for the first switching
Fig. 2. Block diagram of the proposed ADC.
and then upward for the remainder. Hence, the maximum variation
of the common-mode voltage is 1/4 Vref and the common-mode
voltage will gradually approach the common-mode voltage of the
reduces 50% of the common mode voltage variation, as shown in
input signal Vcm . It reduces the dynamic offset and the parasitic
Fig. 1(b). It does not consume any DAC switching energy at the
capacitance variation of the comparator.
first switching. Therefore, it can reduce the power consumption and
Fig. 3 shows an example of the switchback switching method,
design effort of the reference buffer.
where a 10-bit binary-weighted capacitive DAC is adopted and it
The remainder of this brief is organized as follows. Section II
is the same as the reference DAC adopted in Fig. 2. In order to
describes the architecture and design concept of the proposed SAR
simplify the illustration of the switchback switching method, the
ADC. Section III presents the implementation of key building blocks.
sampling capacitor of Fig. 2 is omitted in Fig. 3. The quantitative
Section IV shows the measurement results. Conclusions are given in
energy consumption of the first three switching phases is shown.
Section V.
For the switchback switching method, the bottom plate of the MSB
capacitor is connected to Vref p and the rest are connected to Vrefn
II. A RCHITECTURE AND D ESIGN C ONCEPT OF at the sampling phase. Then the sampling switches turn off, the
THE P ROPOSED SAR ADC comparator directly performs the first comparison without switching
A. ADC Architecture any capacitor. After the MSB is determined, one MSB capacitor will
switch to Vrefn . There is no energy consumption at this conversion
Fig. 2 shows the complete block diagram of the proposed ADC step.
[4]. The ADC core consists of two sampling capacitors, two For an n-bit SAR ADC, if each digital output code is equiprobable,
capacitive reference DACs, dynamic-latched comparator and SAR the average switching energy of the monotonic [2] and Vcm -based
control logic. The proposed capacitive DAC is split into two parts: switching method [3] can be derived as
a reference DAC and a sampling capacitor. The sampling capacitor
captures the input signal and the reference DAC provides the n−1  
reference signal. The reference DAC is a binary-weighted capacitor E avg,mono = 2n−2−i C Vref
2 (1)
array which has better linearity than the C-2C capacitor array or the i=1
capacitor array with a bridged capacitor. n−1   
At the sampling phase, the switches Sa and Sb are turned on and E avg,Vcm = 2n−2−2i 2i − 1 C Vref
2 (2)
the input signal is sampled onto the sampling capacitors, Csp and i=1
Csn . The bottom plate of the most-significant-bit (MSB) capacitor where C is the unit capacitance of the DAC and Vref is the reference
in the reference DAC is switched to Vref p and those of LSBs are voltage supply to reference DAC, Vref = Vref p − Vrefn . The average
switched to Vrefn at the same time. Meanwhile, the reference DAC switching energy for an n-bit SAR ADC using the switchback
is at the reset state. Next, the switches Sa and Sb are turned off switching procedure can be derived as
and the SAR ADC begins the conversion phase. The comparator
n−2  
determines whether Vip is higher than Vin or not at the beginning
E avg,switch = 2n−3−i C Vref
2 . (3)
of the conversion phase. If Vip is higher than Vin , the MSB will be
i=1
set to 1. Otherwise, the MSB is 0. Then the MSB triggers the SAR
logic to control the reference switching of the DAC by the proposed For a 10-bit case, the monotonic and Vcm -based switching pro-
switchback switching procedure. cedures consume 255.5 and 170.2 CV 2ref , respectively, while the
586 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 3, MARCH 2013

Clkc
1000 P1 P2 P3 P9 P10 Sample
Switchback (w/o reset power)
D Q D Q D Q D Q D Q D Q
Switchback (w/ reset power)
Monotonic Valid
Switching power (CVref )

800
2

Vcm-based Clk
Energy-saving (a)
Clk
600 Sample
Clkc
P1
P2
400 P3
P4
P5
200 P6
P7
P8
P9
0 P10
0 200 400 600 800 1000 (b)
Output codes

Fig. 4. Switching energy versus output code. Fig. 7. Proposed asynchronous phase generator. (a) Schematic. (b) Timing
diagram.
5
8
Parasitic Capacitance (fF)

7 4.8
Parasitic Capacitance (fF)

5 4.6

3
4.4

2
4.2
1

0
0 0.2 0.4 0.6 0.8 1 4
Input signal swing (Vref) 0 0.1 0.2 0.3 0.4 0.5
Input signal swing (Vref) SAR

Fig. 5. Parasitic capacitance versus input common-mode voltage at the Reference DAC Reference DAC 0.190 mm
comparator input terminal. C
M
Sampling capacitor P Sampling capacitor
0.525 mm
Clkc_b
Fig. 8. Die micrograph.
Outp1 Outn1
Clkc Outn Outp
Vip Vin
2
Outp1 Outn1
DNL(lsb)

1
Vbias 0
-1
Pre-amp Latch Comparator 0 200 400
Code
600 800 1000

Outp 2
Valid
INL(lsb)

Outn
0

Fig. 6. Dynamic comparator with a pre-amplifier.

-2
0 200 400 600 800 1000
Code

Fig. 9. DNL and INL at 30 MS/s.

proposed switching procedure consumes only 127.5 CV 2ref . The
proposed technique thus requires 50% less switching energy than the
monotonic one and 25% less than the Vcm -based one. Fig. 4 shows MSB capacitor must settle to the reference voltage in a very short
a comparison of switching energy for the four methods versus the time during the conversion phase. The MSB capacitor of switchback
output code. switching method is pre-charged in the sampling phase which
Although the switchback switching method consumes less power allows longer settling time than the conversion phase. Therefore,
than the monotonic and Vcm -based switching methods during the the switchback switching method does not require a fast-settling
conversion phase. It must be pre-charged in the sampling phase. For reference buffer to charge MSB capacitor in the conversion phase.
a 10-bit case, if all of the switching methods sample the same input
signal, the switchback switching method consumes 255.5 CV 2ref . III. I MPLEMENTATION OF K EY B UILDING B LOCKS
Fig. 4 also shows a comparison of switching energy for the four
methods versus the output code when both sampling and conversion A. S/H Circuit
phase are calculated. The proposed SAR ADC samples input signal on the sampling
Accordingly, the switchback switching method may consume capacitors, Csp and Csn , via the bootstrapped switches, Sa and Sb [9].
more power than the monotonic and Vcm -based switching methods The nonlinear variation of the parasitic capacitance during the
if both sampling and conversion phases are taken into consideration. conversion phase, induced by the sampling switch Sa and the
Nevertheless, it is worth to note that the switchback switching comparator input pair, affects the linearity of the proposed SAR ADC.
method reduces the design overhead of reference voltage circuit. The top-plate parasitic capacitance of the sampling capacitor is a
The reason is for monotonic or Vcm -based switching methods, the constant value, which does not affect the ADC performance. Fig. 5
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 3, MARCH 2013 587

0 70

Power Spectrum Density(dBFS)

SNDR = 56.25dB 65

SNDR & SFDR (dB)

-20 SFDR = 68.15dB
60
-40
55

-60 50
SNDR
SFDR
-80 45

40 0 1
-100 10 Input Frequency (MHz) 10
0 5 10 15
Input Frequency(MHz)

Fig. 10. Measured power spectrum at 30 MS/s and 2-MHz input. Fig. 11. Dynamic performance versus input frequency.

70
shows the parasitic capacitance at the gate of the comparator input
differential pair, Cgs + Cgd + Cgb . With the bootstrapped switch, a 65

SNDR & SFDR (dB)

small-size sampling switch is adopted. During the conversion phase,
60
the bootstrapped switch turns off and the parasitic capacitance of
drain terminal, Cgd + Cds , is smaller than 0.01 fF. Therefore, Fig. 5 55

just shows the simulated parasitic capacitance of the pre-amp input 50

SNDR
pair, which is the total capacitance of gate terminal. During the SFDR
transition of the monotonic switching method, 0–0.5 Vref , where Vref 45

is Vref p − Vrefn , the parasitic capacitance varies from 4.4 to 4.9 fF. 40
10 20 30 40 50
Moreover, with the switchback switching method, the common-mode- Sampling Frequency(MHz)
voltage variation decreases from 0.5 to 0.25 Vref . In this case, the
Fig. 12. Dynamic performance versus sampling frequency.
parasitic capacitance varies from 4.74 to 4.9 fF.
The voltage of comparator input terminal, VCMP , can be expressed
as TABLE I
S PECIFICATION S UMMARY
Csp
VCMP = Vin + VDAC
Csp + C p1 Specifications (unit) Experimental results
⎛ 
⎞
Supply voltage (V) 1.0
C p1 C p1
= Vin + ⎝1 − − ⎠ VDAC (4) Input range (Vpp ) 1.2
Ctotal Ctotal Active area (mm2 ) 0.10
Input capacitance (pF) 0.4
where C p1 is the parasitic capacitance at the comparator input
Sampling rate (MS/s) 30
terminal, including the top-plate parasitic capacitance of the sampling
DNL (LSB) −0.66 ∼ 0.88
capacitor and the parasitic capacitance of the pre-amplifier. C p1 is the
INL (LSB) −1.27 ∼ 1.32
constant part of C p1 and C p1 is the variable part of C p1 . VCMP
ENOB (bit) 9.16 @ 30 MS/s
and VDAC are the voltages of the comparator input and reference
56.89/68.65 (0.5 MHz)
DAC output, respectively. VDAC can be written as SNDR/SFDR (dB) 56.25/68.15 (2 MHz)

9
ERBW (MHz) 15 @ 30 MS/s
Di · 2i−1 · C
i=1 Power (mW) 0.98
VDAC = Vref . (5) FOM (fJ/conv.-step) 57

9 C ·C
2i−1 · C + Cspsp+Cp1
p1
i=1
If the parasitic capacitance C p1 is a constant value (C p1 = 0), it sampling capacitance, the kickback noise originated from the latched
can be regarded as a fixed gain error and does not affect the dynamic comparator becomes more critical. Furthermore, the bottom plate of
performance. However, C p1 here is not a constant value. During the the sampling capacitors, Csp and Csn , are floating and hence sampling
conversion process, C p1 is 0.16 fF, which affects the ADC linearity. capacitors are more sensitive to kickback noise than the conventional
To achieve 10-bit linearity, assume the maximum error due to C p1 case. Therefore, the proposed comparator adopts a pre-amplifier to
must be smaller than 0.5 LSB. From (4), the minimum capacitance of block the kickback noise and enhance the comparison speed.
the sampling capacitor Csp is 328 fF. According to (5), the minimum
unit capacitance C is 0.64 fF. If the monotonic switching method is C. SAR Control Logic
adopted, the minimum capacitance of the sampling capacitor Csp is
1025 fF. With the proposed switching method, the minimum input To avoid a high-frequency clock generator and a pulse-width
capacitance decrease from 1025 to 328 fF. For routing parasitic modulator (PWM), the proposed ADC uses an asynchronous control
capacitance, process variation and matching issues, the adopted circuit to internally generate the necessary clock signals [5]. Fig. 7
values of Csp and C are 400 and 5 fF, respectively. The sampling shows a schematic and a timing diagram of the asynchronous phase
capacitors and reference DAC are metal-oxide-metal capacitors [2]. generator. The conversion process starts once the system clock is
switched to low. Sample is the sample signal which turns on the
sampling switches. After ten comparisons, Sample will be set to
B. Dynamic Comparator high to sample the input signal until the system clock, Clk, switches
Fig. 6 shows the schematic of the comparator which consists to low. Therefore, the duty cycle of the system clock, Clk, is 50%
of a pre-amplifier and a dynamic latched comparator. With a low and no PWM is needed for the integration application. The dynamic
588 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 3, MARCH 2013

TABLE II
C OMPARISON TO S TATE - OF - THE -A RT W ORKS

Specifications (unit) JSSC’10 [2] JSSC’10 [3] ISSCC’08 [6] TCAS II’10 [7] ISSCC’10 [8] proposed
Architecture SAR SAR SAR SAR SAR SAR
Technology 0.13 mm 90 nm 90 nm 65 nm 65 nm 90 nm
Supply voltage (V) 1.2 1.2 1 1.0 1 1
Sampling rate (MS/s) 50 100 40 80 50 30
Resolution (bit) 10 10 9 9 10 10
Sampling capacitance (pF) 2.5 2.0 5 0.64 0.53 0.4
ENOB (bit) 9.18@0.5 MHz 9.1@1.8 MHz 8.56@1 MHz 8.18@39 MHz 9.16@2 MHz 9.16@0.5 MHz
Power (mW) 0.826 3 0.82 1.7 0.82 0.98
FOM (fJ/conv.-step) 29 55 54 39 30 57
Active area (mm2 ) 0.052 0.181 0.09 0.05 0.039 0.1

comparator generates the Valid signal after each comparison. Clkc is which makes the FOM larger than the other works. Nevertheless, if
the control signal of the dynamic comparator. P1 to P10 sample the the power consumption of the front-end buffer and reference buffer
digital output codes of the comparator and serve as control signals for is considered, the FOM of the proposed ADC will be lower than the
the capacitor arrays to perform the switchback switching procedure. other works.

IV. M EASUREMENT R ESULTS

V. C ONCLUSION
The ADC was fabricated in a 1P9M 90-nm CMOS technology.
The micrograph of the ADC core is shown in Fig. 8. The ADC In this brief, a SAR ADC with a new switching method was
core only occupies an area of 525 × 190 μm. The ADC has a 1.2-V presented. The proposed switching procedure reduces the parasitic
peak-to-peak differential input range. The measurement results of the capacitance variation and the comparator dynamic offset induced by
prototype are presented below. input common-mode-voltage variation. The input capacitance of the
The measured differential nonlinearity (DNL) and integral nonlin- proposed ADC is just 0.4 pF, which reduces the power consumption
earity (INL) of the proposed ADC are shown in Fig. 9. The peak and design effort of the front-end buffer. The prototype occupies an
DNL and INL are −0.66/0.88 and −1.27/1.32 LSB, respectively. active area of 0.1 mm2 , and achieves a 30-MS/s operation speed
Fig. 10 shows the measured fast Fourier transform spectrum with with power consumption less than 1 mW, resulting in an FOM of
an input frequency close to 2 MHz at a 1.0-V supply and a 30-MS/s 57 fJ/conversion-step.
sampling rate. The measured signal-to-noise distortion ratio (SNDR).
and spurious free dynamic range (SFDR) are 56.25 and 68.15 dB, ACKNOWLEDGMENT
respectively. The authors would like to thank National Chip Implementation
Fig. 11 plots the measured SNDR and SFDR versus the input Center, Hsinchu, Taiwan, for supporting the chip implementation.
frequency at 30 MS/s. At a low input frequency, the measured SNDR
and SFDR are 56.89 and 68.65 dB, respectively. The resultant ENOB
R EFERENCES
is 9.16 bits. When the input frequency increases to 15 MHz, the
measured SNDR and SFDR are 53.99 and 68.1 dB, respectively. The [1] W. Y. Pang, C. S. Wang, Y. K. Chang, N. K. Chou, and C. K. Wang, “A
effective resolution bandwidth is higher than 15 MHz. 10-bit 500-KS/s low power SAR ADC with splitting capacitor for bio-
medical applications,” in Proc. IEEE ASSCC Tech. Papers, Nov. 2009,
Fig. 12 shows the measured performance versus the sampling pp. 149–152.
frequency with a 0.5-MHz sinusoidal stimulus. When the sampling [2] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 10-bit 50-MS/s
rate was 10 MS/s, the SNDR and SFDR were 57.13 and 68.17 SAR ADC with a monotonic capacitor switching procedure,” IEEE J.
dB, respectively. When the sampling rate was over 30 MS/s, the Solid-State Circuits, vol. 45, no. 4, pp. 731–740, Apr. 2010.
[3] Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, S.-P. U. R. P. Martins, and
performance rapidly degrades because the time for input signal
F. Maloberti, “A 10-bit 100-MS/s reference-free SAR ADC in 90 nm
sampling was insufficient. CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111–1121,
At a 1.0-V supply and 30 MS/s, the analog part, including the S/H Jun. 2010.
circuit and dynamic comparator, consumes 0.55 mW. The switching [4] G.-Y. Huang, C.-C. Liu, Y.-Z. Lin, and S.-J. Chang, “A 10-bit 12 MS/s
power of the reference DAC draws 0.08 mW and the digital control successive approximation ADC with 1.2-pF input capacitance,” in IEEE
ASSCC Dig. Tech. Papers, Nov. 2009, pp. 157–160.
logic consumes 0.35 mW. The pre-amplifier depletes most of the [5] S. W. M. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW
analog power (76%) because it consumes static power consumption. asynchronous ADC in 0.13-μm CMOS,” in IEEE ISSCC Dig. Tech.
The proposed switching sequence reduces the DAC switching power Papers, Feb. 2006, pp. 574–575.
significantly; it just occupies 8.1% of the total power. Excluding [6] V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas,
the output buffers, the total power consumption is 0.98 mW. A and J. Craninckx, “An 820 μW 9b 40 MS/s noise-tolerant dynamic-
SAR ADC in 90 nm digital CMOS,” in IEEE ISSCC Dig. Tech. Papers,
specification summary of the ADC is listed in Table I. Feb. 2008, pp. 238–239.
Table II compares the proposed ADC with other state-of-the-art [7] M. Furta, M. Nozawa, and T. Italura, “A 9-bit 80 MS/s successive
SAR ADCs [2], [3], [6]–[8]. To compare the proposed ADC to other approximation register analog-to-digital converter with a capacitor reduc-
works with different sampling rates and resolutions, the well-known tion technique,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 7,
pp. 502–506, Jul. 2010.
figure-of-merit (FOM) equation is used [8] M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, “A 10b
Power 50 MS/s 820 mW SAR ADC with on-chip digital calibration,” in Proc.
FOM = ENOB . (6) IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 384–385.
2 × min {2 × ERBW, f s }
[9] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline
The FOM of the proposed ADC is 57 fJ/conversion-step at 30 analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5,
MS/s and a 1.0-V supply. The pre-amplifier consumes 0.46 mW, pp. 599–606, May 1999.