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NMOS Subthreshold Characterization

Comprehensive Laboratory Manual

Department of Electrical Engineering
Indian Institute of Technology, Bombay

Table of Contents
1. Introduction
2. Theoretical Background
3. Experimental Setup
4. Detailed Procedures
5. Expected Results
6. Safety Protocols
7. Analysis Methods

1. Introduction

1.1 Objectives
• Characterize NMOS subthreshold behavior
• Extract key parameters (swing, leakage current)
• Study temperature effects
• Analyze drain voltage dependence

1.2 Components Required

• CD4007 IC (contains 3 NMOS and 3 PMOS transistors)
• Digital multimeter with nA measurement capability (Keithley 2400 or equivalent)
• Temperature-controlled chamber (range: 25°C to 70°C)
• DC power supplies:
◦ VDD: 0-5V (±0.1V accuracy)
◦ VGS: 0-32V (±0.01V accuracy)
• Precision potentiometers:
◦ R1: 10kΩ (±1% tolerance)
◦ R2: 10kΩ (±1% tolerance)

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• Breadboard and shielded cables

• Temperature sensor (PT100 or equivalent)

2. Theoretical Background

2.1 Subthreshold Current Equation

The drain current in subthreshold region is given by:

ID = ID0 × exp((VGS - VT)/(nVT)) × (1 - exp(-VDS/VT))

Where:

• ID0 = μ0Cox(W/L)(kT/q)²
• n = 1 + (Cd/Cox) ≈ 1.2-2.5
• VT = kT/q ≈ 26mV at 300K

2.2 Temperature Dependence

Key temperature relationships:

1. Threshold voltage: VT(T) = VT(T0) - αT(T-T0) where αT ≈ 0.5-3 mV/K

2. Mobility temperature dependence: μ(T) = μ(T0)(T/T0)^(-m) where m ≈ 1.5-2.0

2.3 Expected Parameter Ranges

Parameter Typical Range Units

VT 0.6 - 1.2 V

S 60 - 100 mV/decade

IOFF 1 - 100 pA

n 1.2 - 2.5 -

DIBL 20 - 100 mV/V

3. Experimental Setup

3.1 Detailed Circuit Configuration

VDD (5V)
|

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R1 (10kΩ)
|
|--[Ammeter]--+
| |
VGS o--| D
| | NMOS |
R2 G |
| | |
| S |
| | |
GND------------+

3.2 Equipment Connections

1. Power Supply Connections:

◦ VDD: Connect to top of R1

◦ VGS: Connect through R2 to gate
◦ Ground: Common ground point

2. Measurement Setup:

◦ Ammeter: In series with drain

◦ Voltmeter 1: Across gate-source
◦ Voltmeter 2: Across drain-source

4. Detailed Procedures

Part I: Basic Characterization

1. Initial Setup

◦ Set VDD = 5V
◦ Connect circuit as shown
◦ Verify all connections
◦ Set temperature to 25°C

2. VGS Sweep Procedure a. Set VDS = 50mV b. Start with VGS = 0V c. Increase VGS in steps:

◦ 0V to 0.3V: 50mV steps

◦ 0.3V to 0.9V: 25mV steps
◦ 0.9V to VT: 50mV steps d. Record ID for each point

Expected Results Table:

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VGS (V) ID (nA) log(ID)

0.0 0.1-1.0 -10 to -9

0.2 1-10 -9 to -8

0.4 10-100 -8 to -7

0.6 100-1000 -7 to -6

0.8 1000-10000 -6 to -5

Part II: Temperature Characterization

1. Setup Temperature Chamber

◦ Verify temperature sensor calibration

◦ Allow 15 minutes for stabilization
◦ Record ambient temperature

2. Temperature Sweep a. Set VDS = 1V b. Measure at temperatures:

◦ T1 = 25°C (room temp)

◦ T2 = 40°C
◦ T3 = 60°C c. Wait 10 minutes between measurements

Expected Temperature Results:

Temp (°C) VT (V) S (mV/dec) IOFF (pA)

25 1.0 65 10

40 0.95 70 50

60 0.90 75 200

Part III: Drain Voltage Effects

1. DIBL Measurement a. Select VGS values:
◦ VGS1 = 0.5V
◦ VGS2 = 0.7V
◦ VGS3 = 0.9V b. Sweep VDS: 0V to 1V (100mV steps)

Expected DIBL Results:

VDS (V) ID (nA) @ VGS=0.5V ID (nA) @ VGS=0.7V ID (nA) @ VGS=0.9V

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VDS (V) ID (nA) @ VGS=0.5V ID (nA) @ VGS=0.7V ID (nA) @ VGS=0.9V

0.1 1-10 10-100 100-1000

0.5 5-50 50-500 500-5000

1.0 10-100 100-1000 1000-10000

5. Safety Protocols

5.1 Electrical Safety

1. Maximum Ratings:

◦ VDS(max) = 20V
◦ VGS(max) = ±15V
◦ ID(max) = 10mA
◦ Power dissipation = 100mW

2. ESD Protection:

◦ Use grounded wrist strap

◦ Handle IC with proper tools
◦ Keep devices in conductive foam

5.2 Temperature Chamber Safety

1. Maximum temperature: 70°C
2. Minimum temperature: 20°C
3. Temperature ramp rate: ≤5°C/min
4. Safety features:
◦ Thermal cutoff
◦ Emergency stop button
◦ Over-temperature protection

6. Analysis Methods

6.1 Parameter Extraction

1. Subthreshold Swing:

◦ Plot log(ID) vs VGS

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◦ Calculate slope in linear region

◦ S = 1/slope

2. Threshold Voltage:

◦ Use constant current method

◦ ID(threshold) = 100nA × W/L

3. DIBL Coefficient:

◦ Plot VT vs VDS
◦ DIBL = |∂VT/∂VDS|

6.2 Temperature Analysis

1. Calculate activation energy:

◦ Plot ln(ID) vs 1/kT

◦ EA = -slope × k

2. Extract temperature coefficients:

◦ Plot VT vs T
◦ Calculate αT = -∂VT/∂T

7. Report Requirements
1. Raw Data Tables
2. Analyzed Parameters
3. Error Analysis
4. Discussion of Results
5. Comparison with Theory

Expected Final Parameters

Parameter Expected Value Acceptable Range

VT 1.0V ±0.2V

S 70mV/dec ±10mV/dec

n 1.5 ±0.3

DIBL 50mV/V ±20mV/V

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Parameter Expected Value Acceptable Range

EA 0.3eV ±0.1eV

8. Expected Graphical Results

8.1 Subthreshold Characteristics

A. Log(ID) vs VGS Plot

Expected characteristics:

log(ID)
↑
| Strong
| Inversion
| /
| / ~60mV/decade
| / slope
| /
| / Subthreshold
| / Region
| /
| /
| /
|/
+-----------------> VGS
0 VT (≈1V)

Key Features:

1. Linear region in semi-log plot below VT

2. Slope = 1/S ≈ 1/(70mV/decade) at 25°C
3. Clear transition at VT
4. Off-state current floor at ~10⁻¹² A

B. Temperature Dependence

Expected Plot Features:

log(ID)
↑ 70°C
| / 50°C
| / / 30°C
| / / /

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|/ / / ~10mV/decade
|/ / per °C change
|//
|/
+-----------------> VGS

Characteristic Points:

Temperature Swing (mV/dec) VT (V)

30°C 65 0.98

50°C 75 0.93

70°C 85 0.88

C. DIBL Effect Plot

ID (μA)
↑
| VGS = 0.9V
| _________
| /
| /
| / VGS = 0.7V
|/ _________
| /
|/ VGS = 0.5V
| _________
|/
+-----------------> VDS
0 0.5V 1.0V

Expected DIBL Characteristics:

1. Early saturation (VDS ≈ 4kT/q)

2. DIBL coefficient ≈ 50mV/V
3. Increased effect at higher temperatures

8.2 Parameter Extraction Plots

A. Threshold Voltage Temperature Dependence

VT (V)
1.0 +
|\.
0.9 | \.

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| \.
0.8 | \.
| \.
+----------+----> T(°C)
25 50 75

Expected slope: -2mV/°C

B. Subthreshold Swing Temperature Dependence

S (mV/dec)
90 + /
| /
80 | /
| /
70 | /
| /
60 +
+----------+----> T(°C)
25 50 75

Expected relationship: S ∝ T

8.3 Mobility Analysis

A. Effective Mobility vs Gate Voltage

μeff (cm²/V·s)
↑
|\.
| \.
| \.
| \.
| \.
+----------+----> VGS
0 VT 2VT

Expected Features:

1. Peak mobility near VT

2. Degradation at higher VGS
3. Temperature dependence: μ ∝ T⁻¹·⁵

B. Temperature Coefficient Plot

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ln(ID)
↑
| 30°C
| / 50°C
| / / 70°C
| / /
| / /
|/ /
| /
| /
+-----------------> 1/kT

Expected activation energy:

• EA ≈ 0.3-0.4 eV in subthreshold
• EA ≈ 0.1-0.2 eV in strong inversion

8.4 Important Graph Features to Verify

1. Smooth continuous curves without abrupt changes
2. Expected slopes in linear regions
3. Proper temperature ordering of curves
4. Clear saturation behavior
5. Exponential relationships appear linear in semi-log plots
6. No measurement artifacts or noise spikes
7. Proper intersection points at characteristic voltages

9. Detailed Graph Analysis and Observations

9.1 Subthreshold Characteristics Analysis

A. Log(ID) vs VGS Analysis

1. Region-wise Behavior:

◦ Off-state (VGS < 0.3V):

▪ Nearly constant current (~1-10pA)

▪ Limited by junction leakage
▪ Weak temperature dependence

◦ Subthreshold Region (0.3V < VGS < VT):

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▪ Exponential current increase

▪ Expected slope: 60-80 mV/decade
▪ Highly uniform line in semi-log plot

◦ Transition Region (VGS ≈ VT):

▪ Gradual curve bending

▪ Transition width ≈ 100mV
▪ Key region for VT extraction

◦ Strong Inversion (VGS > VT):

▪ Quadratic current increase

▪ Mobility degradation visible
▪ Power-law relationship

2. Key Observation Points:

Region Expected ID Range Slope Characteristic

Off-state 1-10 pA Near zero

Subthreshold 10 pA - 1 μA 60-80 mV/decade

Transition 1-10 μA Changing

Strong Inversion >10 μA Quadratic

B. Temperature Effects Analysis

1. Vertical Shift Characteristics:

◦ Each 10°C increase typically results in:

▪ 2x-3x increase in off-state current
▪ ~8% reduction in mobility
▪ ~20mV reduction in VT

2. Slope Changes:

Temperature Expected Swing Slope Change

30°C 65 mV/dec Reference

50°C 75 mV/dec +15%

70°C 85 mV/dec +30%

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3. Critical Observations:

◦ Parallel shifts in subthreshold region

◦ Convergence point at strong inversion
◦ Increased leakage at higher temperatures
◦ Maintained exponential behavior

C. DIBL Effect Analysis

1. VDS Dependence:

VDS Range Expected Behavior Key Features

0-0.1V Linear Ohmic region

0.1-0.3V Transition Channel pinch-off

>0.3V Saturation Current leveling

2. Curve Characteristics:

◦ Low VGS (0.5V):

▪ Gentle saturation
▪ Lower DIBL effect
▪ More temperature sensitive

◦ Medium VGS (0.7V):

▪ Moderate saturation
▪ Visible DIBL effect
▪ Standard behavior

◦ High VGS (0.9V):

▪ Sharp saturation
▪ Strong DIBL effect
▪ Less temperature sensitive

9.2 Parameter Extraction Analysis

A. VT Temperature Plot

1. Linear Fit Analysis:

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VT(T) = VT(T0) - αT(T-T0)

Expected Parameters:

◦ VT(T0) ≈ 1.0V at 25°C

◦ αT ≈ 2mV/°C
◦ R² should exceed 0.99

2. Key Observation Points:

Temperature Expected VT Tolerance

25°C 1.00V ±0.05V

50°C 0.95V ±0.05V

75°C 0.90V ±0.05V

B. Swing Temperature Analysis

1. Expected Relationship:

S(T) = S0(T/T0)

Where:

◦ S0 ≈ 60mV/dec at 300K
◦ Linear increase with temperature
◦ Slope ≈ 0.2mV/dec/°C

2. Quality Metrics:

◦ Linearity (R² > 0.98)

◦ Intercept at origin when plotted vs T/T0
◦ Maximum deviation < 5%

9.3 Advanced Analysis Features

A. Activation Energy Extraction

1. Arrhenius Plot Analysis:

ln(ID) vs 1/kT

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Expected Features:

◦ Linear regions with different slopes

◦ Slope proportional to EA
◦ Intersection points indicate mechanism changes

2. Extraction Points:

Region Expected EA Physical Meaning

Subthreshold 0.3-0.4 eV Band gap dependent

Strong Inversion 0.1-0.2 eV Mobility limited

B. Mobility Degradation Analysis

1. Effective Mobility Plot:

◦ Peak value near VT

◦ Power-law decrease above VT
◦ Temperature dependence follows T^(-1.5)

2. Degradation Parameters:

VGS/VT Mobility Reduction Mechanism

1.0 0% (reference) -

1.5 ~20% Surface roughness

2.0 ~40% Phonon scattering

9.4 Common Issues and Solutions

1. Measurement Artifacts:

◦ Noise spikes: Use longer integration time

◦ Oscillations: Check cable shielding
◦ Step discontinuities: Improve contact resistance

2. Temperature Effects:

◦ Thermal equilibrium: Wait 15 minutes after T change

◦ Self-heating: Limit maximum current
◦ Package effects: Consider thermal resistance

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3. Data Quality Checks:

◦ Subthreshold slope continuity

◦ Temperature ordering preservation
◦ Reasonable parameter ranges
◦ Smooth transitions between regions

References
1. Taur, Y., & Ning, T. H. (2013). Fundamentals of Modern VLSI Devices
2. Schroder, D. K. (2015). Semiconductor Material and Device Characterization
3. Tsividis, Y. (2011). Operation and Modeling of the MOS Transistor

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