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DV Courses Structure

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35 views7 pages

DV Courses Structure

This is related to dv courses.

Uploaded by

Surya S1802
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DIGITAL ELECTRONICS

Number systems
o Decimal , Binary, Hexa Decimal, Octal
o Boolean Algebra properties and functions
o Digital logic Gates
o Integrated circuits
o Mapping
o POS and SOP

Combinational Logic

o Combinational circuits
o Adder – Subtractor
o Half and Full adders
o Subtractors
o Multipliers
o Encoder and Decoders
o Multiplexers

Sequential Logic

o Sequential circuits
o Latches
o Flip flops
o Synchronous and asynchronous circuits
o Clocked sequential circuits
o Race free state assignment
Registers and Counters

o Shift registers
o Serial transfer and addition
o Binary counter
o Ripple counter
o Up- down counter
o Ring counter

Memory and PLA


VERILOG LANGUAGE

Introduction
Verilog language basics
Verilog constructs
o Data types
o registers, nets
o Vectors, Array
o Operators

Task and functions


Modules and ports
Assignments
o Continuous assignments
o Procedural assignments

Modeling

o Data Flow modeling


o Behavioral modelling
• Overview
• Procedural assignments
• Conditional statements
• Blocking statements
• fork join
o Gate level modeling
o Switch level modeling
FSM
Compiler Directives
Verilog timing regions
compiler directives
system task usage: $display, $monitor, $strobe
SYSTEM VERILOG LANGUAUGE CONSTRUCTS

▪ SV Introduction
▪ Operators, data types & Arrays
▪ Procedural statements
▪ Tasks and functions
▪ Process
o Fork_join
o Fork_join any and Fork_join none

▪ Object Oriented Programming


o Basics of OOP – Class, Object, handle
o Class elements – Properties, methods
o Object copying
o Inheritance
o $cast – static and dynamic casting
o Encapsulation – Data hiding, local, protected, public
o Polymorphism – real life use cases
o Static properties and methods
o Scope resolution operator
▪ Constraints, Randomization
o Constraints format
o Constraints type – Simple, distribution, implication, if-else,
iterative, variable ordering, soft, unique
o Randomization in class, module
▪ Inter process synchronization (IPC)
o Semaphore
o Events and SV regions
o Virtual interface
o Clocking blocks
o Modport

▪ Assertions
o Assertion format
o SVA built in methods
o Operators
o Variable delays
▪ Functional and code coverage
o What is functional coverage?
o Code coverage
o Different types of code coverage
▪ DPI
▪ Configuration libraries, Packages
▪ Functional Verification overview
o Test bench architecture & components
o Test bench development: Modularity, Reusability
o Understanding Functional Verification flow
▪ System Verilog Course overview
o System Verilog language features
o Verilog for TB development
o Verilog Language constructs and shortcomings
UVM CONSTRUCTS

• Introduction to UVM & Need for a methodology?


• UVM evolution
o OVM, AVM, RVM, NVM, eRM
• OOP basics
• UVM Test bench Hierarchy Block diagram
• Sequences, Sequencers
o Default sequence
o Virtual sequences
o p_sequencer
o m_sequencer
o Virtual Sequencer
• Configuration DB, Resource DB
o Detailed usage of both data bases.
o How config_db is related to resource_db?
o Using config_db to change the testbench architecture.
• UVM Phases
• Different testbench component coding
o Monitor
o Driver
o Agent
o Coverage
o Scoreboard
• UVM Callbacks
• TLM ports

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