DATA SHEET

4G bits GDDR5 SGRAM

EDW4032BABG (128M words x 32 bits)
Specifications Features
• Density: 4G bits • x32/x16 mode configuration set at power-up with
• Organization EDC pin
— 8Mbit x 32 I/O x 16 banks • Single ended interface for data, address and command
— 16Mbit x 16 I/O x 16 banks • Quarter data-rate differential clock inputs CK_t, CK_c
• Package for address and commands
— 170-ball FBGA • Two half data-rate differential clock inputs WCK_t,
WCK_c, each associated with two data bytes (DQ,
— Lead-free (RoHS compliant) and Halogen-free DBI_n, EDC)
• Power supply: • Double Data Rate (DDR) data (WCK)
— VDD: 1.6V/1.5V ± 3% and 1.35V ± 3% • Single Data Rate (SDR) command (CK)
— VDDQ: 1.6V/1.5V ± 3% and 1.35V ± 3% • Double Data Rate (DDR) addressing (CK)
• Data rate: 7.0Gbps/6.0Gbps (max.) • Write data mask function via address bus
• 16 internal banks (single/double byte mask)
• Four bank groups for tCCDL = 3tCK • Data Bus Inversion (DBI) and Address Bus Inversion
• 8n prefetch architecture: 256 bit per array Read or (ABI)
Write access for x32; 128 bit for x16 • Input/output PLL on/off mode
• Burst length (BL): 8 only • Duty cycle corrector (DCC) for data clock (WCK)
• Programmable CAS latency: 6 to 22 • Address training: address input monitoring via DQ pins
• Programmable Write latency: 3 to 7 • WCK2CK clock training: phase information via EDC
• Programmable CRC READ latency: 1 to 3 pins
• Programmable CRC WRITE latency: 8 to 14 • Data read and write training via Read FIFO (FIFO
• Programmable EDC hold pattern for CDR depth = 6)
• Precharge: auto precharge option for each burst • Read FIFO pattern preload by LDFF command
access • Direct write data load to Read FIFO by WRTR
• Refresh: auto-refresh, self-refresh command
• Refresh cycles: 16384 cycles/32ms • Consecutive read of Read FIFO by RDTR command
• Interface: Pseudo open drain (POD-15) • Read/Write data transmission integrity secured by
• On-die termination (ODT): nom. values of 60Ω or 120Ω cyclic redundancy check (CRC–8)
• Pseudo open drain (POD-15) compatible outputs • Read/Write EDC on/off mode
— 40Ω pulldown • DQ Preamble for Read on/off mode
— 60Ω pullup • Low Power modes
• ODT and output driver strength auto-calibration with • RDQS mode on EDC pin
external resistor ZQ pin (120Ω) • On-chip temperature sensor with read-out
• Programmable termination and driver strength offsets • Automatic temperature sensor controlled self-refresh
• Selectable external or internal VREF for data inputs; rate
programmable offsets for internal VREF • Digital RAS lockout
• Separate external VREF for address / command inputs • Vendor ID, FIFO depth and Density info fields for
• Operating case temperature range identification
— TC = 0°C to +95°C • Mirror function with MF pin
• Boundary Scan function with SEN pin

Document No. E2080E20 (Ver. 2.0)

Date Published November 2013 (K) Japan
Printed in Japan
URL: http://www.elpida.com

©Elpida Memory, Inc. 2013

 EDW4032BABG
Ordering Information

Organization
Part number (words x bits) VDD, VDDQ Max. Data Rate Package

EDW4032BABG-60-F 128M x 32 1.5V / 1.35V 6.0Gbps / 5.0Gbps 170-ball FBGA

EDW4032BABG-70-F 1.6V / 1.35V 7.0Gbps / 5.0Gbps

Part Number
E D W 40 32 B A BG - 70 - F
Elpida Memory

Type Environment Code

D: Packaged Device F: Lead Free (RoHS compliant)
and Halogen Free
Product Family
W: GDDR5 SGRAM Speed
60: 6.0Gbps
70: 7.0Gbps
Density/Bank
40: 4Gb/16-bank

Organization Package
32: x32 BG: FBGA

Power Supply, Interface Revision

B: VDD = 1.6V/1.5V

Data Sheet E2080E20 (Ver. 2.0)

2
 EDW4032BABG
Pin Configuration

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Data Sheet E2080E20 (Ver. 2.0)

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Signal Function Signal Function

CK_t, CK_c Clock ZQ Impedance Reference
WCK01_t, WCK01_c,
Data Clocks RESET_n Reset
WCK23_t, WCK23_c
CKE_n Clock Enable MF Mirror Function
CS_n Chip Select SEN Scan Enable
RAS_n, CAS_n, WE_n Command inputs VREFC Reference voltage for command and address
BA0 - BA3 Bank Address inputs VREFD Reference voltage for DQ and DBI_n
A0 - A13 Address inputs VDDQ I/O power
DQ0 - DQ31 Data Input/Output VSSQ I/O ground
DBI0_n - DBI3_n Data bus inversion VDD Power supply
EDC0 - EDC3 Error Detection Code VSS Ground
ABI_n Address bus inversion NC Not connected

Data Sheet E2080E20 (Ver. 2.0)

4
 EDW4032BABG
1. Configuration
The Elpida GDDR5 SGRAM is a high speed dynamic random-access memory designed for applications requiring
high bandwidth. It contains 4,294,967,296 bits and is internally configured as a 16-bank DRAM.
The GDDR5 SGRAM uses a 8n prefetch architecture and DDR interface to achieve high-speed operation. The
device can be configured to operate in x32 mode or x16 (clamshell) mode. The mode is detected during device
initialization. The GDDR5 interface transfers two 32 bit wide data words per WCK clock cycle to/from the I/O pins.
Corresponding to the 8n prefetch a single write or read access consists of a 256 bit wide, two CK clock cycle data
transfer at the internal memory core and eight corresponding 32 bit wide one-half WCK clock cycle data transfers
at the I/O pins.
The GDDR5 SGRAM operates from a differential clock CK_t and CK_c. Commands are registered at every rising
edge of CK_t. Addresses are registered at every rising edge of CK_t and every rising edge of CK_c.
GDDR5 replaces the pulsed strobes (WDQS & RDQS) used in previous DRAMs such as GDDR4 with a free running
differential forwarded clock (WCK_t, WCK_c) with both input and output data registered and driven respectively at
both edges of the forwarded WCK.
Read and write accesses to the GDDR5 SGRAM are burst oriented; an access starts at a selected location and
continues for a total of eight data words. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command and
the next rising CK_c edge are used to select the bank and the row to be accessed. The address bits registered
coincident with the READ or WRITE command and the next rising CK_c edge are used to select the bank and the
column location for the burst access.

Data Sheet E2080E20 (Ver. 2.0)

5
 EDW4032BABG
1.1 Signal Description

Table 1: Signal Description

Signal Type Detailed Function

Clock: CK_t and CK_c are differential clock inputs. Command inputs are latched on the rising
CK_t, CK_c Input edge of CK_t. Address inputs are latched on the rising edge of CK_t and the rising edge of
CK_c. All latencies are referenced to CK_t. CK_t and CK_c are externally terminated.
WCK01_t, Data Clocks: WCK_t and WCK_c are differential clocks used for WRITE data capture and
WCK01_c, READ data output. WCK01_t,WCK01_c is associated with DQ0-DQ15, DBI0_n, DBI1_n,
Input
WCK23_t, EDC0 and EDC1. WCK23_t,WCK23_c is associated with DQ16-DQ31, DBI2_n, DBI3_n,
WCK23_c EDC2 and EDC3. WCK clocks operate at nominally twice the CK clock frequency.
Clock Enable: CKE_n low activates and CKE_n high deactivates internal clock, device input
buffers and output drivers. Taking CKE_n high provides Precharge Power-Down and Self-
Refresh operations (all banks idle), or Active Power-Down (row active in any bank). CKE_n is
synchronous for Power-Down entry and exit and for Self-Refresh entry. CKE_n must be
CKE_n Input maintained low throughout READ and WRITE accesses. Input buffers excluding CK_t, CK_c,
CKE_n, WCK01_t, WCK01_c, WCK23_t, WCK23_c are disabled during Power-Down. Input
buffers excluding CKE_n are disabled during Self-Refresh. The value of CKE_n latched at
power-up with RESET_n going high determines the termination value of the address and
command inputs.
Chip Select: CS_n low enables, and CS_n high disables the command decoder. All commands
are masked when CS_n is registered high, but internal command execution continues. CS_n
CS_n Input
provides for individual device selection on memory channels with multiple memory devices.
CS_n is considered part of the command code.
RAS_n, CAS_n, Command inputs: RAS_n, CAS_n and WE_n (along with CS_n) define the command to be
Input
WE_n entered.
Bank Address inputs: BA0-BA3 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied. BA0-BA3 also determine which Mode Register is
BA0 - BA3 Input
accessed with a MODE REGISTER SET command. BA0-BA3 are sampled with the rising edge
of CK_t.
Address inputs: A0-A13 provide the row address for ACTIVE commands. A0-A5(A6) provide
the column address and A8 defines the auto precharge function for READ and WRITE
commands, to select one location out of the memory array in the respective bank. A8 sampled
during a PRECHARGE command determines whether the PRECHARGE applies to one bank
A0 - A13 Input
(A8 low, bank selected by BA0-BA3) or all banks (A8 high). The address inputs also provide
the op-code during an MODE REGISTER SET command, and the data bits during LDFF
commands. A8-A12 are sampled with the rising edge of CK _t and A0-A7,A13 are sampled
with the rising edge of CK_c.
DQ0 - DQ31 I/O Data Input/Output: 32 bit data bus
Data bus inversion: DBI0_n is associated with DQ0-DQ7, DBI1_n with DQ8-DQ15, DBI2_n
DBI0_n - DBI3_n I/O
with DQ16-DQ23, and DBI3_n with DQ24-DQ31.
Error Detection Code: The calculated CRC data is transmitted on these pins. In addition these
EDC0 - EDC3 Output pins drive a hold pattern when idle and can be used as an RDQS function. EDC0 is associated
with DQ0-DQ7, EDC1 with DQ8-DQ15, EDC2 with DQ16-DQ23, and EDC3 with DQ24-DQ31.
ABI_n Input Address bus inversion
ZQ - Impedance Reference: external reference pin for auto-calibration
Reset: VDDQ CMOS input. A full chip reset may be performed at any time by pulling RESET_n
RESET_n Input
low. With RESET_n low all ODTs are disabled.
MF Input Mirror Function: VDDQ CMOS input. Must be tied to Power or Ground.
SEN Input Scan Enable: VDDQ CMOS input. Must be tied to Ground when not in use.
VREFC Supply Reference voltage for command and address inputs.
VREFD Supply Reference voltage for DQ and DBI_n inputs.
VDDQ Supply Isolated power for the input and output buffers.
VSSQ Supply Isolated ground for the input and output buffers.
VDD Supply Power supply
VSS Supply Ground
NC - Not connected

Data Sheet E2080E20 (Ver. 2.0)

6
 EDW4032BABG
1.2 Mirror Function Mode

The GDDR5 SGRAM provides a mirror function (MF) pin to change the physical location of the command, address,
data and WCK pins assisting in routing devices back to back. The MF ball should be tied directly to VSSQ or VDDQ
depending on the control line orientation desired.
The pins affected by this Mirror Function mode are listed in Table 2.

Table 2: Ball Assignment with Mirror Function

Signal Signal Signal Signal

Ball MF=0 MF=1 Ball MF=0 MF=1 Ball MF=0 MF=1 Ball MF=0 MF=1
A2 DQ1 DQ25 A4 DQ0 DQ24 K5 A11 A6 A9 A1 G12 CS_n WE_n
B2 DQ3 DQ27 B4 DQ2 DQ26 P5 WCK23_c WCK01_c L12 WE_n CS_n
C2 EDC0 EDC3 D4 WCK01_t WCK23_t H10 BA3 A3 BA1 A5 A13 DQ9 DQ17
D2 DBI0_n DBI3_n E4 DQ4 DQ28 K10 BA1 A5 BA3 A3 B13 DQ11 DQ19
E2 DQ5 DQ29 F4 DQ6 DQ30 A11 DQ8 DQ16 C13 EDC1 EDC2
F2 DQ7 DQ31 H4 A10 A0 A8 A7 B11 DQ10 DQ18 D13 DBI1_n DBI2_n
M2 DQ31 DQ7 K4 A8 A7 A10 A0 E11 DQ12 DQ20 E13 DQ13 DQ21
N2 DQ29 DQ5 M4 DQ30 DQ6 F11 DQ14 DQ22 F13 DQ15 DQ23
P2 DBI3_n DBI0_n N4 DQ28 DQ4 H11 BA0 A2 BA2 A4 M13 DQ23 DQ15
R2 EDC3 EDC0 P4 WCK23_t WCK01_t K11 BA2 A4 BA0 A2 N13 DQ21 DQ13
T2 DQ27 DQ3 T4 DQ26 DQ2 M11 DQ22 DQ14 P13 DBI2_n DBI1_n
U2 DQ25 DQ1 U4 DQ24 DQ0 N11 DQ20 DQ12 R13 EDC2 EDC1
G3 RAS_n CAS_n D5 WCK01_c WCK23_c T11 DQ18 DQ10 T13 DQ19 DQ11
L3 CAS_n RAS_n H5 A9 A1 A11 A6 U11 DQ16 DQ8 U13 DQ17 DQ9
Functions within the GDDR5 SGRAM that refer to external signals are transparent with respect to Mirror Function
mode, meaning that the signal names shown in the respective functional description apply both to mirrored (MF=1)
and non-mirrored (MF=0) modes. The referenced package pin is determined by the Mirror Function mode the
devices is configured to.

1.3 Clamshell Mode Detection

The GDDR5 SGRAM can operate in a x32 mode or a x16 mode to allow a clamshell configuration with a point to
point connection on the high speed data signals. The disabled pins in x16 mode will be in Hi-Z state, non-terminating.
The x16 mode is detected at power-up on the pin at location C-13 which is EDC1 when configured to MF=0 and
EDC2 when configured to MF=1. For x16 mode this pin is tied to VSSQ; the pin is part of the two bytes that are
disabled in this mode and therefore not needed for EDC functionality. For x32 mode this pin is active and always
terminated to VDDQ in the system or by the controller. The configuration is set with RESET_n going high. Once the
configuration has been set, it cannot be changed during normal operation. Usually the configuration is fixed in the
system.

Table 3: Clamshell Mode and Mirror Function

Mode MF EDC1 (MF=0) or EDC2 (MF=1)
x16 non-mirrored VSSQ VSSQ
x32 non-mirrored VSSQ VDDQ (terminated by the system or controller)
x16 mirrored VDDQ VSSQ
x32 mirrored VDDQ VDDQ (terminated by the system or controller)

Data Sheet E2080E20 (Ver. 2.0)

7
 EDW4032BABG
Figure 1 shows examples of the board channels and topologies that are supported in GDDR5 in order to illustrate
the expected usage of x16 mode and the MF pin.

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Figure 1: Example GDDR5 PCB Layout Topologies

Data Sheet E2080E20 (Ver. 2.0)

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 EDW4032BABG
1.4 Clocking

The GDDR5 SGRAM operates from a differential clock CK_t and CK_c. Commands are registered at every rising
edge of CK_t. Addresses are registered at every rising edge of CK_t and every rising edge of CK_c.
GDDR5 uses a double data rate data interface and an 8n-prefetch architecture. The data interface uses two
differential forwarded clocks (WCK_t, WCK_c). DDR means that the data is registered at every rising edge of WCK_t
and rising edge of WCK_c. WCK_t and WCK_c are continuously running and operate at twice the frequency of the
command/address clock (CK_t, CK_c).

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Figure 2: GDDR5 Clocking and Interface Relationship

1.5 Addressing

The GDDR5 SGRAM uses a double data rate address scheme to reduce pins required on the GDDR5 SGRAM as
shown in Table 4. The addresses should be provided to the GDDR5 SGRAM in two parts; the first half is latched on
the rising edge of CK_t along with the command pins such as RAS_n, CAS_n and WE_n; the second half is latched
on the rising edge of CK_c.
The use of DDR addressing allows all address values to be latched in at the same rate as the SDR commands. All
addresses related to command access have been positioned for latching on the initial rising edge for faster
decoding.

Table 4: Address Pairs

Clock Edge Address Inputs
Rising CK_t BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8
Rising CK_c A3 A4 A5 A2 A13 A6 A0 A1 A7

Addressing schemes for x32 mode and x16 mode differ only in the number of valid column addresses, as shown in
Table 5.

Table 5: Addressing Scheme

128M x 32 256M x 16
Row address A0-A13 A0-A13
Column address A0-A5 A0-A6
Bank address BA0-BA3 BA0-BA3
Autoprecharge A8 A8
Page size 2 KB 2 KB
Refresh 16K/32ms 16K/32ms
Refresh period 1.9 µs 1.9 µs

Data Sheet E2080E20 (Ver. 2.0)

9
 EDW4032BABG
1.6 Commands

Table 6: Command Truth Table

CKE_n CKE_n CS RAS CAS WE BA3- A12- A6-A7, A0-A5

Operation Code (n-1) (n) _n _n _n _n BA0 A13 A11 A10 A8 A9 (A6) Notes
DESELECT DESEL L X H X X X X X X X X X X 2,8
NO OPERATION
NOP L X L H H H X X X X X X X 2,8
(NOP)
MODE REGISTER
MRS L L L L L L MRA X OPCODE 2,3
SET
ACTIVATE ACT L L L L H H BA RA 2,4
READ RD L L L H L H BA X L L L X CA 2,5,9
READ with
RDA L L L H L H BA X L L H X CA 2,5
Autoprecharge
LOAD FIFO LDFF L L L H L H BST X H L L DATA 2,7
READ TRAINING RDTR L L L H L H X X H H L X X 2
WRITE without Mask WR L L L H L L BA X L L L X CA 2,5
WRITE without Mask
WRA L L L H L L BA X L L H X CA 2,5
with Autoprecharge
WRITE with Single
WSM L L L H L L BA X L H L X CA 2,5
Byte Mask
WRITE with
Autoprecharge, WSMA L L L H L L BA X L H H X CA 2,5
Single Byte Mask
WRITE with Double
WDM L L L H L L BA X H L L X CA 2,5
Byte Mask
WRITE with
Autoprecharge, WDMA L L L H L L BA X H L H X CA 2,5
Double Byte Mask
WRITE TRAINING WRTR L L L H L L X X H H L X X 2
PRECHARGE PRE L L L L H L BA X X X L X X 2
PRECHARGE ALL PREALL L L L L H L X X X X H X X 2
REFRESH REF L L L L L H X X X X X X X 6
POWER-DOWN H X X X
PDE L H X X X X X X X
ENTRY L H H H
POWER-DOWN H X X X
PDX H L X X X X X X X
EXIT L H H H
SELF-REFRESH
SRE L H L L L H X X X X X X X 6
ENTRY
SELF-REFRESH H X X X
SRX H L X X X X X X X
EXIT L H H H
Notes: 1. H = logic high level; L = logic low level; X = Don’t Care. Signal may be H or L, but not floating.
2. Addresses shown are logical addresses; physical addresses are inverted when address bus inversion (ABI) is
activated and ABI_n=L.
3. BA0-BA3 provide the Mode Register address (MRA), A0-A11 the opcode to be loaded.
4. BA0-BA3 provide the bank address (BA), A0-A13 provide the row address (RA).
5. BA0-BA3 provide the bank address, A0-A5 (A6) provide the column address (CA); no sub-word addressing within a
burst of 8.
6. This command is REFRESH when CKE_n(n) = L, and SELF-REFRESH ENTRY when CKE_n(n) is H.
7. BA0-BA2 select burst location (BST) and A0-A9, BA3 provide the data.
8. DESELECT and NO OPERATION are functionally interchangeable.
9. In address training mode READ is decoded from the command pins only with RAS_n = H, CAS_n = L, WE_n= H.

Data Sheet E2080E20 (Ver. 2.0)

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 EDW4032BABG
2. Electrical Characteristics
Table 7: Absolute Maximum Ratings
Parameter Symbol Min. Max. Unit
Voltage on VDD supply relative to VSS VDD -0.5 2.0 V
Voltage on VDDQ supply relative to VSSQ VDDQ -0.5 2.0 V
Voltage on VREF and inputs relative to VSS VIN -0.5 2.0 V
Voltage on I/O pins relative to VSS VOUT -0.5 2.0 V
Storage Temperature TSTG -55 +150 °C
Short Circuit output current IOUT — 50 mA
Caution: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only, and functional operation of the device at these
or any other conditions above those indicated in the operational sections of these specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

2.1 Operating Conditions

Table 8: Operating Temperature Range

Parameter Symbol Min Max Unit

Operating temperature TC 0 +95 °C
Notes: 1. Operating temperature TC is the case surface temperature on the center / top side of the DRAM. It specifies the
temperature where all DRAM specifications will be supported.
2. For measurement conditions, please refer to JEDEC document JESD51-2.

Table 9: Input Capacitance

Parameter Symbol Min Max Unit Notes

Delta Input/Output Capacitance: DQ, DBI_n, EDC DCIO — 0.3 pF 1,2
Delta Input Capacitance: Command and Address DCI1 — 0.2 pF 1,3,6
Delta Input Capacitance: CK_t, CK_c DCI2 — 0.1 pF 1,4
Delta Input Capacitance: WCK_t, WCK_c DCI3 — 0.1 pF 1,5
Input/Output Capacitance: DQ, DBI_n, EDC CIO 0.9 1.3 pF 1
Input Capacitance: Command and Address CI1 1.0 1.3 pF 1,6
Input Capacitance: CK_t, CK_c CI2 1.1 1.3 pF 1
Input Capacitance: WCK_t, WCK_c CI3 0.9 1.1 pF 1
Notes: 1. The capacitance is measured according to JEP147 (“PROCEDURE FOR MEASURING INPUT CAPACITANCE
USING A VECTOR NETWORK ANALYZER (VNA)”) with VDD, VDDQ, VSS, VSSQ applied and all other pins floating
(except the pin under test). VDD=VDDQ=1.5V and on-die termination off.
2. DCIO = CIO.MAX - CIO.MIN
3. DCI1 = CI1.MAX - CI1.MIN
4. DCI2 = Absolute value of C CK_t - C CK_c
5. DCI3 = Absolute value of C WCK_t - C WCK_c
6. DCI1 and CI1 apply to RAS_n, CAS_n, WE_n, CS_n, CKE_n, ABI_n, BA3/A3, BA2/A4, BA1/A5, BA0/A2, A12/A13,
A11/A6, A10/A0, A9/A1, A8/A7

Data Sheet E2080E20 (Ver. 2.0)

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 EDW4032BABG
GDDR5 SGRAMs are designed for 1.5V typical voltage supplies. This GDDR5 SGRAM does also support 1.35V
typical voltage supplies. The interface of GDDR5 with 1.5V VDDQ will follow the POD15 specification (JESD8-20A).
The interface of GDDR5 with 1.35V VDDQ will follow the POD135 specification Class B (JESD8-21). I/O levels are
given here for reference only. All AC and DC values are measured at the ball.

Table 10: DC Operating Conditions

POD15 POD135
Parameter Symbol min. typ. max. min. typ. max. Unit Notes
Device supply voltage (-70) VDD 1.552 1.6 1.648 1.3095 1.35 1.3905 V 1
Device supply voltage (-60) VDD 1.455 1.5 1.545 1.3095 1.35 1.3905 V 1
I/O Supply voltage (-70) VDDQ 1.552 1.6 1.648 1.3095 1.35 1.3905 V 1
I/O Supply voltage (-60) VDDQ 1.455 1.5 1.545 1.3095 1.35 1.3905 V 1
0.69 * 0.71 * 0.69 * 0.71 *
Reference voltage for DQ and DBI_n pins VREFD — — V 2,3
VDDQ VDDQ VDDQ VDDQ
0.49 * 0.51 * 0.49 * 0.51 *
Reference voltage for DQ and DBI_n pins VREFD2 — — V 2,3,4
VDDQ VDDQ VDDQ VDDQ
External reference voltage for address and 0.69 * 0.71 * 0.69 * 0.71 *
VREFC — — V 5
command VDDQ VDDQ VDDQ VDDQ
DC input logic high voltage for address and VREFC VREFC
VIHA(DC) — — — — V
command inputs + 0.15 + 0.135
DC input logic low voltage for address and VREFC VREFC
VILA(DC) — — — — V
command inputs - 0.15 - 0.135
DC input logic high voltage for DQ, DBI_n VREFD VREFD
VIHD(DC) — — — — V
inputs with VREFD + 0.10 + 0.09
DC input logic low voltage for DQ, DBI_n VREFD VREFD
VILD(DC) — — — — V
inputs with VREFD - 0.10 - 0.09
DC input logic high voltage for DQ, DBI_n VREFD2 VREFD2
VIHD2(DC) — — — — V
inputs with VREFD2 + 0.30 + 0.27
DC input logic low voltage for DQ, DBI_n VREFD2 VREFD2
VILD2(DC) — — — — V
inputs with VREFD2 - 0.30 - 0.27
Input logic high voltage for RESET_n, SEN, VDDQ VDDQ
VIHR — — — — V
MF - 0.5 - 0.5
Input logic low voltage for RESET_n, SEN,
VILR — — 0.3 — — 0.3 V
MF
Input logic high voltage for EDC1/2 VDDQ VDDQ
VIHX — — — — V 8
(x16 mode detect) - 0.3 - 0.3
Input logic low voltage for EDC1/2
VILX — — 0.3 — — 0.3 V 8
(x16 mode detect)
Input leakage current
(any input 0V ≤ VIN ≤ VDDQ; all other pins IL -5 — +5 -5 — +5 µA 9
not under test = 0V)
Output leakage current
IOZ -5 — +5 -5 — +5 µA 10
(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)
Output logic low voltage VOL(DC) — — 0.62 — — 0.56 V
External resistor value ZQ 115 120 125 115 120 125 Ω
Notes: 1. GDDR5 SGRAMs are designed to tolerate PCB designs with separate VDDQ and VDD power regulators.
2. AC noise in the system is estimated at 50 mV peak-to-peak for the purpose of DRAM design.
3. Source of reference voltage and control of Reference voltage for DQ and DBI_n pins is determined by VREFD, Half
VREFD and VREFD Offset Mode Registers.
4. VREFD Offsets are not supported with VREFD2.
5. External VREFC is to be provided by the controller as there is no alternative supply.
6. DB, DBI_n input slew rate must be greater than or equal to 3V/ns for POD15 and 2.7V/ns for POD135. The slew rate
is measured between VREFD crossing and VIHD(AC) or VILD(AC) or VREFD2 crossing and VIHD2(AC) or
VILD2(AC).
7. ADD/CMD input slew rate must be greater than or equal to 3V/ns for POD15 and 2.7V/ns for POD135. The slew rate
is measured between VREFC crossing and VIHA(AC) or VILA(AC).

Data Sheet E2080E20 (Ver. 2.0)

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 EDW4032BABG
8. VIHX and VILX define the input voltage levels for the receiver that detects x32 mode or x16 mode with RESET_n going high.
9. IL is measured with ODT off. Any input 0V ≤ VIN ≤ VDDQ; all other pins not under test = 0V.
10. IOZ is measured with DQs disabled; 0V ≤ VOUT ≤ VDDQ.

Table 11: AC Operating Conditions

POD15 POD135
Parameter Symbol min. typ. max. min. typ. max. Unit Notes
AC input logic high voltage for address and VREFC VREFC
VIHA(AC) — — — — V
command inputs + 0.20 + 0.18
AC input logic low voltage for address and VREFC VREFC
VILA(AC) — — — — V
command inputs - 0.20 - 0.18
AC input logic high voltage for DQ, DBI_n VREFD VREFD
VIHD(AC) — — — — V
inputs with VREFD + 0.15 + 0.135
AC input logic low voltage for DQ, DBI_n VREFD VREFD
VILD(AC) — — — — V
inputs with VREFD - 0.15 - 0.135
AC input logic high voltage for DQ, DBI_n VREFD2 VREFD2
VIHD2(AC) — — — — V
inputs with VREFD2 + 0.40 + 0.36
AC input logic low voltage for DQ, DBI_n VREFD2 VREFD2
VILD2(AC) — — — — V
inputs with VREFD2 - 0.40 - 0.36
Note: For optimum performance it is recommended that signal swings are larger than shown in the table.

Table 12: Clock Input Operating Conditions

POD15 POD135
Parameter Symbol min. max. min. max. Unit Notes
VREFC VREFC VREFC VREFC
Clock input mid-point voltage: CK_t, CK_c VMP(DC) V 1,6
- 0.1 + 0.1 - 0.1 + 0.1
Clock input differential voltage: CK_t, CK_c VIDCK(DC) 0.22 — 0.198 — V 4,6
Clock input differential voltage: CK_t, CK_c VIDCK(AC) 0.40 — 0.36 — V 2,4,6
Clock input differential voltage: WCK_t,
VIDWCK(DC) 0.20 — 0.18 — V 5,7
WCK_c
Clock input differential voltage: WCK_t,
VIDWCK(AC) 0.30 — 0.27 — V 2,5,7
WCK_c
Clock input voltage level for CK_t, CK_c, VDDQ VDDQ
VIN -0.3 -0.3 V
WCK_t, WCK_c single ended inputs + 0.3 + 0.3
CK_t, CK_c single ended slew rate CKslew 3 — 2.7 — V/ns 9
WCK_t, WCK_c single ended slew rate WCKSlew 3 — 2.7 — V/ns 10
Clock input crossing point voltage: CK_t, VREFC VREFC VREFC VREFC
VIXCK(AC) V 2,3,6
CK_c - 0.12 + 0.12 - 0.108 + 0.108
Clock input crossing point voltage: VREFD VREFD VREFD VREFD 2,3,7,
VIXWCK(AC) V
WCK_t, WCK_c - 0.10 + 0.10 - 0.09 + 0.09 8
Notes: 1. This provides a minimum of 0.9V to a maximum of 1.2V, and is nominally 70% of VDDQ with POD15. If POD135, this
provides a minimum of 0.845V to a maximum of 1.045V, and is nominally 70% of VDDQ. DRAM timings relative to CK
cannot be guaranteed if these limits are exceeded.
2. For AC operations, all DC clock requirements must be satisfied as well.
3. The value of VIXCK and VIXWCK is expected to equal 70% VDDQ for the transmitting device and must track variations
in the DC level of the same.
4. VIDCK is the magnitude of the difference between the input level in CK_t and the input level on CK_c. The input
reference level for signals other than CK_t and CK_c is VREFC.
5. VIDWCK is the magnitude of the difference between the input level in WCK_t and the input level on WCK_c. The input
reference level for signals other than WCK_t and WCK_c is either VREFD, VREFD2 or the internal VREFD.
6. The CK_t and CK_c input reference level (for timing referenced to CK_t and CK_c) is the point at which CK_t and
CK_c cross. Please refer to the applicable timings in the AC timings table.
7. The WCK_t and WCK_c input reference level (for timing referenced to WCK_t and WCK_c) is the point at which
WCK_t and WCK_c cross. Please refer to the applicable timings in the AC Timings table.
8. VREFD is either VREFD, VREFD2 or the internal VREFD.
9. The slew rate is measured between VREFC crossing and VIXCK(AC).
10. The slew rate is measured between VREFD crossing and VIXWCK(AC).

Data Sheet E2080E20 (Ver. 2.0)

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 EDW4032BABG
3. Package Drawing
170-ball FBGA
Solder ball: Lead free (Sn-Ag-Cu)

Unit: mm

12.0 ± 0.1
0.2 S A
INDEX MARK
14.0 ± 0.1

0.2 S B

0.2 S
1.1 ± 0.1

0.12 S 0.35 ± 0.05

A
170-B0.45 ± 0.05 B0.15 M S A B
0.8

B
12.8

INDEX MARK

2.0 0.8

10.4

ECA-TS2-0327-02

Data Sheet E2080E20 (Ver. 2.0)

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 EDW4032BABG

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR MOS DEVICES

Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.

CME0107

Data Sheet E2080E20 (Ver. 2.0)

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 EDW4032BABG

The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.

No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Be aware that this product is for use in typical electronic equipment for general-purpose applications.
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, this product is not intended for use in the product in aerospace, aeronautics, nuclear power,
combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other
such application in which especially high quality and reliability is demanded or where its failure or
malfunction may directly threaten human life or cause risk of bodily injury. Customers are instructed to
contact Elpida Memory's sales office before using this product for such applications.

[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.

[Usage environment]
Usage in environments with special characteristics as listed below was not considered in the design.
Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in
environments with the special characteristics listed below.

Example:
1) Usage in liquids, including water, oils, chemicals and organic solvents.
2) Usage in exposure to direct sunlight or the outdoors, or in dusty places.
3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 ,
SO 2 , and NO x .
4) Usage in environments with static electricity, or strong electromagnetic waves or radiation.
5) Usage in places where dew forms.
6) Usage in environments with mechanical vibration, impact, or stress.
7) Usage near heating elements, igniters, or flammable items.

If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.

M01E1007

Data Sheet E2080E20 (Ver. 2.0)

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 EDW4032BABG
Revision History
Ver. Date Description
1.0 Jul. 2013 Initial version
2.0 Nov. 2013 Status changed from “Preliminary Data Sheet” to “Data Sheet”

Data Sheet E2080E20 (Ver. 2.0)

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