M29W400DT

M29W400DB
4 Mbit (512Kb x8 or 256Kb x16, Boot Block)
3V Supply Flash Memory

FEATURES SUMMARY
■ SUPPLY VOLTAGE Figure 1. Packages
– VCC = 2.7V to 3.6V for Program, Erase
and Read
■ ACCESS TIME: 45, 55, 70ns
■ PROGRAMMING TIME
– 10µs per Byte/Word typical
■ 11 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location) SO44 (M)
– 2 Parameter and 8 Main Blocks
■ PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program
algorithms
■ ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■ UNLOCK BYPASS PROGRAM COMMAND
TSOP48 (N)
– Faster Production/Batch Programming 12 x 20mm
■ TEMPORARY BLOCK UNPROTECTION
MODE
■ LOW POWER CONSUMPTION
– Standby and Automatic Standby
FBGA
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
TFBGA48 (ZA)
– Top Device Code M29W400DT: 00EEh
6 x 9mm
– Bottom Device Code M29W400D: 00EFh
■ PACKAGES
– Compliant with Lead-Free Soldering
Processes FBGA
– Lead-Free Versions

TFBGA48 (ZE)
6 x 8mm

June 2004 1/38

M29W400DT, M29W400DB

TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Input/Output or Address Input (DQ15A-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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 M29W400DT, M29W400DB

Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Block Protect and Chip Unprotect Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 15
Table 5. Commands, 16-bit mode, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12.Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13.Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15.Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16.SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline . . . . . . . . 26
Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data 26
Figure 17.TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline. . . . . . . . . 27
Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 27
Figure 18.TFBGA48 6x9mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline . . . . 28
Table 18. TFBGA48 6x9mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data. . 28

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M29W400DT, M29W400DB

Figure 19.TFBGA48 6x8mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline . . . . 29
Table 19. TFBGA48 6x8mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data. . 29

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

APPENDIX A.BLOCK ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 21. Top Boot Block Addresses M29W400DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 22. Bottom Boot Block Addresses M29W400D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

APPENDIX B.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 23. Programmer Technique Bus Operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20.Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 22.In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 23.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 24. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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 M29W400DT, M29W400DB

SUMMARY DESCRIPTION
The M29W400D is a 4 Mbit (512Kb x8 or 256Kb Figure 2. Logic Diagram
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its VCC
Read mode where it can be read in the same way
as a ROM or EPROM.
The memory is divided into blocks that can be 18 15
erased independently so it is possible to preserve A0-A17 DQ0-DQ14
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the W DQ15A–1
memory. Program and Erase commands are writ- M29W400DT
ten to the Command Interface of the memory. An E M29W400DB BYTE
on-chip Program/Erase Controller simplifies the G RB
process of programming or erasing the memory by
taking care of all of the special operations that are RP
required to update the memory contents.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
VSS
The blocks in the memory are asymmetrically ar- AI06853
ranged, see Figures 6 and 7, Block Addresses.
The first or last 64 Kbytes have been divided into
four additional blocks. The 16 Kbyte Boot Block Table 1. Signal Names
can be used for small initialization code to start the
microprocessor, the two 8 Kbyte Parameter A0-A17 Address Inputs
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the ap- DQ0-DQ7 Data Inputs/Outputs
plication may be stored.
DQ8-DQ14 Data Inputs/Outputs
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory. DQ15A–1 Data Input/Output or Address Input
They allow simple connection to most micropro-
cessors, often without additional logic. E Chip Enable
The memory is offered in SO44, TSOP48 (12 x
20mm), TFBGA48 0.8mm pitch (6 x 9mm and 6 G Output Enable
x8mm) packages. The memory is supplied with all
W Write Enable
the bits erased (set to ’1’).
In addition to the standard versions, the packages RP Reset/Block Temporary Unprotect
are also available in Lead-free versions, in compli-
ance with JEDEC Std J-STD-020B, the ST ECO- RB Ready/Busy Output
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive. BYTE Byte/Word Organization Select
All packages are compliant with Lead-free solder-
VCC Supply Voltage
ing processes.
VSS Ground

NC Not Connected Internally

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M29W400DT, M29W400DB

Figure 3. SO Connections Figure 4. TSOP Connections

A15 1 48 A16
NC 1 44 RP
A14 BYTE
RB 2 43 W
A13 VSS
A17 3 42 A8
A12 DQ15A–1
A7 4 41 A9
A11 DQ7
A6 5 40 A10
A10 DQ14
A5 6 39 A11
A9 DQ6
A4 7 38 A12
A8 DQ13
A3 8 37 A13
NC DQ5
A2 9 36 A14
NC DQ12
A1 10 35 A15
W DQ4
A0 11 M29W400DT 34 A16
RP 12 M29W400DT 37 VCC
E 12 M29W400DB 33 BYTE
NC 13 M29W400DB 36 DQ11
VSS 13 32 VSS
NC DQ3
G 14 31 DQ15A–1
RB DQ10
DQ0 15 30 DQ7
NC DQ2
DQ8 16 29 DQ14
A17 DQ9
DQ1 17 28 DQ6
A7 DQ1
DQ9 18 27 DQ13
A6 DQ8
DQ2 19 26 DQ5
A5 DQ0
DQ10 20 25 DQ12
A4 G
DQ3 21 24 DQ4
A3 VSS
DQ11 22 23 VCC
A2 E
AI06855
A1 24 25 A0
AI06854

Note: 1. NC = Not Connected Note: 1. NC = Not Connected

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 M29W400DT, M29W400DB

Figure 5. TFBGA Connections (Top view through package)

1 2 3 4 5 6

A A3 A7 RB W A9 A13

B A4 A17 NC RP A8 A12

C A2 A6 NC NC A10 A14

D A1 A5 NC NC A11 A15

E A0 DQ0 DQ2 DQ5 DQ7 A16

F E DQ8 DQ10 DQ12 DQ14 BYTE

VCC DQ15
G G DQ9 DQ11 DQ13
A–1

H VSS DQ1 DQ3 DQ4 DQ6 VSS

AI06856

Note: 1. NC = Not Connected

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M29W400DT, M29W400DB

Figure 6. Block Addresses (x8)

M29W400DT M29W400DB
Top Boot Block Addresses (x8) Bottom Boot Block Addresses (x8)

7FFFFh 7FFFFh
16 KByte 64 KByte
7C000h 70000h
7BFFFh 6FFFFh
8 KByte 64 KByte
7A000h 60000h
79FFFh
8 KByte Total of 7
78000h 64 KByte Blocks
77FFFh
32 KByte
70000h
6FFFFh
64 KByte 1FFFFh
60000h 64 KByte
10000h
0FFFFh
32 KByte
08000h
07FFFh
Total of 7 8 KByte
64 KByte Blocks
06000h
1FFFFh 05FFFh
64 KByte 8 KByte
10000h 04000h
0FFFFh 03FFFh
64 KByte 16 KByte
00000h 00000h

AI06857

Note: Also see Appendix A, Tables 21 and 22 for a full listing of the Block Addresses.

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 M29W400DT, M29W400DB

Figure 7. Block Addresses (x16)

M29W400DT M29W400DB
Top Boot Block Addresses (x16) Bottom Boot Block Addresses (x16)

3FFFFh 3FFFFh
8 KWord 32 KWord
3E000h 38000h
3DFFFh 37FFFh
4 KWord 32 KWord
3D000h 30000h
3CFFFh
4 KWord Total of 7
3C000h 32 KWord Blocks
3BFFFh
16 KWord
38000h
37FFFh
32 KWord 0FFFFh
30000h 32 KWord
08000h
07FFFh
16 KWord
04000h
03FFFh
Total of 7 4 KWord
32 KWord Blocks
03000h
0FFFFh 02FFFh
32 KWord 4 KWord
08000h 02000h
07FFFh 01FFFh
32 KWord 8 KWord
00000h 00000h

AI06858

Note: Also see Appendix A, Tables 21 and 22 for a full listing of the Block Addresses.

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M29W400DT, M29W400DB

SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table goes High, VIH, the memory will be ready for Bus
1., Signal Names, for a brief overview of the sig- Read and Bus Write operations after tPHEL or
nals connected to this device. tRHEL, whichever occurs last. See the Ready/Busy
Address Inputs (A0-A17). The Address Inputs Output section, Table 15 and Figure 15, Reset/
select the cells in the memory array to access dur- Temporary Unprotect AC Characteristics for more
ing Bus Read operations. During Bus Write opera- details.
tions they control the commands sent to the Holding RP at VID will temporarily unprotect the
Command Interface of the Program/Erase Con- protected Blocks in the memory. Program and
troller. Erase operations on all blocks will be possible.
Data Inputs/Outputs (DQ0-DQ7). The Data In- The transition from VIH to VID must be slower than
puts/Outputs output the data stored at the selected tPHPHH.
address during a Bus Read operation. During Bus Ready/Busy Output (RB). The Ready/Busy pin
Write operations they represent the commands is an open-drain output that can be used to identify
sent to the Command Interface of the Program/ when the memory array can be read. Ready/Busy
Erase Controller. is high-impedance during Read mode, Auto Select
Data Inputs/Outputs (DQ8-DQ14). The Data In- mode and Erase Suspend mode.
puts/Outputs output the data stored at the selected After a Hardware Reset, Bus Read and Bus Write
address during a Bus Read operation when BYTE operations cannot begin until Ready/Busy be-
is High, VIH. When BYTE is Low, VIL, these pins comes high-impedance. See Table 15 and Figure
are not used and are high impedance. During Bus 15, Reset/Temporary Unprotect AC Characteris-
Write operations the Command Register does not tics.
use these bits. When reading the Status Register During Program or Erase operations Ready/Busy
these bits should be ignored. is Low, VOL. Ready/Busy will remain Low during
Data Input/Output or Address Input (DQ15A-1). Read/Reset commands or Hardware Resets until
When BYTE is High, VIH, this pin behaves as a the memory is ready to enter Read mode.
Data Input/Output pin (as DQ8-DQ14). When Byte/Word Organization Select (BYTE). The
BYTE is Low, VIL, this pin behaves as an address Byte/Word Organization Select pin is used to
pin; DQ15A–1 Low will select the LSB of the Word switch between the 8-bit and 16-bit Bus modes of
on the other addresses, DQ15A–1 High will select the memory. When Byte/Word Organization Se-
the MSB. Throughout the text consider references lect is Low, VIL, the memory is in 8-bit mode, when
to the Data Input/Output to include this pin when it is High, VIH, the memory is in 16-bit mode.
BYTE is High and references to the Address In- VCC Supply Voltage. The VCC Supply Voltage
puts to include this pin when BYTE is Low except supplies the power for all operations (Read, Pro-
when stated explicitly otherwise. gram, Erase etc.).
Chip Enable (E). The Chip Enable, E, activates The Command Interface is disabled when the VCC
the memory, allowing Bus Read and Bus Write op- Supply Voltage is less than the Lockout Voltage,
erations to be performed. When Chip Enable is VLKO. This prevents Bus Write operations from ac-
High, VIH, all other pins are ignored. cidentally damaging the data during power up,
Output Enable (G). The Output Enable, G, con- power down and power surges. If the Program/
trols the Bus Read operation of the memory. Erase Controller is programming or erasing during
Write Enable (W). The Write Enable, W, controls this time then the operation aborts and the memo-
the Bus Write operation of the memory’s Com- ry contents being altered will be invalid.
mand Interface. A 0.1µF capacitor should be connected between
Reset/Block Temporary Unprotect (RP). The the VCC Supply Voltage pin and the VSS Ground
Reset/Block Temporary Unprotect pin can be pin to decouple the current surges from the power
used to apply a Hardware Reset to the memory or supply. The PCB track widths must be sufficient to
to temporarily unprotect all Blocks that have been carry the currents required during program and
protected. erase operations, ICC3.
A Hardware Reset is achieved by holding Reset/ VSS Ground. The VSS Ground is the reference for
Block Temporary Unprotect Low, VIL, for at least all voltage measurements.
tPLPX. After Reset/Block Temporary Unprotect

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 M29W400DT, M29W400DB

BUS OPERATIONS
There are five standard bus operations that control ance state. To reduce the Supply Current to the
the device. These are Bus Read, Bus Write, Out- Standby Supply Current, ICC2, Chip Enable should
put Disable, Standby and Automatic Standby. See be held within VCC ± 0.2V. For the Standby current
Tables 2 and 3, Bus Operations, for a summary. level see Table 11., DC Characteristics.
Typically glitches of less than 5ns on Chip Enable During program or erase operations the memory
or Write Enable are ignored by the memory and do will continue to use the Program/Erase Supply
not affect bus operations. Current, ICC3, for Program or Erase operations un-
Bus Read. Bus Read operations read from the til the operation completes.
memory cells, or specific registers in the Com- Automatic Standby. If CMOS levels (VCC ± 0.2V)
mand Interface. A valid Bus Read operation in- are used to drive the bus and the bus is inactive for
volves setting the desired address on the Address 150ns or more the memory enters Automatic
Inputs, applying a Low signal, VIL, to Chip Enable Standby where the internal Supply Current is re-
and Output Enable and keeping Write Enable duced to the Standby Supply Current, ICC2. The
High, VIH. The Data Inputs/Outputs will output the Data Inputs/Outputs will still output data if a Bus
value, see Figure 12., Read Mode AC Waveforms, Read operation is in progress.
and Table 12., Read AC Characteristics, for de-
tails of when the output becomes valid. Special Bus Operations. Additional bus opera-
tions can be performed to read the Electronic Sig-
Bus Write. Bus Write operations write to the nature and also to apply and remove Block
Command Interface. A valid Bus Write operation Protection. These bus operations are intended for
begins by setting the desired address on the Ad- use by programming equipment and are not usu-
dress Inputs. The Address Inputs are latched by ally used in applications. They require VID to be
the Command Interface on the falling edge of Chip applied to some pins.
Enable or Write Enable, whichever occurs last.
Electronic Signature. The memory has two
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable codes, the manufacturer code and the device
code, that can be read to identify the memory.
or Write Enable, whichever occurs first. Output En-
able must remain High, VIH, during the whole Bus These codes can be read by applying the signals
listed in Tables 2 and 3, Bus Operations.
Write operation. See Figures 13 and 14, Write AC
Waveforms, and Tables 13 and 14, Write AC Block Protection and Blocks Unprotection.
Characteristics, for details of the timing require- Each block can be separately protected against
ments. accidental Program or Erase. Protected blocks
Output Disable. The Data Inputs/Outputs are in can be unprotected to allow data to be changed.
the high impedance state when Output Enable is There are two methods available for protecting
High, VIH. and unprotecting the blocks, one for use on pro-
Standby. When Chip Enable is High, VIH, the gramming equipment and the other for in-system
memory enters Standby mode and the Data In- use. Block Protect and Chip Unprotect operations
puts/Outputs pins are placed in the high-imped- are described in Appendix B.

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M29W400DT, M29W400DB

Table 2. Bus Operations, BYTE = VIL

Address Inputs Data Inputs/Outputs
Operation E G W
DQ15A–1, A0-A17 DQ14-DQ8 DQ7-DQ0
Bus Read VIL VIL VIH Cell Address Hi-Z Data Output

Bus Write VIL VIH VIL Command Address Hi-Z Data Input

Output Disable X VIH VIH X Hi-Z Hi-Z

Standby VIH X X X Hi-Z Hi-Z

Read Manufacturer A0 = VIL, A1 = VIL, A9 = VID,

VIL VIL VIH Hi-Z 20h
Code Others VIL or VIH

A0 = VIH, A1 = VIL, A9 = VID, EEh (M29W400DT)

Read Device Code VIL VIL VIH Hi-Z
Others VIL or VIH EFh (M29W400D)
Note: X = VIL or VIH.

Table 3. Bus Operations, BYTE = VIH

Address Inputs Data Inputs/Outputs
Operation E G W
A0-A17 DQ15A–1, DQ14-DQ0
Bus Read VIL VIL VIH Cell Address Data Output

Bus Write VIL VIH VIL Command Address Data Input

Output Disable X VIH VIH X Hi-Z

Standby VIH X X X Hi-Z

Read Manufacturer A0 = VIL, A1 = VIL, A9 = VID,

VIL VIL VIH 0020h
Code Others VIL or VIH

A0 = VIH, A1 = VIL, A9 = VID, 00EEh (M29W400DT)

Read Device Code VIL VIL VIH
Others VIL or VIH 00EFh (M29W400D)
Note: X = VIL or VIH.

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 M29W400DT, M29W400DB

COMMAND INTERFACE
All Bus Write operations to the memory are inter- quires four Bus Write operations, the final write op-
preted by the Command Interface. Commands eration latches the address and data and starts the
consist of one or more sequential Bus Write oper- Program/Erase Controller.
ations. Failure to observe a valid sequence of Bus If the address falls in a protected block then the
Write operations will result in the memory return- Program command is ignored, the data remains
ing to Read mode. The long command sequences unchanged. The Status Register is never read and
are imposed to maximize data security. no error condition is given.
The address used for the commands changes de- During the program operation the memory will ig-
pending on whether the memory is in 16-bit or 8- nore all commands. It is not possible to issue any
bit mode. See either Table 5, or 6, depending on command to abort or pause the operation. Typical
the configuration that is being used, for a summary program times are given in Table 4., Program,
of the commands. Erase Times and Program, Erase Endurance Cy-
Read/Reset Command. The Read/Reset com- cles. Bus Read operations during the program op-
mand returns the memory to its Read mode where eration will output the Status Register on the Data
it behaves like a ROM or EPROM, unless other- Inputs/Outputs. See the section on the Status
wise stated. It also resets the errors in the Status Register for more details.
Register. Either one or three Bus Write operations After the program operation has completed the
can be used to issue the Read/Reset command. memory will return to the Read mode, unless an
The Read/Reset Command can be issued, be- error has occurred. When an error occurs the
tween Bus Write cycles before the start of a pro- memory will continue to output the Status Regis-
gram or erase operation, to return the device to ter. A Read/Reset command must be issued to re-
read mode. Once the program or erase operation set the error condition and return to Read mode.
has started the Read/Reset command is no longer Note that the Program command cannot change a
accepted. The Read/Reset command will not bit set at ’0’ back to ’1’. One of the Erase Com-
abort an Erase operation when issued while in mands must be used to set all the bits in a block or
Erase Suspend. in the whole memory from ’0’ to ’1’.
Auto Select Command. The Auto Select com- Unlock Bypass Command. The Unlock Bypass
mand is used to read the Manufacturer Code, the command is used in conjunction with the Unlock
Device Code and the Block Protection Status. Bypass Program command to program the memo-
Three consecutive Bus Write operations are re- ry. When the access time to the device is long (as
quired to issue the Auto Select command. Once with some EPROM programmers) considerable
the Auto Select command is issued the memory time saving can be made by using these com-
remains in Auto Select mode until another com- mands. Three Bus Write operations are required
mand is issued. to issue the Unlock Bypass command.
From the Auto Select mode the Manufacturer Once the Unlock Bypass command has been is-
Code can be read using a Bus Read operation sued the memory will only accept the Unlock By-
with A0 = VIL and A1 = VIL. The other address bits pass Program command and the Unlock Bypass
may be set to either VIL or VIH. The Manufacturer Reset command. The memory can be read as if in
Code for STMicroelectronics is 0020h. Read mode.
The Device Code can be read using a Bus Read Unlock Bypass Program Command. The Un-
operation with A0 = VIH and A1 = VIL. The other lock Bypass Program command can be used to
address bits may be set to either VIL or VIH. The program one address in memory at a time. The
Device Code for the M29W400DT is 00EEh and command requires two Bus Write operations, the
for the M29W400D is 00EFh. final write operation latches the address and data
The Block Protection Status of each block can be and starts the Program/Erase Controller.
read using a Bus Read operation with A0 = VIL, The Program operation using the Unlock Bypass
A1 = VIH, and A12-A17 specifying the address of Program command behaves identically to the Pro-
the block. The other address bits may be set to ei- gram operation using the Program command. A
ther VIL or VIH. If the addressed block is protected protected block cannot be programmed; the oper-
then 01h is output on Data Inputs/Outputs DQ0- ation cannot be aborted and the Status Register is
DQ7, otherwise 00h is output. read. Errors must be reset using the Read/Reset
Program Command. The Program command command, which leaves the device in Unlock By-
can be used to program a value to one address in pass Mode. See the Program command for details
the memory array at a time. The command re- on the behavior.

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M29W400DT, M29W400DB

Unlock Bypass Reset Command. The Unlock changed. No error condition is given when protect-
Bypass Reset command can be used to return to ed blocks are ignored.
Read/Reset mode from Unlock Bypass Mode. During the Block Erase operation the memory will
Two Bus Write operations are required to issue the ignore all commands except the Erase Suspend
Unlock Bypass Reset command. Read/Reset command. Typical block erase times are given in
command does not exit from Unlock Bypass Table 4. All Bus Read operations during the Block
Mode. Erase operation will output the Status Register on
Chip Erase Command. The Chip Erase com- the Data Inputs/Outputs. See the section on the
mand can be used to erase the entire chip. Six Bus Status Register for more details.
Write operations are required to issue the Chip After the Block Erase operation has completed the
Erase Command and start the Program/Erase memory will return to the Read Mode, unless an
Controller. error has occurred. When an error occurs the
If any blocks are protected then these are ignored memory will continue to output the Status Regis-
and all the other blocks are erased. If all of the ter. A Read/Reset command must be issued to re-
blocks are protected the Chip Erase operation ap- set the error condition and return to Read mode.
pears to start but will terminate within about 100µs, The Block Erase Command sets all of the bits in
leaving the data unchanged. No error condition is the unprotected selected blocks to ’1’. All previous
given when protected blocks are ignored. data in the selected blocks is lost.
During the erase operation the memory will ignore Erase Suspend Command. The Erase Suspend
all commands. It is not possible to issue any com- Command may be used to temporarily suspend a
mand to abort the operation. Typical chip erase Block Erase operation and return the memory to
times are given in Table 4. All Bus Read opera- Read mode. The command requires one Bus
tions during the Chip Erase operation will output Write operation.
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more The Program/Erase Controller will suspend within
details. the Erase Suspend Latency Time after the Erase
Suspend Command is issued (see Table 4 for nu-
After the Chip Erase operation has completed the merical values). Once the Program/Erase Control-
memory will return to the Read Mode, unless an ler has stopped the memory will be set to Read
error has occurred. When an error occurs the mode and the Erase will be suspended. If the
memory will continue to output the Status Regis- Erase Suspend command is issued during the pe-
ter. A Read/Reset command must be issued to re- riod when the memory is waiting for an additional
set the error condition and return to Read Mode. block (before the Program/Erase Controller starts)
The Chip Erase Command sets all of the bits in un- then the Erase is suspended immediately and will
protected blocks of the memory to ’1’. All previous start immediately when the Erase Resume Com-
data is lost. mand is issued. It is not possible to select any fur-
Block Erase Command. The Block Erase com- ther blocks to erase after the Erase Resume.
mand can be used to erase a list of one or more During Erase Suspend it is possible to Read and
blocks. Six Bus Write operations are required to Program cells in blocks that are not being erased;
select the first block in the list. Each additional both Read and Program operations behave as
block in the list can be selected by repeating the normal on these blocks. If any attempt is made to
sixth Bus Write operation using the address of the program in a protected block or in the suspended
additional block. The Block Erase operation starts block then the Program command is ignored and
the Program/Erase Controller about 50µs after the the data remains unchanged. The Status Register
last Bus Write operation. Once the Program/Erase is not read and no error condition is given. Read-
Controller starts it is not possible to select any ing from blocks that are being erased will output
more blocks. Each additional block must therefore the Status Register.
be selected within 50µs of the last block. The 50µs It is also possible to issue the Auto Select and Un-
timer restarts when an additional block is selected. lock Bypass commands during an Erase Suspend.
The Status Register can be read after the sixth The Read/Reset command must be issued to re-
Bus Write operation. See the Status Register for turn the device to Read Array mode before the Re-
details on how to identify if the Program/Erase sume command will be accepted.
Controller has started the Block Erase operation.
Erase Resume Command. The Erase Resume
If any selected blocks are protected then these are command must be used to restart the Program/
ignored and all the other selected blocks are Erase Controller from Erase Suspend. An erase
erased. If all of the selected blocks are protected can be suspended and resumed more than once.
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un-

14/38
 M29W400DT, M29W400DB

Block Protect and Chip Unprotect Commands. be unprotected to allow the data inside the blocks
Each block can be separately protected against to be changed.
accidental Program or Erase. The whole chip can Block Protect and Chip Unprotect operations are
described in Appendix B.

Table 4. Program, Erase Times and Program, Erase Endurance Cycles

Parameter Min Typ (1,2) Max(2) Unit

Chip Erase (All bits in the memory set to ‘0’) 2.5 s

Chip Erase 6 35(3) s

Block Erase (64 Kbytes) 0.8 6(4) s

Program (Byte or Word) 10 200(3) µs

Chip Program (Byte by Byte) 5.5 30(3) s

Chip Program (Word by Word) 2.8 15(3) s

Erase Suspend Latency Time 18 25(4) µs

Program/Erase Cycles (per Block) 100,000 cycles

Data Retention 20 years
Note: 1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles.
4. Maximum value measured at worst case conditions for both temperature and VCC.

15/38
M29W400DT, M29W400DB

Table 5. Commands, 16-bit mode, BYTE = VIH

Bus Write Operations

Length
Command 1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1 X F0
Read/Reset
3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
2 X A0 PA PD
Program
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The
Command Interface only uses A-1; A0-A10 and DQ0-DQ7 to verify the commands; A11-A17, DQ8-DQ14 and DQ15 are Don't Care.
DQ15A-1 is A-1 when BYTE is VIL or DQ15 when BYTE is VIH.

Table 6. Commands, 8-bit mode, BYTE = VIL

Bus Write Operations
Length

Command 1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1 X F0
Read/Reset
3 AAA AA 555 55 X F0
Auto Select 3 AAA AA 555 55 AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass
2 X A0 PA PD
Program
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The
Command Interface only uses A-1; A0-A10 and DQ0-DQ7 to verify the commands; A11-A17, DQ8-DQ14 and DQ15 are Don't Care.
DQ15A-1 is A-1 when BYTE is VIL or DQ15 when BYTE is VIH.

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 M29W400DT, M29W400DB

STATUS REGISTER
Bus Read operations from any address always ror is signalled and DQ6 toggles for approximately
read the Status Register during Program and 1µs.
Erase operations. It is also read during Erase Sus- Figure 9., Data Toggle Flowchart, gives an exam-
pend when an address within a block being erased ple of how to use the Data Toggle Bit.
is accessed.
Error Bit (DQ5). The Error Bit can be used to
The bits in the Status Register are summarized in identify errors detected by the Program/Erase
Table 7., Status Register Bits. Controller. The Error Bit is set to ’1’ when a Pro-
Data Polling Bit (DQ7). The Data Polling Bit can gram, Block Erase or Chip Erase operation fails to
be used to identify whether the Program/Erase write the correct data to the memory. If the Error
Controller has successfully completed its opera- Bit is set a Read/Reset command must be issued
tion or if it has responded to an Erase Suspend. before other commands are issued. The Error bit
The Data Polling Bit is output on DQ7 when the is output on DQ5 when the Status Register is read.
Status Register is read. Note that the Program command cannot change a
During Program operations the Data Polling Bit bit set to ’0’ back to ’1’ and attempting to do so will
outputs the complement of the bit being pro- set DQ5 to ‘1’. A Bus Read operation to that ad-
grammed to DQ7. After successful completion of dress will show the bit is still ‘0’. One of the Erase
the Program operation the memory returns to commands must be used to set all the bits in a
Read mode and Bus Read operations from the ad- block or in the whole memory from ’0’ to ’1’
dress just programmed output DQ7, not its com- Erase Timer Bit (DQ3). The Erase Timer Bit can
plement. be used to identify the start of Program/Erase
During Erase operations the Data Polling Bit out- Controller operation during a Block Erase com-
puts ’0’, the complement of the erased state of mand. Once the Program/Erase Controller starts
DQ7. After successful completion of the Erase op- erasing, the Erase Timer Bit is set to ’1’. Before the
eration the memory returns to Read Mode. Program/Erase Controller starts the Erase Timer
In Erase Suspend mode the Data Polling Bit will Bit is set to ‘0’ and additional blocks to be erased
output a ’1’ during a Bus Read operation within a may be written to the Command Interface. The
block being erased. The Data Polling Bit will Erase Timer Bit is output on DQ3 when the Status
change from a ’0’ to a ’1’ when the Program/Erase Register is read.
Controller has suspended the Erase operation. Alternative Toggle Bit (DQ2). The Alternative
Figure 8., Data Polling Flowchart, gives an exam- Toggle Bit can be used to monitor the Program/
ple of how to use the Data Polling Bit. A Valid Ad- Erase controller during Erase operations. The Al-
dress is the address being programmed or an ternative Toggle Bit is output on DQ2 when the
address within the block being erased. Status Register is read.
Toggle Bit (DQ6). The Toggle Bit can be used to During Chip Erase and Block Erase operations the
identify whether the Program/Erase Controller has Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successfully completed its operation or if it has re- successive Bus Read operations from addresses
sponded to an Erase Suspend. The Toggle Bit is within the blocks being erased. A protected block
output on DQ6 when the Status Register is read. is treated the same as a block not being erased.
Once the operation completes the memory returns
During Program and Erase operations the Toggle
to Read mode.
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After During Erase Suspend the Alternative Toggle Bit
successful completion of the operation the memo- changes from ’0’ to ’1’ to ’0’, etc. with successive
ry returns to Read mode. Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
During Erase Suspend mode the Toggle Bit will dresses within blocks not being erased will output
output when addressing a cell within a block being
the memory cell data as if in Read mode.
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the After an Erase operation that causes the Error Bit
Erase operation. to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
If any attempt is made to erase a protected block, ror. The Alternative Toggle Bit changes from ’0’ to
the operation is aborted, no error is signalled and ’1’ to ’0’, etc. with successive Bus Read Opera-
DQ6 toggles for approximately 100µs. If any at-
tions from addresses within blocks that have not
tempt is made to program a protected block or a erased correctly. The Alternative Toggle Bit does
suspended block, the operation is aborted, no er-
not change if the addressed block has erased cor-
rectly.

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M29W400DT, M29W400DB

Table 7. Status Register Bits

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB
Program Any Address DQ7 Toggle 0 – – 0
Program During Erase
Any Address DQ7 Toggle 0 – – 0
Suspend
Program Error Any Address DQ7 Toggle 1 – – 0
Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before Erasing Block 0 Toggle 0 0 Toggle 0

timeout Non-Erasing Block 0 Toggle 0 0 No Toggle 0
Erasing Block 0 Toggle 0 1 Toggle 0
Block Erase
Non-Erasing Block 0 Toggle 0 1 No Toggle 0
Erasing Block 1 No Toggle 0 – Toggle 1
Erase Suspend
Non-Erasing Block Data read as normal 1
Good Block Address 0 Toggle 1 1 No Toggle 0
Erase Error
Faulty Block Address 0 Toggle 1 1 Toggle 0
Note: Unspecified data bits should be ignored.

Figure 8. Data Polling Flowchart Figure 9. Data Toggle Flowchart

START
START

READ DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ
DQ5 & DQ6
DQ7 YES
=
DATA
DQ6 NO
=
NO TOGGLE

YES
NO DQ5
=1
NO DQ5
YES =1

READ DQ7 YES

at VALID ADDRESS
READ DQ6
TWICE
DQ7 YES
=
DATA
DQ6 NO
NO =
TOGGLE

FAIL PASS YES

FAIL PASS
AI03598
AI01370C

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 M29W400DT, M29W400DB

MAXIMUM RATING
Stressing the device above the rating listed in the these or any other conditions above those indicat-
Absolute Maximum Ratings" table may cause per- ed in the Operating sections of this specification is
manent damage to the device. Exposure to Abso- not implied. Refer also to the STMicroelectronics
lute Maximum Rating conditions for extended SURE Program and other relevant quality docu-
periods may affect device reliability. These are ments.
stress ratings only and operation of the device at

Table 8. Absolute Maximum Ratings

Symbol Parameter Min Max Unit
TBIAS Temperature Under Bias –50 125 °C
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering (1) °C

VIO Input or Output Voltage (2,3) –0.6 VCC +0.6 V

VCC Supply Voltage –0.6 4 V

VID Identification Voltage –0.6 13.5 V
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assermbly), the ST ECOPACK® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
2. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.
3. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions.

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M29W400DT, M29W400DB

DC AND AC PARAMETERS
This section summarizes the operating measure- Conditions summarized in Table 9., Operating and
ment conditions, and the DC and AC characteris- AC Measurement Conditions. Designers should
tics of the device. The parameters in the DC and check that the operating conditions in their circuit
AC characteristics Tables that follow, are derived match the operating conditions when relying on
from tests performed under the Measurement the quoted parameters.

Table 9. Operating and AC Measurement Conditions

M29W400D
Parameter 45 55 70 Unit
Min Max Min Max Min Max
VCC Supply Voltage 3.0 3.6 2.7 3.6 2.7 3.6 V

Ambient Operating Temperature (range 6) –40 85 –40 85 –40 85

°C
Ambient Operating Temperature (range 1) 0 70 0 70 0 70
Load Capacitance (CL) 30 30 100 pF

Input Rise and Fall Times 10 10 10 ns

Input Pulse Voltages 0 to VCC 0 to VCC 0 to VCC V

Input and Output Timing Ref. Voltages VCC/2 VCC/2 VCC/2 V

Figure 10. AC Measurement I/O Waveform Figure 11. AC Measurement Load Circuit

VCC VCC

VCC

VCC/2
25kΩ
0V
DEVICE
AI04498 UNDER
TEST

25kΩ
0.1µF CL

AI04499
CL includes JIG capacitance

Table 10. Device Capacitance

Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 12 pF
Note: Sampled only, not 100% tested.

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 M29W400DT, M29W400DB

Table 11. DC Characteristics

Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA
E = VIL, G = VIH,
ICC1 Supply Current (Read) 10 mA
f = 6MHz
E = VCC ±0.2V,
ICC2 Supply Current (Standby)
RP = VCC ±0.2V
100 µA

Program/Erase
ICC3 (1) Supply Current (Program/Erase)
Controller active
20 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7VCC VCC +0.3 V

VOL Output Low Voltage IOL = 1.8mA 0.45 V

VOH Output High Voltage IOH = –100µA VCC –0.4 V

VID Identification Voltage 11.5 12.5 V

IID Identification Current A9 = VID 100 µA

Program/Erase Lockout Supply
VLKO 1.8 2.3 V
Voltage
Note: 1. Sampled only, not 100% tested.

Figure 12. Read Mode AC Waveforms

tAVAV
A0-A17/
VALID
A–1
tAVQV tAXQX

tELQV tEHQX

tELQX tEHQZ

tGLQX tGHQX

tGLQV tGHQZ
DQ0-DQ7/
VALID
DQ8-DQ15
tBHQV

BYTE

tELBL/tELBH tBLQZ AI02907

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M29W400DT, M29W400DB

Table 12. Read AC Characteristics

M29W400D
Symbol Alt Parameter Test Condition Unit
45 55 70
E = VIL,
tAVAV tRC Address Valid to Next Address Valid Min 45 55 70 ns
G = VIL

E = VIL,
tAVQV tACC Address Valid to Output Valid Max 45 55 70 ns
G = VIL

tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 0 ns

tELQV tCE Chip Enable Low to Output Valid G = VIL Max 45 55 70 ns

Output Enable Low to Output

tGLQX (1) tOLZ
Transition
E = VIL Min 0 0 0 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL Max 25 30 35 ns

tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 20 25 30 ns

tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 20 25 30 ns

tEHQX
Chip Enable, Output Enable or
tGHQX tOH Min 0 0 0 ns
Address Transition to Output Transition
tAXQX

tELBL tELFL
Chip Enable to BYTE Low or High Max 5 5 5 ns
tELBH tELFH

tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 25 30 ns

tBHQV tFHQV BYTE High to Output Valid Max 30 30 40 ns
Note: 1. Sampled only, not 100% tested.

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 M29W400DT, M29W400DB

Figure 13. Write AC Waveforms, Write Enable Controlled

tAVAV
A0-A17/
VALID
A–1
tWLAX

tAVWL tWHEH

tELWL tWHGL

tGHWL tWLWH

tWHWL

tDVWH tWHDX
DQ0-DQ7/
VALID
DQ8-DQ15

VCC

tVCHEL

RB

tWHRL AI01869C

Table 13. Write AC Characteristics, Write Enable Controlled

M29W400D
Symbol Alt Parameter Unit
45 55 70
tAVAV tWC Address Valid to Next Address Valid Min 45 55 70 ns
tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 0 ns
tWLWH tWP Write Enable Low to Write Enable High Min 30 30 30 ns
tDVWH tDS Input Valid to Write Enable High Min 25 30 45 ns
tWHDX tDH Write Enable High to Input Transition Min 0 0 0 ns
tWHEH tCH Write Enable High to Chip Enable High Min 0 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 30 30 30 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 0 ns
tWLAX tAH Write Enable Low to Address Transition Min 40 45 45 ns
tGHWL Output Enable High to Write Enable Low Min 0 0 0 ns
tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 0 ns

tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 35 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 50 µs

Note: 1. Sampled only, not 100% tested.

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M29W400DT, M29W400DB

Figure 14. Write AC Waveforms, Chip Enable Controlled

tAVAV
A0-A17/
VALID
A–1
tELAX

tAVEL tEHWH

tWLEL tEHGL

tGHEL tELEH

tEHEL

tDVEH tEHDX
DQ0-DQ7/
VALID
DQ8-DQ15

VCC

tVCHWL

RB

tEHRL AI01870C

Table 14. Write AC Characteristics, Chip Enable Controlled

M29W400D
Symbol Alt Parameter Unit
45 55 70
tAVAV tWC Address Valid to Next Address Valid Min 45 55 70 ns
tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 0 ns
tELEH tCP Chip Enable Low to Chip Enable High Min 30 30 30 ns
tDVEH tDS Input Valid to Chip Enable High Min 25 30 45 ns
tEHDX tDH Chip Enable High to Input Transition Min 0 0 0 ns
tEHWH tWH Chip Enable High to Write Enable High Min 0 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 30 30 30 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 0 ns
tELAX tAH Chip Enable Low to Address Transition Min 40 45 45 ns
tGHEL Output Enable High Chip Enable Low Min 0 0 0 ns
tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 0 ns

tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 35 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 50 µs

Note: 1. Sampled only, not 100% tested.

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 M29W400DT, M29W400DB

Figure 15. Reset/Block Temporary Unprotect AC Waveforms

W, E, G

tPHWL, tPHEL, tPHGL

RB

tRHWL, tRHEL, tRHGL

tPLPX
RP
tPHPHH

tPLYH

AI02931

Table 15. Reset/Block Temporary Unprotect AC Characteristics

M29W400D
Symbol Alt Parameter Unit
45 55 70

tPHWL (1)
RP High to Write Enable Low, Chip Enable Low,
tPHEL tRH Min 50 50 50 ns
Output Enable Low
tPHGL (1)

tRHWL (1)
RB High to Write Enable Low, Chip Enable Low,
tRHEL (1) tRB
Output Enable Low
Min 0 0 0 ns
(1)
tRHGL

tPLPX tRP RP Pulse Width Min 500 500 500 ns

tPLYH (1) tREADY RP Low to Read Mode Max 10 10 10 µs

tPHPHH (1) tVIDR RP Rise Time to VID Min 500 500 500 ns
Note: 1. Sampled only, not 100% tested.

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M29W400DT, M29W400DB

PACKAGE MECHANICAL

Figure 16. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline

A2 A
C
b e
CP

E EH

1 A1 α L
SO-d

Note: Drawing is not to scale.

Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 2.80 0.1102
A1 0.10 0.0039
A2 2.30 2.20 2.40 0.0906 0.0866 0.0945
b 0.40 0.35 0.50 0.0157 0.0138 0.0197
C 0.15 0.10 0.20 0.0059 0.0039 0.0079
CP 0.08 0.0030
D 28.20 28.00 28.40 1.1102 1.1024 1.1181
E 13.30 13.20 13.50 0.5236 0.5197 0.5315
EH 16.00 15.75 16.25 0.6299 0.6201 0.6398
e 1.27 – – 0.0500 – –
L 0.80 0.0315
a 8 8
N 44 44

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 M29W400DT, M29W400DB

Figure 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

1 48
e

D1 B

24 25 L1
A2 A
E1
E

DIE A1 α L

C
CP TSOP-G

Note: Drawing is not to scale.

Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.100 0.050 0.150 0.0039 0.0020 0.0059
A2 1.000 0.950 1.050 0.0394 0.0374 0.0413
B 0.220 0.170 0.270 0.0087 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.080 0.0031
D1 12.000 11.900 12.100 0.4724 0.4685 0.4764
E 20.000 19.800 20.200 0.7874 0.7795 0.7953
E1 18.400 18.300 18.500 0.7244 0.7205 0.7283
e 0.500 – – 0.0197 – –
L 0.600 0.500 0.700 0.0236 0.0197 0.0276
L1 0.800 0.0315
α 3 0 5 3 0 5

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M29W400DT, M29W400DB

Figure 18. TFBGA48 6x9mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline

D1
FD
FE SD

SE
BALL "A1"
E E1
ddd

e b
A A2
A1

BGA-Z00

Note: Drawing is not to scale.

Table 18. TFBGA48 6x9mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.200 0.0079
A2 1.000 0.0394
b 0.400 0.350 0.450 0.0157 0.0138 0.0177
D 6.000 5.900 6.100 0.2362 0.2323 0.2402
D1 4.000 – – 0.1575 – –
ddd 0.100 0.0039
E 9.000 8.900 9.100 0.3543 0.3504 0.3583
e 0.800 – – 0.0315 – –
E1 5.600 – – 0.2205 – –
FD 1.000 – – 0.0394 – –
FE 1.700 – – 0.0669 – –
SD 0.400 – – 0.0157 – –
SE 0.400 – – 0.0157 – –

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 M29W400DT, M29W400DB

Figure 19. TFBGA48 6x8mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline

D1
FD
FE SD

SE
BALL "A1"
E E1
ddd

e b
A A2
A1

BGA-Z32

Note: Drawing is not to scale.

Table 19. TFBGA48 6x8mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.260 0.0102
A2 0.900 0.0354
b 0.350 0.450 0.0138 0.0177
D 6.000 5.900 6.100 0.2362 0.2323 0.2402
D1 4.000 – – 0.1575 – –
ddd 0.100 0.0039
E 8.000 7.900 8.100 0.3150 0.3110 0.3189
E1 5.600 – – 0.2205 – –
e 0.800 – – 0.0315 – –
FD 1.000 – – 0.0394 – –
FE 1.200 – – 0.0472 – –
SD 0.400 – – 0.0157 – –
SE 0.400 – – 0.0157 – –

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M29W400DT, M29W400DB

PART NUMBERING

Table 20. Ordering Information Scheme

Example:M29W400D 55 N 6 T

Device Type
M29

Operating Voltage
W = VCC = 2.7 to 3.6V

Device Function
400D = 4 Mbit (512Kx8 or 256Kx16), Boot Block

Array Matrix
T = Top Boot
B = Bottom Boot

Speed
45 = 45ns
55 = 55ns
70 = 70ns

Package
M = SO44
N = TSOP48: 12 x 20mm
ZA = TFBGA48: 6 x 9mm
ZE = TFBGA48: 6 x 8mm

Temperature Range
6 = –40 to 85 °C
1 = 0 to 70 °C

Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-free and RoHS Package, Standard Packing
F = Lead-free and RoHS Package, Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.

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 M29W400DT, M29W400DB

APPENDIX A. BLOCK ADDRESS TABLE

Table 21. Top Boot Block Addresses Table 22. Bottom Boot Block Addresses
M29W400DT M29W400D
Size Address Range Address Range Size Address Range Address Range
# #
(Kbytes) (x8) (x16) (Kbytes) (x8) (x16)
10 16 7C000h-7FFFFh 3E000h-3FFFFh 10 64 70000h-7FFFFh 38000h-3FFFFh
9 8 7A000h-7BFFFh 3D000h-3DFFFh 9 64 60000h-6FFFFh 30000h-37FFFh
8 8 78000h-79FFFh 3C000h-3CFFFh 8 64 50000h-5FFFFh 28000h-2FFFFh
7 32 70000h-77FFFh 38000h-3BFFFh 7 64 40000h-4FFFFh 20000h-27FFFh
6 64 60000h-6FFFFh 30000h-37FFFh 6 64 30000h-3FFFFh 18000h-1FFFFh
5 64 50000h-5FFFFh 28000h-2FFFFh 5 64 20000h-2FFFFh 10000h-17FFFh
4 64 40000h-4FFFFh 20000h-27FFFh 4 64 10000h-1FFFFh 08000h-0FFFFh
3 64 30000h-3FFFFh 18000h-1FFFFh 3 32 08000h-0FFFFh 04000h-07FFFh
2 64 20000h-2FFFFh 10000h-17FFFh 2 8 06000h-07FFFh 03000h-03FFFh
1 64 10000h-1FFFFh 08000h-0FFFFh 1 8 04000h-05FFFh 02000h-02FFFh
0 64 00000h-0FFFFh 00000h-07FFFh 0 16 00000h-03FFFh 00000h-01FFFh

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M29W400DT, M29W400DB

APPENDIX B. BLOCK PROTECTION

Block protection can be used to prevent any oper- Technique Bus Operations, BYTE = VIH or VIL,
ation from modifying the data stored in the Flash. gives a summary of each operation.
Each Block can be protected individually. Once The timing on these flowcharts is critical. Care
protected, Program and Erase operations on the should be taken to ensure that, where a pause is
block fail to change the data. specified, it is followed as closely as possible. Do
There are three techniques that can be used to not abort the procedure before reaching the end.
control Block Protection, these are the Program- Chip Unprotect can take several seconds and a
mer technique, the In-System technique and Tem- user message should be provided to show that the
porary Unprotection. Temporary Unprotection is operation is progressing.
controlled by the Reset/Block Temporary Unpro- In-System Technique
tection pin, RP; this is described in the Signal De-
scriptions section. The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
Unlike the Command Interface of the Program/ pin, RP. This can be achieved without violating the
Erase Controller, the techniques for protecting and maximum ratings of the components on the micro-
unprotecting blocks change between different processor bus, therefore this technique is suitable
Flash memory suppliers. For example, the tech- for use after the Flash has been fitted to the sys-
niques for AMD parts will not work on STMicro- tem.
electronics parts. Care should be taken when
To protect a block follow the flowchart in Figure
changing drivers for one part to work on another.
22., In-System Equipment Block Protect Flow-
Programmer Technique chart. To unprotect the whole chip it is necessary
The Programmer technique uses high (VID) volt- to protect all of the blocks first, then all the blocks
age levels on some of the bus pins. These cannot can be unprotected at the same time. To unprotect
be achieved using a standard microprocessor bus, the chip follow Figure 23., In-System Equipment
therefore the technique is recommended only for Chip Unprotect Flowchart.
use in Programming Equipment. The timing on these flowcharts is critical. Care
To protect a block follow the flowchart in Figure should be taken to ensure that, where a pause is
20., Programmer Equipment Block Protect Flow- specified, it is followed as closely as possible. Do
chart.To unprotect the whole chip it is necessary to not allow the microprocessor to service interrupts
protect all of the blocks first, then all blocks can be that will upset the timing and do not abort the pro-
unprotected at the same time. To unprotect the cedure before reaching the end. Chip Unprotect
chip follow Figure 21., Programmer Equipment can take several seconds and a user message
Chip Unprotect Flowchart. Table 23., Programmer should be provided to show that the operation is
progressing.

Table 23. Programmer Technique Bus Operations, BYTE = VIH or VIL

Address Inputs Data Inputs/Outputs
Operation E G W
A0-A17 DQ15A–1, DQ14-DQ0
A9 = VID, A12-A17 Block Address
Block Protect VIL VID VIL Pulse X
Others = X
A9 = VID, A12 = VIH, A15 = VIH
Chip Unprotect VID VID VIL Pulse X
Others = X
A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,
Block Protection Pass = XX01h
VIL VIL VIH A12-A17 Block Address
Verify Retry = XX00h
Others = X
A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,
Block Unprotection Retry = XX01h
VIL VIL VIH A12-A17 Block Address
Verify Pass = XX00h
Others = X

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 M29W400DT, M29W400DB

Figure 20. Programmer Equipment Block Protect Flowchart

START

ADDRESS = BLOCK ADDRESS

Set-up

W = VIH

n=0

G, A9 = VID,
E = VIL

Wait 4µs
Protect

W = VIL

Wait 100µs

W = VIH

E, G = VIH,
A0, A6 = VIL,
A1 = VIH

E = VIL

Wait 4µs

G = VIL
Verify

Wait 60ns

Read DATA

DATA NO
=
01h
YES
++n NO
A9 = VIH = 25
E, G = VIH
YES
End

PASS A9 = VIH
E, G = VIH

AI03469
FAIL

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M29W400DT, M29W400DB

Figure 21. Programmer Equipment Chip Unprotect Flowchart

START

PROTECT ALL BLOCKS

Set-up

n=0
CURRENT BLOCK = 0

A6, A12, A15 = VIH(1)

E, G, A9 = VID

Wait 4µs
Unprotect

W = VIL

Wait 10ms

W = VIH

E, G = VIH

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1, A6 = VIH

E = VIL

Wait 4µs

G = VIL INCREMENT
CURRENT BLOCK
Wait 60ns
Verify

Read DATA

NO DATA YES
=
00h

NO ++n LAST NO
= 1000 BLOCK

YES YES

A9 = VIH A9 = VIH
End

E, G = VIH E, G = VIH

FAIL PASS AI03470

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 M29W400DT, M29W400DB

Figure 22. In-System Equipment Block Protect Flowchart

START
Set-up

n=0

RP = VID

WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL

WRITE 60h
ADDRESS = BLOCK ADDRESS
Protect

A0 = VIL, A1 = VIH, A6 = VIL

Wait 100µs

WRITE 40h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
Verify

Wait 4µs

READ DATA
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL

DATA NO
=
01h
YES
++n NO
RP = VIH = 25
End

YES
ISSUE READ/RESET
COMMAND
RP = VIH

PASS
ISSUE READ/RESET
COMMAND

FAIL
AI03471

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M29W400DT, M29W400DB

Figure 23. In-System Equipment Chip Unprotect Flowchart

START

PROTECT ALL BLOCKS

Set-up

n=0
CURRENT BLOCK = 0

RP = VID

WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH

WRITE 60h
Unprotect

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = VIH

Wait 10ms

WRITE 40h
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
Verify

Wait 4µs
INCREMENT
CURRENT BLOCK
READ DATA
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH

NO DATA YES
=
00h

NO ++n LAST NO
= 1000 BLOCK
End

YES YES

RP = VIH RP = VIH

ISSUE READ/RESET ISSUE READ/RESET

COMMAND COMMAND

FAIL PASS
AI03472

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 M29W400DT, M29W400DB

REVISION HISTORY

Table 24. Document Revision History

Date Version Revision Details
26-Jul-2002 -01 First Issue
Revision numbering modified: a minor revision will be indicated by incrementing the digit
after the dot, and a major revision, by incrementing the digit before the dot (revision
version 01 equals 1.0). Revision History moved to end of document.
Typical after 100k W/E Cycles column removed from Table 4, Program, Erase Times and
19-Feb-2003 2.0
Program, Erase Endurance Cycles, Data Retention and Erase Suspend Latency Time
parameters added. Common Flash Interface removed from datasheet.
Lead-free package options E and F added to Table 20., Ordering Information Scheme.
Document promoted from Product Preview to Preliminary Data status.
tWLWH and tELEH parameters modified for all Speed Classes in Tables 13 and 14,
respectively (“Write AC Characteristics, Write Enable Controlled” and “Write AC
28-May-2003 2.1
Characteristics, Chip Enable Controlled”). Minor text changes. TSOP48 package updated
(Figure 17 and Table 17).
Document status changed to Full datasheet. TFBGA48 6x8 package added.
30-Sep-2003 2.2
TLEAD parameter added in Table 8., Absolute Maximum Ratings.

6-Oct-2003 2.3 tGLQV modified in Table 12, Read AC Characteristics.

16-Jan-2004 3.0 RB pin description corrected in Table 1., Signal Names.

Tape and Reel option updated in Table 20., Ordering Information Scheme.
8-Jun-2004 4.0 Lead-free packaging promotion updated in FEATURES SUMMARY, SUMMARY
DESCRIPTION, MAXIMUM RATING and PART NUMBERING sections.

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M29W400DT, M29W400DB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

ECOPACK® is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.

© 2004 STMicroelectronics - All rights reserved

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