THAMIRABHARANI ENGINEERING COLLEGE

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Thatchanallur, Tirunelveli 627 358, Tamil Nadu.

DEPARTMENT OF ELECTRONICS AND COMMUNIATION ENGINEERING

EC 3552 – VLSI AND CHIP DESIGN
UNIT – I MOS TRANSISTOR
PRINCIPLES PART-A
1. What is meant by channel length modulation?
The p–n junction between the drain and body forms a depletion region with a width of
Ld that increases with Vdb (Drain to body voltage). The depletion region effectively
shortens the channel length to
Leff = L - Ld
2. Define a propagation delay for CMOS inverter.
The propagation delay of the CMOS inverter is determined by the time it takes to
charge and discharge the capacitances present in the logic circuit.
Propagation Delay Time, tpd:
Maximum time from the input crossing 50% to the output crossing 50%
3. Define any two layout design rules.
Scalable Design Rules (e.g. SCMOS, λ-based design rules)
Absolute Design Rules (e.g. μ-based design rules)
4. What is latch up? How to prevent a latch up.
Latch Up:
Latch is the generation of a low-impedance path in CMOS chips between the power
supply and the ground rails due to interaction of parasitic pnp and npn bipolar
transistors. This causes excessive current flows to the devices.
Prevention:
i. Increase well and substrate doping concentrations to reduce Rwell and
Rsub. For example, using retrograde doped wells.
ii. Provide alternative (or better) collectors of the minority carriers. For
example, the use of guard rings around devices.
 5. Define body effect.
The threshold voltage Vt is constant or varied, with respect to voltage difference
between source and the body is called body effect.

6. Define lambda layout rule.

Lambda rules specify the layout with minimum feature sizes and minimum allowable feature

separations in terms of parameter λ and allow linear proportional scaling of all geometrical

constraint.

7. What are stick diagram.

Stick diagram are the key element of designing a circuit used to convey layer information through

the use of a color code.

8. What is CMOS technology.

Complementary Metal Oxide Semiconductor (CMOS) in which both n-channel MOS and

p-channel MOS are fabricated in the same IC.

9. Write a parasitic delay and logical effort for basic gates.

Logical Effort:

Parasitic Delay :
 10.Define a threshold voltage for a MOSFET.
The threshold voltage of a MOSFET is usually defined as the gate voltage were an
inversion layer forms at the interface between the insulating layer (oxide) and the
substrate (body) of the transistor.
11.What are the objective (need) of layout rules?
i. To build reliably functional circuits in as small an area as possible.
ii. To provide a necessary communication link circuit designer and process
engineer during manufacturing.
iii. To obtain a circuit with optimum yield in smallest possible area.

12.Why nMOS transistor is selected as pull down transistor.

When high voltage is given at the input nMOS is turned ON. So the output is pulled down to Vss. An
NMOS device pulls the output all the way down to GND, while a PMOS lowers the output no further than
|VTp| — the PMOS turns off at that point, and stops contributing dis-charge current. NMOS
transistorsare hence the preferred devices in the PDN.

13. Compare nMOS and pMOS transistor.

S.No nMOS pMOS

1 The majority carriers are electron The majority carriers are electron

2 Positive voltage is applied at the gate Negative voltage is applied at the gate
terminal terminal
3 NMOS conducts at logic 1 PMOS conducts at logic 0

4 Mobility of electron is high Mobility of electron is low

5 Switching speed is high Switching speed is low

 14.Draw the 3-input NOR gate using CMOS Logic with truth table

15. Differentiate pass transistor and transmission gate.

pass transistor: Whan a nmos or pmos is used alone us an imperfect switch we call it pass transistor
transmission gate: By combining the nmos and pmos transistor in parallel, we obtain the switch that turns ON
when a 1 is applied to g in which zeros or ones are passed in acceptable manner
16. Write about pull-up and pull-down network.
Pullup - a network that provides a low resistance path to Vdd when output is logic '1' and provides a high
resistance to Vdd otherwise.
Pulldown - a network that provides a low resistance path to Gnd when output is logic '0' and provides a high
resistance to Gnd otherwise.

17. Write about inversion layer.

In this mode, a higher positive potential exceeding a critical threshold voltage is applied. The attracts more
positive charge to the gate. The holes are repelled further and a small number of free electrons in the body are
attracted to the region beneath the gate. This conductive layer of electrons in the p-type body is called the inversion
layer.
18. Sketch the static CMOS gate computing Y =((A+B+C).D)’
 19. What is drain induced barrier lowering effect?
Drain-induced barrier lowering (DIBL) is a short-channel effect in MOSFETs referring originally
to a reduction of threshold voltage of the transistor at higher drain voltages.

20. Define scaling. What are the advantages of scaling? List different types of scaling.
Proportional adjustment of the dimensions of an electronic device while maintaining the electrical properties
of the device, results in a device either larger or smaller than the unscaled device.
Types:
 Full scaling (or) constant field scaling
 Fixed voltage scaling
 General scaling (or) Lateral scaling
Advantages:
 Greater device density
 Higher speed
 Reduced power consumption
 Improved performance due to reduced capacitance
 PART-B
1. Explain in detail about the ideal I-V characteristics of nMOS and pMOS
devices.
2. Explain in detail about non-ideal I-V characteristics of nMOS and pMOS devices.
3. Explain DC transfer characteristics of a CMOS inverter with necessary
conditions for the different regions of operation.

4. Discuss the principles of constant field and lateral scaling.

5. Describe the equation for source to drain current in the three regions of
operation of a MOS transistor and draw the VI characteristics.

6. Explain the need of scaling, scaling principles and fundamental units of

CMOS inverter.

7. Explain the Operating regions of MOS transistor?

8. Explain the n-well process?

9. Explain Power-Consumption Components?

10. Explain Static power consumption and Dynamic power consumption?

0
 UNIT – II COMBINATIONAL LOGIC CIRCUITS
PART-A
1. Define Elmore constant.
Elmore delay is a simple approximation to the delay through an RC network in an
electronic system.

The Elmore delay model estimates the delay from a source switching to one of the
leaf nodes changing as the sum over each node i of the capacitance Ci on the node,
multiplied by the effective resistance R is on the shared path from the source to the
node and the leaf. Application of Elmore delay is best illustrated through examples.

2. What are the factors that causes a power dissipation in CMOS circuits?
Static Dissipation:
i. Sub threshold condition through OFF transistors
ii. Tunneling current through gate oxide
iii. Leakage through the reverse bias diode
iv. Contention current in ratioed
circuits Dynamic Dissipation:
i. Charging and discharging of load capacitance
ii. Short circuit current while both PMOS and NMOS network are partially ON.
3. Implement a 2 : 1 mux using Pass transistor.
4. Define logical effort.
The ratio of the input capacitance of the gate to the input capacitance of the inverter is
called logical effort
5. How to avoid monotonicity problem in dynamic CMOS.
The monotonicity problem can be solved by placing a static CMOS inverter between
dynamic gates. This is used to convert the monotonically falling output into a
monotonically rising signal
6. Distinguish between static and dynamic CMOS design.
S.No Static CMOS Dynamic CMOS
1 It required a 2N number of It required only N+1 gates
gates to implement a circuit
Where N – Number of input
2 No Monotonicity problem Monotonicity problem arises
3 No need of Clock pulse Required a careful clocking

7. Why keepers are used in domino logic?

Keepers must be wide enough to compensate for any leakage current drawn when the
output is floating and pull-down network is OFF.
8. Define level restoration.
The level restores is feed back transistor of an inverter which is help to eliminate the
static power dissipation in the inverter and no static current path can exist through the
level restorer.
9. What is branching effort?
The ratio of total capacitance seen by a stage to a capacitance on the path
b = C on path + C off path / C on path

10. What is Elmore’s Constant? Give Elmore delay expression for propagation delay of
an inverter.
It is an analytical method used to estimate the RC delay in a network. Elmore delay model estimates
the delay of a RC ladder as the sum over each node in the ladder of the resistance Rn-1 betweenthat node and a
supply multiplied by the capacitor on the nodes.
 11. Why single phase dynamic logic structure cannot be cascaded? Justify.
The cascading of dynamic logic from one gate to other gives problem. The precharge "1" state of
the first gate causes the second gate to discharge prematurely, before the first gate has reached its correct
state. This uses up the "precharge" of the second gate, which cannot be restored until the next clock
cycle,thus there is no recovery from this error.
12. What do you meant by design margin?
The additional performance capability above required standard basic system parameters that may
be specified by a system designer to compensate for uncertainties is called design margin. Design margin
required as there are three sources of variation- two environmental and one manufacturing.

13. What are factors that cause static power dissipation in CMOS circuits?
Power dissipation due to leakage current when the idle is called the static power dissipation.
Static power due to
i. Sub – threshold conduction through OFF transistors
ii. Tunneling current through gate oxide
iii. Leakage through reverse biased diodes
iv. Contention current in radioed circuits.
 14. What are the methods to reduce dynamic power dissipation?
i. Reducing the product of capacitance and its switching frequency.
ii. Eliminate logic switching that is not necessary for computation.
iii. Reduce activity factor Reduce supply voltage
15. List various sources of leakage currents?
Various source of leakage currents are listened
below: I1=Reverse-bias p-n junction diode
leakage current.

I2=band-to-band tunneling current

I3=Subthreshold leakage current
I4=Gate oxide tunneling current
I5=Gate current due to hot carrier junction
I6=Channel punch through
I7=Gate induced drain leakage current

16. What is stick diagram? Sketch the stick diagram for 3 input NOR gate.

Stick diagrams are a means of capturing topography and layer information using simple diagrams.
Stick diagrams convey layer information through color codes. Acts as an interface between symbolic
circuit and the actual layout.

17. What is staic CMOS logic?

Static CMOS logic is a combination of two networks, Pull up Network using PMOS transistors
and Pull down network using NMOS transistors. They are dual with each other. At any time ,any
one of the network is on.

18. What is dynamic CMOS logic?

Dynamic circuits reduce the drawbacks of ratioed circuits using a clock input to the pull up transistor(PMOS).
It requires N+2 transistors and there are two modes of operation ,Precharge and Evaluation.
19.What are the disadvantages of dynamic logic?
 Consume significant dynamic power
 Sensitive to noise during evaluation
 Carefull clocking
 Monotonicity problem

20.Define propagation delay.

The propagation delay is the time taken to change the output after applying the input.
This is the upper bound on interval between valid inputs and valid outputs.
 PART-B
1.Derive the expressions for effective resistance and capacitance estimation Using
Elmore’s RC delay model.
2. Write short notes on i) Static CMOS, ii) Bubble pushing, iii) Compound gates.
3. Illustrate the operation of dynamic CMOS Domino and NP Domino logic with
necessary diagrams.
4. What are the sources of power dissipation in CMOS and discuss various design
techniques to reduce power dissipation in CMOS.
5. Write the basic principle of low power logic design.
6. Derive an expression for dynamic power dissipation.
7. Explain the pass transistor logic and show how complementary pass transistor logic
and double pass transistor logic are applied for 2: 1 multiplexer.
8. Write short notes on (i)Ratioed Circuits (ii)Dynamic CMOS Circuits.
9. Enumerate the features of static CMOS logic.
10. Explain the static and dynamic power dissipation in CMOS circuits with expressions.
 UNIT – III SEQUENTIAL LOGIC CIRCUITS AND CLOCKING STRATEGIES
PART -A
1. Compare SRAM and DRAM.
Both SRAMs and DRAMs are volatile in nature, (i.e.) Information is lost if power
line is removed. However SRAMs provide high switching speed, good noise margin
but require large chip area than DRAMs.
2. Define meta stability
Meta stability is a unknown state is neither 0 or 1. Meta stability happens for the
design systems violating setup or hold time requirement.
3. Define setup and holding time
Set up time (tsu):
The time that the data input (D) is valid before the clock transition that is 0 to 1
transition for a positive edge -triggered registers
Hold time (t hold)
The time that the data input must remain valid after the clock edge.
4. Distinguish between a latches and flip flop.
S.No Latches Flip Flop
1 A Latch is Level-Sensitive A FF is edge triggered.
2 A latch stores when the clock A FF stores when the clock rises
level is low and is transparent and is mostly never transparent.
when the level is high.
5. Define Skew and Jitter
Skew:
Clock skew defined as a spatial variation in arrival time of a clock transition on an
integrated circuit
Jitter:
Clock jitter is a temporal variation of the clock period at a given point on the chip.
6. Define pipelining
Pipelining is a popular design technique often used to accelerate the operation of the
data path in digital processors. The major advantages of pipelining are to reduce
glitching in complex logic networks and getting lower energy due to operand
isolation.
7. What is C2MOS register
The positive edge triggered register based on master slave concept insensitive to clock
overlap. This is called clocked CMOS or C2MOS.
8. What is NORA CMOS?
NORA-CMOS is a logic circuit that combines C2MOS pipeline and NORA dynamic
logic function blocks. Each module consists of a block of combinational logic with a
mixture of static and dynamic logic followed by a C2MOS latch.
9. Write the importance of Sense amplifiers
Sense amplifier play a major role in the functionality, performance and reliability of
memory circuits.
The following are the functions of sense amplifier
i. Amplification
ii. Delay reduction
iii. Power reduction
iv. Signal restoration
 10. Define Race condition?
When a CLK and CLK both are high for a short period of time (overlap period),both
sampling pass transistors conduct and there is a direct path from the D input to a Q
output. So output change at the rising edge of clock, which is undesired for a negative
edge triggered register. This is called race condition.

11. Compare & Contrast synchronous design and asynchronous design.

Synchronous Sequential Circuit: Output changes at discrete interval of time. It is a circuit based
on an equal state time or a state time defined by external means such as clock. Examples of synchronous
sequential circuit are Flip Flops, Synchronous Counter.
Asynchronous Sequential Circuit: Output can be changed at any instant of time by changing the
input. It is a circuit whose state time depends solely upon the internal logic circuit delays. Example of
asynchronous sequential circuit is Asynchronous Counter.
12. Draw the schematic of dynamic edge-triggered register.

13. Design one transistor DRAM cell.

14. Define clock skew and clock jitter.

Clock skew: In reality clocks have some uncertainty in their arrival times that can cut into the time
available for useful computation is called clock skew.
Clock jitter: Temporal variations in consecutive edges of the clock signals;
modulation + random noise- Cycle-to-cycle (short-term) long term.
 15. List out the techniques used for low power logic design.
i. To reduce the dynamic power, supply voltage VDD is reduced.
ii. The transistors with minimum size can be used to reduce the capacitances.
iii. The power dissipation due to short circuit current is minimized by matching
the rise time/fall times of the input and output signals.
iv. Proper layout techniques are used to minimize routing capacitances.
16. Difference between latch and flip-flop.
Sl. No Latch Flip-Flop
A latch stores when the clock level is low and is
1 A Latch is Level-Sensitive
transparent when the level is high.
A FF stores when the clock rises and is mostly
2 A FF is edge triggered.
never transparent.

17. Draw the switch level schematic of multiplexer based nMOS latch using nMOS
only passtransistors for multipliers.

18. What is clocked CMOS registers.

The dynamic latch can also be drawn as a clocked tristate. Such a form is sometimes called

clocked CMOS (C2MOS) the output is driven through the nMOS and pMOS working in parallel.

C2MOS is slightly smaller because it eliminates two contacts.

19. Define sequential circuits.

A sequential circuit is an interconnection of flip-flops and gates. The gates by themselves constitute a
combinational circuit, but when included with the flip flops, the overall circuit is classified as a sequential circuit.

20.Define parallel processing.

Parallel processing is a term used to denote a large class of techniques that are used to provide simultaneous data-
processing tasks for the purpose of increasing the computational speed of a computer system. Instead of
processing each instruction sequentially as in a conventional computer, a parallel processing system is able to
perform concurrent data processing to achieve faster execution time.
 PART B

1. Explain the operation of master-slave edge based triggered register.

2. Describe in details about timing basics and clock distribution techniques in synchronous design.
3. Write Short notes on following
i.C 2MOS Register
4. Discuss in detail various pipelining approaches to optimize the sequential circuits.
5. Design D-Latch using transmission gate.
6. Discuss in detail various latches and registers.
7. Explain the Non bistable sequential circuits based on CMOS logic.
8. Give in detail about the various sources of clock skew and clock jitter.
9. Explain the different methods of clocking scheme.
10. Discuss in detail about synchronous design.
UNIT – IV INTERCONNECT, MEMORY ARCHITECTURE AND ARITHMETIC
CIRCUITS
PART -A
1. List of the components of data path
A Datapath consists of interconnection of combinational functions such as arithmetic
(addition, multiplication, comparison and shift) or logical ( AND,OR and XOR)
operations.
2. Give the application of high speed adder
Mainframe computer, servers, multimedia processors.
3. How to design a high-speed adder
In a high speed adder, a carry propagation delay is reduced by using carry bypass
adder or linear carry select adder or square root carry select adder or carry lookahead
adder.
4. What is latency
The latency is, time taken for to get a output in a register, after giving a input.
5. What is meant by bit-sliced data path organization
Data in a processor are operated in word-based manner. Datapath in microprocessor
are 32 or 64 bit wide. The signal processing data paths in digital Subscriber Line
(DSL) modems, magnetic disk drives, or compact-disc players are 5 to 24 bits wide.
A 32 bit processor operates on data words that are 32 bit wide. This is because the
same operation is performed on each bit of the data word. The Datapath consists of 32
bits slices and each operations on a single bit hence called bit-sliced.
6. Define a propagation delay for n-bit fast adders
The propagation delay for n-bit carry bypass adder is
tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum
The propagation delay for n-bit linear carry select adder is
tcarry=tsetup+Mtcarry+(N/M)tmux+tsum
The propagation delay for n-bit square root carry select adder is
tadd = tsetup + Mtcarry + (√2N)tmux + tsum
7. Why barrel shifter is very useful in arithmetic circuits
i. A barrel shifter is a digital circuit that can shift a data word by a specified
number of bits without the use of any sequential logic, only pure
combinatorial logic
ii. Barrel shifter performs a six operation, namely; logical right shift, logical left
shift, arithmetic right shift, arithmetic left shift, rotate right, rotate left
 iii. Propagation delay is constant and independent of the shift value.
iv. Layout size is not dominated by transistors.
8. Write the principle of fast multiplier
Fast multiplier is similar to manually computing multiplier operation. All the partial products
are generated at the same time and organized in an array, but in fast multiplier to compute a
final products a multi operand addition is used.
9. Define mirror adder
In a mirror adder, the realization of pMOS network is identical to nMOS rather than the
conduction complement. Thus, topology is called mirror adder.
10. Define DVS.
To obtain required throughput for high workloads and minimize energy for low workloads,
both supply and frequency must be dynamically varied according to the requirements
applications that is currently being executed. This technique is called dynamic voltage
scaling (DVS)
11. Write the principle of any one fast multiplier?
The Wallace tree has three steps:
i. Multiply each bit of one of the arguments, by each bit of the other, yielding n2 results.
ii. Reduce the number of partial products to two by layers of full and half adders.
iii. Group the wires in two numbers, and add them with a conventional adder.
12. Why we go to Booth’s algorithm?
Booth algorithm is a method that will reduce the number of multiplicand multiples. For a given number of
ranges to be represented, a higher representation radix leads to fewer digits.
13. What is latency?
Latency refers to time interval or delay when a system component is waiting for another systemcomponent
to do something. This duration of time is called latency.

14. Define accumulator.

An accumulator is a register in which intermediate arithmetic and logic results are stored. Without a
register like an accumulator, it would be necessary to write the result of each calculation (addition,
multiplication, shift, etc.) To main memory, perhaps only to be read right back again for use in the next
operation.
15. How CLA differ from RCA.

Sl. No CLA RCA

1. The carry look ahead adder (CLA) solves the In the ripple carry adder, the output is known
carry delay problem by calculating the carry after the carry generated by the previous
signals in advance, based on the input stage is produced.
signals.
2.
Thus, the sum of the most significant bit is
It is based on the fact that a carry signal will
only available after the carry signal has
be generated in two cases: (1) when both bits
rippled through the adder from the least
ai and bi are 1, or (2) when one of the two
significant stage to the most significant stage.
bits is and the carry-in is 1
As a result, the final sum and carry bits will
be valid after a considerable
delay.

16. What is meant by bit-sliced data path organization and what are the advantages of data
pathoperators?
A data path is a collection of functional units, such as arithmetic logic units or multipliers that perform
data processing operations, registers, and buses. Along with the control unit it composes the central processing
unit (CPU).
Control

Data in Data out

Multiplexer
Register

Shifter
Adder
Advantages:
To implement the logic function using n-identical circuits Data may be arranged to flow in one
direction, while any control signals are introduced in an orthogonal direction to the data flow.
17. List out the components of data path.
i. Register
ii. Adder
iii. Shifter
iv. Multiplexer
18. Give the applications of high speed adders.
Addition is one of the essential operations in Digital Signal Processing (DSP) applications which
include Fast Fourier Transform (FFT), Digital filters, multipliers etc. With the advancements in
technology, research is still going on to design a adder that performs addition in flash of time. One of
suchhigh speed adder is carry save adder (CSA).
19. Determine propagation delay of n-bit carry select adder.
tp = tsetup +M tcarry +(N/M)tmux + tsum
20. Why barrel shifter very useful in the designing of arithmetic circuits?
A common usage of a barrel shifter is in the hardware implementation of floating-point arithmetic.
For a floating-point add or subtract operation, the significant of the two numbers must be aligned.
 PART -B

1.Design a 16 bit carry bypass and carry select adder and discuss their features.
2.Sketch the structure of ripple carry adder and explain its operation. How the drawbacks in ripple
carry adder overcome by carry look ahead adder and discuss.
3.Design a 4X4 array multiplier and write down the equation for delay.
4. Give a note on 4X4 carry save multiplier.
5. Write a short note on Barrel shifter.
 UNIT – V ASIC DESIGN & TESTING
PART – A
1. What is meant by CBIC and standard cell?
Cell based ASIC or cell based integrated circuits(CBIC), which uses a predesigned
logic cells like AND gates, OR gates, multiplexers and flipflops.
Here the predesigned logic cells are known as standard cell. The standard cell are also
called as flexible blocks.
2. Name the elements in a configuration logic block
In general logic block consist of few logic cells, a typical logic cell consists of LUT
(Look Up Table), a full adder and a D-type flip flop.
3. What are the feed through cells? State their uses
 In a cell-based ASIC, a connection that needs to cross over a row of
standard cells uses a feedthrough.
 Feedthrough is a piece of metal used to pass a signal through a cell.
4. State the features of full custom design
 Some (possibly all) logic cells that are customized.
 All mask layers that are customized.
 Manufacturing lead time is typically eight-weeks.
 Needs less area and low power consumption
5. Compare full custom with semi-custom
Full Custom Semi-Custom
All the logic cells and masks are All the logic cells are predesigned, and
customized some of the mask layers are customized.
Increased manufacturing and design time Less Time.
Highly complex in design system. This uses cell library so Easier design
Process
Example- microprocessor Example – FPGA, PLD

6. What is ULSI?
Ultra Large Scale Integration (ULSI) is a process of embedding a million of transistor
with in a single chip.
7. What are the various ways of routing procedure.
Routing architecture comprises of programmable switches and wires. Routing
provides connection between I/O blocks and logic blocks, and between one logic
block and another logic block.
 General purpose programmable interconnect
 Direct interconnection between adjacent CLB,s
 Long Line Interconnects.
8. Define ASIC?
Application Specific Integrated Circuits (ASIC) is an integrated circuit designed for a
special purpose application.
9. What is antifuse?
 An Antifuse is an electrically one time programmable two-terminal
device with small area and low parasitic resistance and capacitance.
 An antifuse is normally high resistance (>100MΩ). on application of
appropriate programming voltages, the antifuse is changed permanently to
a low-resistance structure(200- 500Ω)
10. Compare channeled gate array and channel less gate array

Channeled gate array Channel less gate array

Only the interconnect is Only the top few mask layers are
customized Customized
The interconnect uses predefined No predefined areas are set aside for
spaces between rows of base cells routing between cells
Routing is done using spaces Routing is done using the area of
transistors unused
Logic density is less Logic density is higher
11. Compare antifuse and SRAM

Antifuse SRAM
One time programable device SRAM bits can be programmed many
Times
Consume lesser area FPGA consumes extra area
Low delay, high speed Very high delay
12. Define FPGA
 Pre-fabricated silicon devices that comprise of an array of uncommitted
circuit elements (logic blocks) and interconnect resources
 An IC designed to be configured at laboratory by end-user after manufacturing
 13. What is macros.
The logic cells in a gate array library are called macros

14. Differentiate between channeled and channel less gate array.

SL.
Channeled Gate Array Channel less Gate Array
No
Only the top few mask layers are
1 Only the interconnect is customized
customized
The interconnect uses predefined No predefined areas are set aside for
2
spaces between rows of base cells routing between cells.
Routing is done using the area of
3 Routing is done using the spaces
transistors
4 Logic density is less Logic density is higher

15. Give the different types of ASIC and give the steps in ASIC
design flow.
Types of ASIC:
 Full custom ASICs
 Semicustom ASICs - Standard cell based ASICs, Gate-array based ASICs
 Programmable ASICs - Programmable Logic Device (PLD), Field
Programmable Gate Array(FPGA).
Steps in ASIC design flow:
 Design entry
 Logic synthesis system partitioning
 Prelayout simulation
 Floor planning
 Placement
 Routing
 Extraction
 Post layout simulation
16. What is FPGA and
VLSI? VLSI:
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by
combining thousands of transistors into a single chip.
FPGA:
A Field Programmable Gate Array (FPGA) is a programmable logic device that supports
implementation of relatively large logic circuits. FPGA can be used to implement a logic circuit with
more than 20,000 gates whereas a CPLD can implement circuits of up to about 20,000 equivalent gates.
 17. State the features of full custom design.
In a Full custom ASIC, an engineer designs some or all of the logic cells, circuits or layout
specifically for one ASIC. It makes sense to take this approach only if there are no suitable existing cell
libraries available that can be used for the entire design.
18. What is standard cell based ASIC design.
A cell-based ASIC (CBIC) uses predesigned logic cells known as standard cells. The standard
cell areas also called fle4xible blocks in a CBIC are built of rows of standard cells. The ASIC designer
defines only the placement of standard cells and the interconnect in a CBIC. All the mask layers of a
CBIC are customized and are unique to a particular customer.

19. What is an antifuse? State its merits and demerits.

An antifuse is normally high resistance (>100MΩ). on application of appropriate programming
voltages, the antifuse is changed permanently to a low-resistance structure(200-500Ω) .
20. Write the various ways of routing procedures.
 Global routing architecture
 Detailed routing architecture
 FPGA interconnect routing.
 PART -B
1.Briefly explain in detail about full custom and Semi custom ASIC with its
classification.

2. Discuss different types of programming technology used in FPGA design.

3.With the neat sketch explain the Basic building blocks of FPGA architecture.

4. Classify the types of FPGA routing techniques and explain.

5. Write short notes on routing procedures involved in FPGA interconnect.