Literature Survey on :

RISC Processor Architectures and

FPGA Implementation Techniques

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 1. Introduction :

Purpose of the Literature Survey

The primary objective of this literature survey is to conduct a comprehensive review of

approximately 40 scholarly papers that explore the implementation of RISC-V
architectures in various applications on Field-Programmable Gate Arrays (FPGAs). This
survey aims to:

1. Identify and Analyze: Review different RISC-V processor implementations on

FPGAs, examining their architectural variations and design choices.
2. Evaluate Applications: Understand the range of applications where RISC-V on
FPGA has been effectively utilized, focusing on performance metrics, scalability,
and adaptability.
3. Highlight Optimization Techniques: Explore state-of-the-art optimization
strategies employed in these implementations to enhance performance, power
efficiency, and resource utilization.
4. Identify Research Gaps: Pinpoint areas where current research is lacking or
where further investigation could lead to significant advancements in the field.

By synthesizing the findings from these papers, this survey aims to provide a detailed
understanding of the current state of RISC-V implementations on FPGA, offering
insights into potential future research directions and innovations.

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Overview of RISC Processor Architectures :
- Basic Concepts

RISC (Reduced Instruction Set Computer) architecture is a type of microprocessor design that
focuses on a simplified set of instructions. The primary goal of RISC is to increase the efficiency
of the processor by using a small, highly optimized set of instructions that can be executed
rapidly. Unlike Complex Instruction Set Computers (CISC), which use a wide variety of complex
instructions, RISC architectures rely on a few simple instructions that are designed to be
executed in a single clock cycle. This simplicity allows for faster processing, easier pipelining, and
more efficient use of processor resources .

- Comparison of Architectures :

MIPS ARM RISC-V

 Architecture: MIPS  Architecture: ARM  Open-Source Nature:
(Microprocessor without (Advanced RISC Machine) is RISC-V is a modern, open-
Interlocked Pipeline Stages) is one of the most popular RISC source RISC architecture that
one of the earliest and most architectures in the world, has gained significant
influential RISC architectures. known for its power efficiency attention for its flexibility and
It is known for its clean and and performance. ARM extensibility. Unlike other
straightforward design, which processors are designed with a proprietary architectures,
makes it easy to implement load/store architecture, where RISC-V is free to use,
and scale. operations are performed in allowing for widespread
registers and memory access is experimentation and
 Pipeline Stages: MIPS limited to specific instructions. customization.
typically uses a five-stage
pipeline: Instruction Fetch  Instruction Set: ARM uses  Extensibility: RISC-V’s
(IF), Instruction Decode (ID), a reduced instruction set, with modular design allows for the
Execute (EX), Memory a focus on conditional addition of custom
Access (MEM), and Write execution, a large number of instructions, making it highly
Back (WB). This pipelining registers, and efficient adaptable to different
allows for instruction-level handling of interrupts. applications. This extensibility
parallelism, improving is particularly advantageous
throughput.  Widespread Adoption: for specialized computing
ARM processors dominate the tasks.
 Use Cases: MIPS has been mobile and embedded systems
widely used in academic market, powering a majority  Current Developments:
settings for teaching processor of smartphones, tablets, and RISC-V is rapidly evolving,
design due to its simplicity. It IoT devices. Their low power with ongoing developments in
has also been used in consumption and high both hardware and software. It
embedded systems, routers, performance make them ideal is being adopted in a variety of
and gaming consoles. for battery-operated devices. fields, including academia,
industry, and research, for
everything from simple
microcontrollers to complex
multi-core processors.

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Key Features

RISC architectures share several common features that contribute to their efficiency and
effectiveness:

 Pipelining: Most RISC architectures utilize pipelining to improve instruction

throughput. By breaking down the execution process into multiple stages,
pipelining allows multiple instructions to be processed simultaneously, increasing
overall performance.
 Load/Store Operations: RISC architectures typically separate memory access
from computational operations. This means that data must be loaded into registers
before any arithmetic or logical operations are performed, which simplifies the
design and enhances execution speed.
 Simplicity in Instruction Sets: RISC architectures are designed with a
minimalistic approach to instruction sets. This simplicity reduces the complexity
of the control unit and allows for faster instruction decoding and execution.

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FPGA Implementation Techniques for RISC
Processors:
Implementation Strategies :

a. Soft Processors

 Soft-Core Processors: Soft processors are processor cores that are implemented entirely
using the programmable logic blocks of an FPGA. Examples of soft processors include
Xilinx's MicroBlaze and Intel's Nios II. These processors are designed as IP (Intellectual
Property) cores that can be instantiated and customized within the FPGA's fabric.
 Integration into FPGAs: Soft-core processors like MicroBlaze and Nios II are tightly
integrated into the FPGA design ecosystem. They allow for the easy addition of custom
peripherals, memory controllers, and other hardware components directly in the FPGA.
This integration offers a high degree of flexibility, as designers can modify the
processor’s architecture to meet the specific needs of their application, such as adding
specialized instructions or optimizing for a particular performance metric.
 Use Cases: Soft processors are often used in embedded systems where the flexibility of
reprogramming the processor's functionality is essential. They are also popular in
research and development environments, where rapid prototyping of new processor
designs is required.

b. Custom RISC Implementations

 Custom RISC Processors on FPGA: Beyond soft-core processors, FPGAs are also used to
implement fully custom RISC processors. Designers can create a RISC processor from
scratch using hardware description languages (HDLs) like VHDL or Verilog. This approach
allows for complete control over the processor's architecture, including the instruction
set, pipeline design, and memory hierarchy.
 Flexibility: Implementing custom RISC processors on FPGAs offers unparalleled
flexibility. Designers can experiment with different architectural features, such as
varying the number of pipeline stages, introducing parallel execution units, or adding
specialized functional units. This flexibility is particularly valuable in research settings,
where novel processor designs need to be tested and refined before they are potentially
fabricated as ASICs.
 Challenges: While custom RISC implementations provide great flexibility, they also
present challenges, such as increased design complexity and the need for thorough
verification. Designers must carefully manage the FPGA's resources, such as logic
elements, memory blocks, and I/O pins, to ensure the processor functions correctly and
efficiently.

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Case Studies

• Case Study 1: IOT Applications :

 Design Choices: The Arnold SOC, built on a RISC-V architecture, offers a flexible and
energy-efficient solution for IOT end nodes. With custom instruction extensions and an
embedded FPGA, it achieves significant performance improvements (3.4× better
performance and 2.9× better energy efficiency) while maintaining low power
consumption, making it ideal for processing data from various sensors and executing
complex algorithms in real-time
 Outcomes: The flexibility of FPGA allows for rapid iteration and optimization of the RISC-
V design. Studies have shown that RISC-V processors on FPGAs can achieve high
performance while maintaining low power consumption, making them suitable for IoT
applications.

Case Study 2: Digital Signal Processing Applications

 The RISC-V processor designed for DSP applications demonstrated significant

performance advantages, executing tasks with 20x fewer clock cycles compared to the
ARM Cortex-A9 processor.
 Outcomes:

- Operating at a frequency of 16 MHz, the RISC-V processor achieved an

execution time of 14.11 µs, while the ARM processor, running at 100 MHz, took
45.7 µs.
- This efficiency highlights RISC-V's potential for high-speed processing in DSP
applications, making it a compelling choice for real-time signal processing tasks.
- Compared to ARM, RISC-V's optimized floating-point unit (FPU) reduces latency
and enhances throughput, resulting in faster processing times and improved
performance in DSP applications.

Case Study 3: Encryption Applications

 Design Choices: RISC-V's Galois Field (GF) Instruction Set Architecture (ISA) extension
significantly enhances cryptographic performance. It accelerates both classical
cryptographic algorithms like AES (Advanced Encryption Standard) and elliptic curve
cryptography, as well as post-quantum cryptographic algorithms like Classic McEliece.
This extension provides up to a five-fold acceleration in processing these algorithms,
which is crucial for implementing secure communications in portable devices. The
flexibility of the RISC-V GF ISA extension allows it to handle both error-correction codes
and cryptographic tasks efficiently with minimal increase in hardware utilization

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Outcomes:

- The custom ISA design results in a significant reduction in clock cycles

required for executing Galois field arithmetic, achieving up to 80% fewer
cycles for certain algorithms.
- Logic utilization increases slightly (1.27% for variant one and 2.21% for
variant two), indicating efficient use of resources while enhancing
performance.
- The design maintains a maximum operating frequency of 25 MHz without
frequency degradation, ensuring reliable operation on the Nexys A7 FPGA

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Potential Contributions

1. Innovation Opportunities

The intersection of RISC processors and FPGA technology offers numerous opportunities
for innovation:

 Architectural Designs: Developing RISC architectures optimized for FPGA can

lead to powerful, adaptable processors, particularly in DSP and encryption
applications.
 Implementation Techniques: Optimizing RISC implementations on FPGAs can
enhance performance and efficiency, enabling faster data processing and more
secure encryption.
 Optimization Strategies: Leveraging FPGA features like parallelism and
reconfigurability can improve DSP operations and cryptographic performance,
leading to more efficient and secure systems.

2. Industry Impact

Your research could significantly impact several industries:

 Embedded Systems: Enable more efficient and adaptable processors for complex
tasks, including DSP and encryption.
 High-Performance Computing (HPC): Develop custom accelerators for better
data processing and secure communication.
 Digital Signal Processing (DSP): Enhance real-time performance in audio,
video, and telecommunications applications.
 Encryption and Cybersecurity: Create faster, more secure cryptographic
methods for data protection.
 Telecommunications and Networking: Improve high-throughput, low-latency
equipment for 5G and cloud computing.
 Internet of Things (IOT): Design power-efficient processors for secure, real-
time data transmission in IOT devices.

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 References :

- Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes
- A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing
- Design of RISC Processor with IEEE754 Standard Floating-Point Instruction Set in FPGA
using VHDL for Digital Signal Processing Applications
- HW/SW implementation of RSA digital signature on a RISC-V-based System-on-Chip
- RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical
and Post-Quantum Cryptography