Reconfigurable RISC-V Secure Processor And SoC

Integration
Zhenya Zang Yao Liu Ray C.C. Cheung
City University of Hong Kong City University of Hong Kong City University of Hong Kong
Kowloon Tong, Hong Kong Kowloon Tong, Hong Kong Kowloon Tong, Hong Kong
Email: zzang2-c@my.cityu.edu.hk Email: liu.yao@my.cityu.edu.hk Email: r.cheung@cityu.edu.hk

Abstract—In IoT (Internet of Things) applications, security the IP protection, However, RISC-V is an open source ISA
issues are increasingly attracting attention. However, current (Instruction Set Architecture), and we can design the micro
embedded processors lack cryptographic protection mechanism. architecture as our preference and specific requirements. It is
In this paper, an austere RISC-V core processor with RV32I
subset instruction is deemed as a master device to cooperate with currently regarded as an architecture standard for educational
an AES cryptographic engine in an SoC, due to its openness and and industrial applications, and it has been comprised of a
flexibility. This core contains separate instructions and a data variety of modularized ISAs such as RV32I, RV32E, RV64I,
bus connected to a Wishbone crossbar. A Spartan-6 XC6SLX9 and non-standard ISAs. The RV32I subset indicates that it
board is taken as an architecture protocol verification platform, possesses of 32-bit addressing space, 32 integer instructions
where the peak operating frequency of the RISC-V core and
the encryption SoC is 105MHz and 111.5MHz, respectively. The and 32 GPRs (General Purpose Register), which is exactly
hardware resource utilization is reduced compared with the the work that this paper has finished. The RISC-V foundation
MIPS core with identical efforts provides these suits with compatible toolchains [2], by which
Index Terms—RISC-V, SoC, Security Processor, Wishbone C and assembly code can be both compiled to machine code.
However, this design consists of various register configura-
I. I NTRODUCTION tions, its therefore more efficient to program by using assembly
Nowadays IoT technology establishes connections among code. RISC-V instructions are modularized and extensible, so
sensors, mobile devices and vehicles, by which significant it has some reserved space for designers to design specific
traffic signal, humans health information and environmental accelerators that can be applied to the DSP domain, parallel
index can be collected and transferred. Some studies [22] show computing and some machine learning algorithms [3].
that the number of IoT devices will increase to 200 billions in In this paper, an efficient trade-off between resource over-
2020. Meanwhile, secure issue is critical to IoT applications. head and throughput is achieved, the first portion is to
In 2016, many servers of American server provider called implement an RV32I core with 5-stage pipelines based on
DYN company suffered an attack that results in a large-scale the MIPS core [4]. The peak operating frequency of the
network crash, many fields like payment, financial media and RV32I core is 105.1 MHz, and the Harvard memory access
social media cannot work properly. Therefore, the crucial is utilized. Furthermore, the simulation result is verified by
information should be secure from attackers, and security Modelsim software, and the bitstream is programmed on
approaches should be provided when sharing data. Spartan-6 XC6SLX9 board. The second portion is designing a
Besides, owing to the large amount of data, the com- cryptographic SoC with 111.5 MHz peak operating frequency
putational capability of devices in IoT systems should be based on the RV32I core. An AES IP core and UART
enhanced significantly. One project [1] shows that software- are utilized as an encryption engine and a communication
based methods cannot process big data with a high speed peripheral, respectively. The simulated cipher is verified a
and throughput, whereas hardware-based infrastructures can professionally cryptographic calculator, and hardware resource
implement sophisticated security computations effectively and utilization and synthesis information are reported by Xilinx
efficiently. FPGA (Field Programmable Gate Array) has an Synthesis Technology (XST) kit. In the next section, some
ample performance in terms of the parallel computing and related work is illustrated. The design details of the core and
reconfigurable feature. Therefore, in this article, FPGA is the SoC are depicted in section III. Section IV contains some
adopted as a platform to fabricate and verify a cryptographic performance evaluations. Consequently, section V concludes
SoC. the finished work.
As for the master microcontroller, hazards will be encoun- The main contributions of this paper are listed as follows:
tered when licensed ISAs or micro-architectures cost much • We design an RV32I softcore with 5-stage in-order multi-
money and cannot be modified and applied to different appli- cycle pipeline and loosely coupled individual instruction
cation scenarios if we use the IP (Intelligent Property) directly. and data Wishbone bus.
As we know, it is difficult to implement some modifications • We implement an extensible, programmable and integrat-
on a hardware level to x86 and ARM processor because of ed SoC with an AES-128 encryption engine and other

l-))) 

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 Fig. 1. RISC-V Core Micro Architecture

peripherals. TABLE I
• The performance evaluation shows the proposed work is RV32I ENCODING FORMAT [2]
R-Type func7 rs2 rs1 func3 rd opcode
of small overhead and high speed. I-Type imm[11:0] rs1 func3 rd opcode
S-Type imm[11:5] rs2 rs1 func3 imm[4:0] opcode
II. RELATED WORK U-Type imm[31:12] rd opcode
In academia domain, there are various soft processors pro-
totypes providing security mechanism on FPGA. For example, taken as an encryption engine to encrypt the data transformed
An FPGA based IoT device [1] prevents FPGA bitstream through the SoC.
from being cracked. And the system image of it is encrypted III. DESIGN DETAILS
to strength the system security. Additionally, a single-chip
processor [5] advanced a secure processor model that im- A. RISC-V (RV32I) core
plemented an AES engine, a TRNG (True Random Number The processor core consists of 3 top-level modules RV32I
Generator) and a memory integrity tree on the openSPARC core, IROM (Instruction ROM) and DRAM (Data RAM).
FPGA platform to improve the security of this soft processor. RV32I consists of 47 instructions that also contain sever-
However, it can be deemed as a tightly-coupled architecture al SCALL/SBREAK/CSR instructions that makes hardware
and relies on the specific platform, thus it might be not implementation more integrated. However, it increases the
compatible when utilized in other platforms. complexity of implementation, and these instructions are not
As for the soft processor, there are some existing lightweight essential to this project. Hence, this RV32I core includes 38
RISC-V cores currently, such as Z-scale [6] from Berkeley, instructions in total. There are 32 registers in the register file
ORCA [7] from Vectorblox company, and so on. The Z- that is indexed from 0 to 31. It has 32 GPRs apart from 0th,
scale is a three-stage in-order pipeline soft processor written because it is hardwired to constant 0, which resembles MIPSs
in chisel and resembles in application scenarios to ARM register principle. RV32I base instruction set mainly includes
Cortex series to target embedded systems design. Therefore, four instruction formats namely, R, I, S, and U, as shown in
it is not the appropriate processor to be fabricated for FPGA TABLE I. Every instruction is fixed in 32 bits, and memory is
framework. For the ORCA processor, it is written in VHDL aligned in every four bytes boundary. The required GPRs index
HDL (Hardware Description Language), and its initial aim is are placed in the fixed position. Therefore, it is convenient for
to cooperate with some commercial processors of this vendor, instruction decoder to decode the index of the corresponding
thus it is not customizable for a secure processor. To sum up, register and then access to register file. Fig. 1 describes the
a compatible and lightweight processor should be designed for data and control signal path in the architecture, the decode
different purposes. In this paper, a general purpose lightweight unit has three types of input signals that are opcode with
RV32I core is implemented. Moreover, an AES IP core is index [6:0], funct3 code with index [14:12] and funct7 code



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 Fig. 4. Configuring IROM experiment flow
Fig. 2. Elements allocation in MIPS Fig. 3. Elements allocation in RISC-
IROM [4] V IROM

with index [31:25]. Therefore, instructions and control signals

can be decoded by these codes sequentially. Meanwhile,
corresponding type of immediate value is identified namely,
I, S, SB ,U, UJ. The Imme handler module in the decoding
stage encompasses shift registers to shift U-type immediate
data of U-type instructions. In addition, it also signs and
extends the immediate value of S and I type instructions. Due
to the immediate value divided into two sections in S type Fig. 5. Decoding procedure
instructions, immediate data in a I type instruction contain code. Whereas hardware cannot recognize assembly code
one segment. Hence, they can be distinguished by this factor. directly. Thus, a classical verification flow should be
The ALU Src signal outputted by decode unit determines the utilized in this portion. As Fig. 4 indicates, in Linux OS,
arithmetic in the execution stage, PC Src signal controlling the a set of toolchain provided by official RISC-V foundation
multiplexer in instruction fetching stage is responsible to select can debug every subset of RISC-V (RV32E, RV64I,
the address delivered from memory accessing and decoding etc) assembly code and convert it into a binary file,
stage according to load/store or branches instructions. it can be converted to hexadecimal code by a simple
The space of single port ROM utilized as an instruction script afterward. Additionally, implementing a makefile
memory can be 4GB theoretically, but 64KB is adequate for can make the test automated.
simulation experiment. Similarly, the space of the single port 2) Instruction Decode: Due to the limited paper space,
RAM is also 64KB. And the register file is implemented only logical instruction decoding is illustrated in this
as 32 registers with 32-bit depth and contains 4 input, 2 subsection, and other types of instructions (arithmetical
output and 1 selection signals namely, ReadReg1 receiving instructions, shift instructions, load/store instructions, etc)
fetched instruction data (rs1) with index [19:15], ReadReg2 are similar with it. Logical instructions mean integer
receiving fetched instruction data (rs2) with index [24:20], and register-register type (R-type). The precondition to de-
the data written to WriteReg with index [11:7] (rd) and the code instruction is to judge the type of the instruction.
WriteData decided by a multiplexer depending on the type of The index of opcode is [6:0], based on which decoder
the instruction. can identify the instructions category. According to the
1) Instruction Fetch: This mechanism is similar to the MIPS RV32I manual [2], we can confirm the operation code
architecture. When the IROM is disabled, the program of logical instructions is 0110011. To further identify
counter register holds in zero. When it is enabled, a the specific instruction, the decoder should check funct3
dedicated adder drives the program counter to increase index [14:12]. But instructions in [14:12] (SRL, SRA,
by 4 each cycle to deliver the next instructions address ADD and SUB) are identical. Hence, the decoder must
to IROM. But the most significantly different portion is check funct7 index [31:25] to distinguish them. Fig.
that the byte order of MIPS is a big-endian mode [4], 5 briefly shows the strategy of decoding these logical
while RISC-Vs is a little-endian mode that means high instructions.
bytes of data are stored in high address in memory, and 3) Instruction Execution: According to the decoded result,
low bytes of data are stored in low address in memory. the ALU (Arithmetic Logical Unit) identifies the type of
Therefore, when instructions are fetched from IROM, arithmetic and two operands (source registers index or
bytes positions should be reallocated. Fig. 2 and Fig. 3 immediate value) and executes corresponding operations.
illustrate the instructions address and elements positions 4) Memory Access: At the execution stage, the target ad-
in IROM of MIPS and RISC-V respectively. In order dress of the accessed memory is calculated, based on
to verify the validity of every proceeding conveniently whose lower two bits a selection signal with four-bit
during the design process, the simulation result should be width can be decoded to select the segment of expected
verified frequently. Therefore, applying initial keywords and sign-extended data in DRAM. For example, for
in Verilog code to simulate an array to store the content lb instruction, Assume parameter mem addr i (32-bit)
of instructions is more efficiently than leveraging a ROM is the target address calculated at execution stage and
IP core directly. Currently, every generic version RV32I mem sel o (4-bit) is the selection signal. If the lower
written in Verilog RTL code can be tested in assembly two bits of mem data i is 01, the corresponding selec-



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 TABLE II
ASSEMBLY CODE TESTCASE AND CORRESPONDING HEX
CODE, EXPECTED RESULT
Assembly Code Hexadecimal Code Expected Result
lui x1, 0x20000 200000b7 x1=0x200000000
ori x1,x1,0x100 1000e093 x1=0x200000100
lui x2, 0x30000 30000137 x2=0x300000000
add x3, x2, x1 001101b3 x3=0x500000100
addi x3,x3, 0xf 00f18193 x3=0x50000010f
sub x3, x3, x2 402181b3 x3=x020000010f
lui x1, 0xf0000 ffff00b7 x1=0xfff00000
Fig. 6. Operation forward handles data hazard slt x2, x1, x0 0000a133 x2=0x00000001
sltu x2, x1, x0 0000b133 x2=0x00000000
lui x1, 0x00001 000010b7 x1=0x00001000
slti x3,x1, -0x500 b000a193 x3=0x00000000
sltiu x3,x1,-0x500 b000b193 x3=0x00000001
ori x4, x0, 0x123 12306213 x4=0x00000123
sw x4, 0x0(x0) 00402023 x4=0x00000123
ori x5, x0, 0x123 12306293 x5=0x00000123
lui x4, 0x0 00000237 x4=0x00000000
lw x4, 0x0(x0) 00002203 x4=0x00000123
beq x4, x5, label 00520263
label:
ori x5, x0, 0x0 00006293 x5=0x00000000

Fig. 7. Load hazard leads to a programming mistake

tion signal is 4b0100, and the expected section of data

provided by data memory is [16:23] data. Fig. 8. Simulation results in the Modelsim environment
5) Write Back: The input write enable signal of write encountered during the entire process. This issue can
back module delivered from MEM/WB pipeline stage be addressed by modifying register file module. When
is directly connected to the register file to enable write two input reading register ports are read, a conditional
register port, write address and write value. statement needs to judge that if the register is the one
6) Pipeline Hazard Handling Methodology: For the 5-stage that is read in the current clock cycle and will be written
pipeline in this soft core, registers are merely written in into value in the next clock cycle, then the written data
write back stage. Thus, we can know that all processes is considered as the output data directly.
of instructions are not relevant to WAW (Write-After- 7) Control Unit: The input signal of control unit generated
Write). On the other hand, registers would be accessed by decoding stage is sometimes related to a load instruc-
in the decoding stage, so WAR (Write-After-Read) hazard tion hazard, which denotes that load instructions would
does not exist in the entire process. Therefore, only read data from the data memory at memory access stage,
the RAW (Read-After-Write) condition should be put meanwhile the latest value written into GPR is also at
into consideration. For the adjacent instructions and two memory access stage. Concurrently, a branch instruction
instructions with an interval instruction, three measures is processed in executing stage. It has compared two
can be adopted to address this issue namely, pipeline registers at the last clock cycle and judge whether to
bubbling, compiler scheduling and operand forward. For generate a branch address. Obviously, the written register
pipeline bubbling, it would lead to a remarkable descend is not the expected value that load instruction intends to
to operation frequency, and compiler scheduling cannot load. Therefore, there is a load hazard, an instance is
be realized by HDL. Hence, operand forward is the most shown in Fig. 7. A load hazard condition can be explained
efficient measure to address the RAW hazard. Once a if the current instruction is a load instruction, and its
RAW hazard is encountered, the calculated result would target register is also the one that will be read in the
be sent to the place directly where other instruction needs next instruction from reading ports in register files. To
or other functional modules require it to avoid suspend- handle this issue, a conditional statement to distinguish
ing the pipeline and impacting the operation frequency load instructions should be executed in decoding stage to
negatively. produce a pipeline suspension.
Additionally, data hazard will occurs when two instruc- 8) Validity Verification: Up to now, an RV32I core has
tions have two in-between instructions (occurs at de- been basically completed, then the validity of various
coding and memory access stages) as shown in Fig. instructions should be verified in this portion. As subsec-
6, which means in the same clock cycle, the first in- tion 1) indicated, the FPGA can only recognize machine
struction is executing write-back task, while the fourth code in design and verification stage. In this subsection,
one is executing decoding process. Therefore, the value some logical instructions, arithmetical instructions, shift
written back in first instruction is incorrectly decoded instructions, branch instructions and load/store instruc-
in the fourth instruction, thereby data hazard will be tions are integrated into with an assembly code file that



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 TABLE III
ADDRESSING SPACE OF EVERY SLAVE MODULE

Name of Slave Devices Addressing Space

UART 0x00000000 0x0FFFFFFF
GPIO 0x10000000 0x1FFFFFFF
AES Encryption IP 0x20000000 0x2FFFFFFF
BROM 0x30000000 0x3FFFFFFF
BRAM 0x40000000 0x4FFFFFFF

TABLE IV
ADDRESSING SPACE AND DEFINITIONS OF REGISTERS IN AES
IP CORE INTERFACE Fig. 9. SoC overview diagram

Name of Addressing
register space
Bit width Description IP core should be leveraged [15]. The registers of plain text,
Base+0x24 ciphertext, encryption key and control unit should be identified
Input 32 Store plain text
to Base+0x30 in the interface in order to be configured by assembly code
Base+0x14
Key
to Base+0x20
32 Store key conveniently. The corresponding functions and addresses of
Base+0x4 registers in AES IP core interface are defined in TABLE IV.
Output 32 Store cipher
to Base+0x10 All the processed data transferred by the interface on the SoC
Control Base+0x0 32 Enable en/decryption should be configured by executing assembly code of the RISC-
V soft core.
is presented in TABLE II. After being converted into the
hexadecimal code, it can be fetched by a program counter. The AES IP core is defined as a slave device with a base
In TABLE II, we can see the corresponding hexadecimal address 0x30000000. Hence, all registers in this module take
code of this assembly code and calculated results written 0x30000000 as the base address when executing addressing
back to w data and w addr ports in the register file. task. The data input register is 32-bit width that is used to
From Fig. 8, a portion of the simulated register index and store plain text or cipher, when the IP core executes encryption
expected results in Modelsim environment are presented and decryption processes. Due to the data width, plain text or
that are exactly same as the proposed results shown in cipher should be transferred four times through the Wishbone
TABLE II. crossbar. Therefore, its addressing space is from base+0x0 to
base+0x30 with a reset value 0x0. Besides, the key register is
B. Encryption SoC also a 32-bit width register that stores the encryption key and
In preceding sections, the IROM and DRAM are embedded provides it to the bus when AES should execute encryption and
in the processor core. However, in practical applications, due decryption operations. Moreover, the most significant register
to the large boot program volume, the IROM cannot be in this module is the command control register, 1st bit of
embedded in FPGA simply but utilizing external resources like the control register refers to the enable signal driving AES
flash and SDRAM (Synchronous Dynamic Random Access module to get the information, if the AES core gets ready
Memory). In this SoC design, we implement a SoC prototype and loads anticipated plaintext or cipher into the data input
that contains a single port block ROM and a single port block register. The 3rd bit is responsible to decide if AES module
RAM taken as IROM and DRAM respectively. Designers can should execute encryption or decryption operation, TABLE V
change the depth by revising the macros. External memory introduces functions of the control unit register.
can be leveraged according to the specific requirement as
long as the module is compatible with Wishbone bus interface
specification. Owing to the fact that the storage structure IV. PERFORMANCE EVALUATION
is a Harvard architecture, the RISC-V core has individual
instruction and data interfaces that occupy two master ports A. RISC-V(RV32I) Core Properties
on the Wishbone bus. Fig. 9 generally shows the structure
of the SoC. The UART controller, the GPIO controller, the In terms of the timing performance and resource usage con-
AES controller, the BROM interface and BRAM interface dition of the RISC-V core, we can obtain the information from
are connected to their respective slave ports. To sum up, the Xilinx synthesis report after translating, mapping and lay-
addressing space of every slave device is described in TABLE out. The peak operating frequency of this core is 105.108MHz
III. In preceding RISC-V core design, the fetched address of running on SPARTAN-6 XC6SLK9 FPGA board, and the
the first instruction is 0x00000000, whereas the first instruction hardware resource utilization rate is much less than the MIPS
address in SoC should be 0x30000000, because BROM is core with the identical characteristics like supporting 32-bit
working as a slave device and its initial addressing space is integer computation and containing 32 GPRs. TABLE VI
0x30000000. Thus, a slight amendment of program counter presents the hardware utilization and peak operating frequency
module should be done. Another issue is that the input and information comparisons between MIPS and RISC-V core, the
output port of this IP core is not compatible with the Wishbone DFF mainly contributes to the area overhead. Therefore, the
crossbar bus, so an interface between Wishbone bus and AES RV32I core has a satisfactory performance of low overhead.



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 TABLE V for different encryption strength and situations as long as the
REGISTERS IN CONTROL UNIT interface is compatible with the Wishbone crossbar. In addition
Bit Index Description Reset Value to that, most IoT sensors communication specifications are I2C
31:0 Reserved 0x0
and SPI, so these peripherals can be implemented on it, and the
0:Execute encryption task
2 0x0 data transferred by them can be encrypted as well for diverse
1:Execute decryption task
0:Not ready to receive data applications.
1 1:Ready to receive data and load it 0x0 R EFERENCES
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