21ECC101J

Electronic system and PCB design

Unit 1
 Unit 1

Sl No. Topic References Page No.

1 Classifications of Semiconductor, Doping in Semiconductors 1 15-19

Conductivity of semiconductors, Energy Distribution and
2 1 28-33
Fermi level
Carrier Concentration in intrinsic semiconductor and Mass-
3 1 29-34
Action Law, Problem Solving techniques
Drift and Diffusion Current, Einstein Relationship for
4 2 1.13-1.16
semiconductors

5 Basic PN junction and applications 2 1.30-1.34

4.1- 4.15 and
6 Bipolar junction transistor and MOSFETs 2 & Boylestad
396-407
7 Challenges for Nano MOSFETs (Scaling Issues) 1 195-199

8 SOI MOSFET and Double gate MOSFET (Working Principle) 1 & Internet 212-213

9 FinFET and IGFET (Basic Concept) Internet

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Classifications of Semiconductors
• Materials having an electrical conductivity value falling
between that of a conductor, such as metallic copper,
and an insulator, such as glass.
Electrical conductivity
• The highest occupied energy band is
called the valence band.
• Most electrons remain bound to the
atoms in this band.
• The conduction band is the band of
orbitals that are high in energy and are
generally empty.
• It is the band that accepts the electrons
from the valence band
• The “leap” required for electrons from the
Valence Band to enter the Conduction
Band.
Types of semiconductors
Intrinsic Semiconductor
• A crystal of pure and regular lattice structure is called
intrinsic semiconductor.

⮚ each silicon atom has four

valence electrons
⮚ two valence electrons from
two silicon atoms form the
covalent bond
⮚ Be intact at sufficiently low
temperature
⮚ Be broken at room
temperature
Free Electrons and Holes
⮚Free electrons are
produced by thermal
ionization, which can
move freely in the
lattice structure.

⮚Holes are empty

position in broken
covalent bond, which
can be filled by free
electron, positive
charge
Creation of Electron and hole in a semiconductor

Current Conduction in semiconductor

Extrinsic Semiconductor
• The conductivity of semiconductors improved by
introducing a small number of suitable replacement
atoms called IMPURITIES.
• The process of adding impurity atoms to the pure
semiconductor is called DOPING.
• Usually, only 1 atom in 107 is replaced by a dopant atom
in the doped semiconductor.
• An extrinsic semiconductor can be further classified into:
• N-type Semiconductor
• P-type Semiconductor
N-type Semiconductor
⮚ A silicon crystal doped
by a pentavalent
element. (phosphorus or
arsenic)
⮚ Each dopant atom
donates a free electron
and is thus called a
donor.
⮚ The doped
semiconductor becomes
n type.
P-type Semiconductor
⮚ A silicon crystal
doped with a
trivalent impurity.
(aluminum, boron)
⮚ Each dopant atom
gives rise to a hole,
and called acceptor
⮚ the semiconductor
becomes p type.
Difference between Intrinsic and Extrinsic
Semiconductor
 Mass Action Law
• Under thermal equilibrium the product of the free electron
concentration and the free hole concentration is equal to
a constant equal to the square of intrinsic carrier
concentration.

np = ni2
Conductivity of Semiconductor
J = J p + Jn
Jp = qpμ p E
Jn = −qn(−μn E)
J = qpμ p E + qnμn
E
J = q( pμ p + nμn )E
J ≡ σof.Ea
The conductivity The resistivity of a
semiconductor is semiconductor is
ρ≡
σ ≡ qpμ p + qnμn σ
1 16
Problems
Fermi level in an Intrinsic Semiconductor
Fermi level in an Extrinsic Semiconductor
Problems
Current Flow in Semiconductors
There are two mechanisms by which holes and free
electrons move through a silicon crystal.
• Drift
• The carrier motion is generated by the electrical field
across a piece of silicon. This motion will produce drift
current.
• Diffusion
• The carrier motion is generated by the different
concentration of carrier in a piece of silicon. The diffused
motion, usually carriers diffuse from high concentration to
low concentration, will give rise to diffusion current.
 Drift Current (IS)
⮚ When an electrical field (E) is applied to a
semiconductor crystal holes are accelerated in
the direction of E, free electrons are
repelled.
The flow of electric current due to the motion of the charge carriers under
The influence of an external electric field is called Drift Current

JDrift = J p Drift + J n Drift

J p Drift= qpμ p E A/cm2

Jn Drift = qnμn E A/cm2

JDrift = qpμ p E + qnμn E

JDrift = q( pμ p + nμn )E
JDrift ≡ σ .E
 Diffusion Current (ID)

• Carrier diffusion – is the flow of charge carriers from area of high

concentration to low concentration.
• It requires non-uniform distribution of carriers.
• Diffusion current – is the current flow that results from diffusion.
• Current flow due to mobile charge diffusion is proportional to the
carrier concentration gradient.
• The proportionality constant is the diffusion constant.
▪ Diffusion
Current
▪ Drift current IS = Jdrift A ; Due to electric field
▪ Diffusion current ID = Jdiff A ; Due to concentration gradient
 Einstein Relationship for semiconductors

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Applications of PN diode
Wave forms at various points in a Regulated power
supply
 Rectifiers
⚫Type of circuit used to convert AC voltage to DC voltage

⚫Half Wave Rectifier (HWR)

⚫Full Wave Rectifier (FWR)
⚫Bride Full wave rectifier
 Bi-polar Junction Transistor (BJT)
A BJT is a 3-termanl and two junctions semiconductor device that can be used in
amplification and switching. The name BJT can be justified as follows.
Bi-polar indicates the use of both electrons and holes in current
transportation
Junction signifies the existence of pn- junctions
Transistor is a contraction for transfer resistor
Due to the fact that there are two types of extrinsic semiconductors (p and n-type) and
existence of two junctions, BJT is of two types from the construction point of view.
npn transistor (p-type semiconductor sandwiched between two n-type
semiconductors)
pnp transistor (n-type semiconductor sandwiched between two p-type
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semiconductors) 43
 Idealised two dimensional view of a silicon pnp bipolar
transistor along with the circuit symbol.

Prospective view of a silicon pnp

bipolar transistor.
Idealised two dimensional view of a silicon npn bipolar
transistor along with the circuit symbol.
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 Transistor Biasing

Usually,

The emitter-base junction is forward

biased

The collector-base junction is reverse

biased

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 Transistor Operation (npn)

In NPN transistor, the arrow mark on the emitter is coming away from the base and represents the
direction of flow of conventional current. It is the direction opposite to the flow of electrons which are
the majority charge carriers in N-type semiconductor.
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 The emitter junction is forward-biased with emitter-base battery Veb. The collector junction is
reverse biased with collector-base battery Vcb.
The forward bias of the emitter-base circuit helps the movement of electrons (majority carriers) in the
emitter and holes (majority carriers) in the base towards the junction between the emitter and the
base. This reduces the depletion region at this junction.
On the other hand, the reverse bias of the collector-base circuit forbids the movement of the majority
carriers towards the collector-base junction and the depletion region increases.
The electrons in the emitter are repelled by the –ve terminal of the emitter-base battery. Since the
base is thin and lightly doped, therefore, only a very small fraction (say, 5% ) of the incoming electrons
combine with the holes. The remaining electrons rush through the collector and are swept away by the
+ve terminal of the collector-base battery.
For every electron – hole recombination that takes place at the base region one electron is released
into the emitter region by the –ve terminal of the emitter-base battery. The deficiency of the electrons
caused due to their movement towards the collector is also compensated by the electrons released
from the emitter-base battery.
The current is carried by the electrons both in the external as well as inside the transistor.
21ECC101J
Ie = I b + I c 47
 Transistor Operation (pnp)

In PNP transistor, the arrow mark on the emitter is going into the base and represents the direction of
flow of conventional current. It is in the same direction as that of the movement of holes which are
majority charge carriers in P-type crystal. 48
21ECC101J
The emitter junction is forward-biased with emitter-base battery Veb. The collector junction is
reverse biased with collector-base battery Vcb.
The forward bias of the emitter-base circuit helps the movement of holes (majority carriers) in the
emitter and electrons (majority carriers) in the base towards the junction between the emitter and the
base. This reduces the depletion region at this junction.
On the other hand, the reverse bias of the collector-base circuit forbids the movement of the majority
carriers towards the collector-base junction and the depletion region increases.
The holes in the emitter are repelled by the +ve terminal of the emitter-base battery. Since the base is
thin and lightly doped, therefore, only a very small fraction (say, 5% ) of the incoming holes combine
with the electrons. The remaining holes rush through the collector and are swept away by the -ve
terminal of the collector-base battery.
For every electron – hole recombination that takes place at the base region one electron is released
into the emitter region by breaking the covalent bond and it enters the +ve terminal of the emitter-
base battery. The holes reaching the collector are also compensated by the electrons released from
the collector-base battery.
The current is carried by the electrons in the external circuit and by the holes inside the transistor.

21ECC101J
Ie = Ib + Ic 49
 Modes of Operation
When a transistor is to be connected in a circuit, one terminal is used as an input terminal, the other
terminal is used as an output terminal, and the third terminal is common to the input and output.
Accordingly three configurations are possible as

1. Common-Base (CB) configuration

2. Common-Emitter (CE) configuration
3. Common-Collector (CC) configurations

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 Transistor characteristics - Common-Base
Transistor
Characteristics

Input Output
Characteristics Characteristics

Input Characteristics Output Characteristics

Describe the changes in input current with Plot between Output current ~ Output
the variation in the values of input voltage Voltage.
Output voltage is kept constant
Input current is kept constant
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 MOSFET
• Breakdown and low input impedance are the main disadvantage in case of BJT and FET.
• It is avoided by putting an insulating layer (SiO2) between Gate and channel.
• This creates a capacitor with channel and Gate as two sides.
• Depending upon channel type, MOSFET are divided in to types.

MOSFET

n-channel p-channel
MOSFET MOSFET

• Depending upon the basic mode of operation, MOSFET are divided in to two types,

MOSFET

Depletion type Enhancement type

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MOSFET MOSFET 52
 Enhancement type MOSFET

• The prospective view of an enhancement type MOSFET is shown in the figure.

• When no voltage is applied to the gate, the source-to-drain electrodes correspond to two p–n
junctions connected back to back and no channel exists between source and drain and hence no
current flows between them.
• The only current that can flow from the source to drain is the reverse-leakage current.

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 Enhancement type MOSFET

• When we apply a sufficiently large positive bias to the gate, the MOS structure is inverted so that a
surface inversion layer (or channel) is formed between the two n+- regions as shown in the figure.

• If a small drain voltage is applied, electrons will flow from the source to the drain (the
corresponding current will flow from drain to source) through the conducting channel.

• Thus, the channel acts as a resistor, and the drain current ID is proportional to the drain voltage. This
is the linear region, as indicated by the constant-resistance line in the right-hand diagram of the
figure below.

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 Enhancement type MOSFET

• When the drain voltage increases, eventually it reaches VDsat, at which the thickness of the inversion
layer xi near y = L is reduced to zero; this is called the pinch-off point, P (as shown in the figure
below).

• Beyond the pinch-off point, the drain current remains essentially the same, because for VD > VDsat,
at point P the voltage VDsat remains the same. Thus, the number of carriers arriving at point P from
the source or the current flowing from the drain to the source remains the same. This is the
saturation region, since ID is a constant regardless of an increase in the drain voltage.

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 Enhancement type MOSFET

• When the drain voltage increases, eventually it reaches VDsat, at which the thickness of the inversion
layer xi near y = L is reduced to zero; this is called the pinch-off point, P (as shown in the figure
below).

• Beyond the pinch-off point, the drain current remains essentially the same, because for VD > VDsat,
at point P the voltage VDsat remains the same. Thus, the number of carriers arriving at point P from
the source or the current flowing from the drain to the source remains the same. This is the
saturation region, since ID is a constant regardless of an increase in the drain voltage.

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 Enhancement type MOSFET
• For further increase in VD beyond VDSat, the channel length will decrease from L to L’ while
keeping the drain current constant as shown in the figure below.

• The drain and transfer characteristics of an n-channel enhancement type MOSFET is given as

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 Circuit symbols for depletion and enhancement type MOSFET
Depletion type MOSFET Enhancement type MOSFET

• In case of both depletion type and enhancement type MOSFET, the substrate is sometimes
internally connected to the source terminal, whereas in other cases a fourth lead (labeled SS) is
made available for external control of its potential level.
• Symbols in the upper panels represent MOSFETs with separate SS terminal and symbols in the
lower panel represents MOSFETs with substrate connected to source terminal internally.
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 Challenges for Nano-MOSFET (Scaling issue)

• Scaling down of MOSFET’s dimension has been a continuous trend since its inception
(1970).
• The gate length of MOSFET in the production of ICs has been scaled down at a rate of 13%
each year and will continue to do so in future.
• The benefits of scaling down the dimension are,
• Higher device density in an IC (smaller size).
• Smaller channel length improves the driving current (ID~1/L) and hence the device
performance.
• However, the reduction in the devices size invites the influences from the side regions of
the channel (i.e., source, drain and isolation edge).
• Therefore, the device characteristics deviate from those derived from gradual-channel
approximation for long channel MOSFETs.
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 Short channel effects – On threshold Voltage (VT)

• The threshold voltage (VT) estimated

considering gradual channel approximation
(long channel) remains essentially constant
for various drain-source voltages (VDS).
• That means the charges contained in the
surface depletion region of the substrate are
created solely due to the gate voltage and is
independent of the lateral fields from the
source and drain.
• However, when channel length reduced so
that the short channel effects are non-
negligible, the threshold voltage (VT) rolls off
differently for different VDS values as shown
in the figure.
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 Short channel effects – On threshold Voltage (VT)

• The threshold voltage roll-off can be explained by

the charge sharing model as shown in the figure
where it can be seen that some of the depletion
charge is balanced by the source and drain.
• Let us consider WDM as the maximum depletion
layer width below the channel. WD and WS, and YD
and YS are the vertical and horizontal depletion
layer width under source and drain respectively.
• Theoretically, for VD > 0, WD > WS and YD > YS .
However, for smaller VD we can assume that WS ~
WD ~ WDM.

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 Short channel effects – On threshold Voltage (VT)

• The channel depletion region overlaps with the

source and drain depletion regions. Thus, the
charges induced by the field created by the gate
bias can be approximated by those within the
trapezoidal region as illustrated in figure (c).
• The threshold voltage shift ΔVT is due to the
reduction of charge in the depletion layer from
the rectangular region to the trapezoidal region.
• For long-channel devices, the charge reduction
is smaller, since ∆ (Fig c) is much smaller than L.
• However for short channel devices, the charges
needed to turn on the device are dramatically
reduced, since ∆ is comparable to L.
• Therefore, the threshold voltage decreases with
decreasing channel length.
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 Silicon-on-Insulator MOSFET (SOI MOSFET)

• Figure shows a schematic diagram of an SOI CMOS built on silicon dioxide.

• Unlike a bulk CMOS, where the CMOS built on Si substrate, SOI CMOS is built on an
insulator typically SiO2. It has various advantages over Bulk CMOS.
• SOI-MOSFETSs isolation scheme is simple and does not require complicated well structure.
• The latch-up phenomenon inherent in bulk CMOS circuits is also eliminated.
• The parasitic capacitance in the source and drain regions can be significantly reduced with
the insulating substrate.
• Since a small volume of Si is available for electron-hole pair generation by radiation, the
radiation damage tolerance of SOI-CMOS is better over bulk CMOS. This property is
particularly important for space application.

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 Silicon-on-Insulator MOSFET (SOI MOSFET)

• Depending upon the thickness of the Si channel layer,

SOI can be classified in to two types,
• Partially depleted(PD) SOI-MSFET
• Fully depleted (FD) SOI-MOSFET
• PD-SOI uses a thicker Si channel layer so that the
depletion width of the channel does not exceed the
thickness of Si layer.
• Device design and performance of a PD-SOI are similar
to that of bulk CMOS with a major difference of
floating substrate used in SOI device.
• During device operation, a high field near the drain could induce impact ionization there and
majority carriers (holes in p-type substrate for an n-channel MOSFET) will be stored in the substrate
as there is no substrate contact to drain away the accumulated charges.
• Therefore, the substrate potential will be changed, which results in a reduction of the threshold
voltage which in turn, may cause an increase or a kink in the current-voltage characteristics as
shown in the figure. This float-body or kink effect is especially dramatic for n-channel devices,
because of the higher impact-ionization rate of electrons
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 Silicon-on-Insulator MOSFET (SOI MOSFET)

• Unlike PD-SOI MOSFET, Fully depleted-SOI uses a Si

layer thin enough so that the channel of the transistor
is completely depleted before threshold is reached.
• This allows the device to be operated at a lower
voltage.
• Therefore, FD-SOI is very attractive for low power
operation.
• In addition, the kink effect caused by high-field impact
ionization can be eliminated.
• However, the FD-SOI’s characteristics are sensitive to
variation in the Si thickness.
• Therefore, if an FD-SOI circuit is built on a wafer with
nonuniform Si thickness, its operation will be unstable.

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 Double gate MOSFET

• The double gate MOSFET is a useful form of MOSFET

which can provide some distinct advantages, especially
in RF applications.
• The second gate terminal is used to reduce the
feedback capacitance between input and output and
thus the amplifier becomes more stable.
• Both depletion and enhancement type double gate
MOSFET can be realized. The circuit symbols are
shown in the figure 2.
• The highly doped N middle block acts as the drain for
the first FET and source for the second FET.
• The gate oxide between gate and the channel is the
dielectric layer and the metal used for gate is
conductor and the channel is also conductor, so all
these three layers together form the capacitor.
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 Double gate MOSFET

• Thus the double gate MOSFET is like two capacitors

connected in series.
• Since the total capacitance connected in series is lesser
than the individual capacitance, DG-MOSFETs are used to
reduce the feedback capacitance at high frequencies.
• The characteristics plot of the DG-MOSFET is shown in the
figure-2. It can be observed that the transistor stays n the
active region when both the gate voltages are above
threshold value.
• Advantages
• Higher drive currents at lower supply voltage and
threshold voltage.
• Reduced channel and gate leakage current at off state
which saves power.
• Separate gate control on voltage saves power and chip
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area. 67
 FinFET
• The term “FINFET” describes a non-planar, double gate
transistor built on an SOI substrate, based on the single gate
transistor design. In contrast to planar MOSFET, the channel
b/w source and drain is build as 3D bar on top of the Si
substrate.
• The name has been derived from the fact that the structure,
when viewed, looks like a set of fins as shown in the figure.
• Depending upon the base(substrate) onto which it is fabricated,
FINFET are of two types
• Bulk FinFET
• SOI FinFET
• The gate of the FInFET is wrapped around (a wrap around gate)
te cFin like channel.
• The presence of gate on the both sides of the fin (thin channel)
enhances the control ability of the gate and provides better
electrical control of the channel, thereby reducing the leakage
current and suppressing the short channel effect..
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 FinFET
• For a single Fin structure the effective width (W) of the
transistor can be evaluated as follows.
• For double gate: W = 2*Fin Height Gate Length
• For tri-gate: W = 2*Fin Height + Fin thickness

Source
• Structure with multiple fins is also feasible. For multiple fins, the
effective width of transistor can be written as
• Weff = n*W
• Advantages:

Drain
• Better control over the channel
• Suppressed short-channel effects
• Lower static leakage current
• Faster switching speed Fin Height
Fin Width
• Higher drain current (More drive-current per footprint)
• Lower switching voltage
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• Low power consumption 69
 FinFET
• Disadvantages:
• Difficult to control dynamic Vth
• Quantized device-width. It is impossible to make
fractions of the fins, whereby designers can only specify
the devices’ dimensions in multiples of whole fins.
• Higher parasitics due to 3-D profile
• Very high capacitances
• Corner effect: electric field at the corner is always
amplified compared to the electric field at the sidewall.
This can be minimized using a nitrate layer in corners.
• High fabrication cost
• The drain characteristics plot for a typical FinFET is shown in
the figure.

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 IGFET (Insulated Gate Field Effect Transistor)

The junction field-effect transistor, or JFET, uses voltage applied across a reverse-biased PN junction
to control the width of that junction’s depletion region, which then controls the conductivity of a
semiconductor channel through which the controlled current moves. Another type of field-effect
device—the insulated gate field-effect transistor, or IGFET—exploits a similar principle of a depletion
region controlling conductivity through a semiconductor channel, but it differs primarily from the
JFET in that there is no direct connection between the gate lead and the semiconductor material
itself. Rather, the gate lead is insulated from the transistor body by a thin barrier, hence the term
insulated gate. This insulating barrier acts as the dielectric layer of a capacitor and allows gate-to-
source voltage to influence the depletion region electrostatically rather than by direct connection.

In addition to a choice of N-channel versus P-channel design, IGFETs come in two major types:
enhancement and depletion. So the depletion and enhancement type of MOSFETs discussed
previously are nothing but the IGFETs with SiO2 used as an insulating layer.

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