CHAPTER 13

INTEL 8086 MICROPROCESSOR

ARCHITECTURE, FEATURES, AND
SIGNALS
LEARNING OUTCOMES
Aterstucying this chapter, you will be able to
Intermal architecture of the
unit
understand
8086, which consists the following:
of an execution unit and a bS interface
Diferent general--purpose and
segment registers and their
Accessing of
addresses
instructions and data from the
memory usingfunctions
the segment and offset
Pin details of the 8086
.Functions of the maximum mode and minimum mode signals
13.1 INTRODUCTION
1078. Intel released its irst 16-bit
microprocessor, the 8086,which executes the
inetuctions at 2.5 MIPS (million instructions per second). The execution time for
instruction is 400 ns 1/MIPS =1/(2.5 >x 109). The 8086 can address 1 MB
I MB=220 bytes) of memory, as it has a 20-bit address bus. The width of the data
hns in the 8086 is 16 bits. This higher execution speed and larger
memory size
have enabled the 8086 to replace the smaller minicomputers in many applications.
Anofher feature in the 8086 is the presence of a small six-byte instruction queue
inwhich the instructions fetched from the memory are placed before they are
CXecuted.

32ARCHITECTURE OF 8086 hb l
The functional block diagram of the 8086 is shown in Fig.13.1. It is subdivided
Imto the following two units:
() An execution unit (EU), which includes the ALU, eight 16-bit general-
purpose registers, a 16-bit flag register, and a control unit.
bus interface unit (BIU), whichincludes an adder for address calculations,
instruction
four 16-bit segment registers (CS, DS, SS, and ES), a 16-bit
pointer (IP), a six-byte instruction queue, and bus control logic.
21 Execution Unit
he EU COnsists of eight 16-bit general-purpose registers-AX, BX, CX, DX,
,BP, SI, and DI. Among these registers, AX, BX, CX, and DX
can befurther
 register beanddivided 420
(V) (iv) while(iii) (1) ) used
DL,
SP: shifturotate
the and DX: executed
thedataused The usedstringCX/CL: instructions.
technique, ItBX: divide, adjustment AX/AL: DX BX MICROPROCESSORS
is has
respectively, to into
item count to also The the store
two DH CH RH Ak
The /O a DX
part instructions Temporary
register
device
SP is hold CX used BX andfollowing
AX 8-bit Fiags
of has when with input/output 8-bit datALbusUa
register the used to value the is register or AND
to Fig. B AL
address
shifted/rotated to be the ALregisters-AH or as
dividend indicates count used the refer
16-bit 13.1
or (REP/REPE/REPNE)
instruction
hold L0OP CL
istohelp special
is shown MICROCONTROLLERS
holds used Execution
(EuniU)t registersGeneral
the while da value hold of to (VO) data Functional
stack before part the the the th e functions: in
valuethe as Systemcontrol EU
executing of number while XLAT dataoffset operations, the during Fig. and
pointer tahe count block
division inaccumulator. 13.l. AL,
result when executing program diagram
is instruction. address the Bus
is the times of The BH
Used andINduring and memory and interfacing-123456KInstruction
queue
operation, the of general-purpose and of byteSisx Adder
to and the inexecution. the bits16 ES DS
It bits16
a the the LOOP a BL, 8086 unit
hold OUT location some is (BIU) Address
bus
used
shiftUrotateexecuting using
the It same CH bits20
is decimal bits16
instruction. th e In and
in
multiplicinatstiornuctionumber
n
offset also
instructions. in addition, System
Control Bus
code the look-up the the registers CL,
of and
ASCImultiply,
tim es has repeated memory. and
ad res usopered ation instructions.
of h ol
to useis
d d the to
be
abi each can DH

(vi) thsieg()
n (iv) W) operation instruction. status The
) Wate: Section
13.2.2.in in be or
fla gs The DIS T he the 64(vi) (vi) (i)
negative.
TF or SF 0SZF POston
Wie dter Ar0dd borrow PF CF of flags Bits KBstack Here,
the
memory instructions.
string
(rap logie zero, of the CF, marked
fla g the DI:
(sign (zero value (auxiliarynumber(parity (carry
subtraction The D14|DI3DI2|D11DIo memoryaddres fora and
ofinfssettructions. offset aSI:d res BP: duringregister
data
after
the result PF, in
the
register in the
term
instructionflag): flag):
flag): Z=1,
If in 0).
flag): CPU. flags '--Intel-reserved addres The addres The The the
program DI SI ofBP to
ALThis flag): divisible decide
stored at
of an that AF, flag hexadecimal minimum segment A
carry IF
DF
OF of register register regitheexecut
of ster ion of data
SFthe ZF after flag of 1s), If8-bit CFThe DE, isregister ZE, the is the the
TF holdsindicates
PF the Fig . stored. to the thoep INTEL
is result th e functions
holds
or
I
obtainedF , SF, 8086 by refers is source is
is a is flag): lower 13. 2 size destination be
is of
address
BCD used bits is 16-bit and and can 16. called 8086
usedexecuted. D9 is form can In tos called readcalled the of
isthat AFset the Thi s MICROPROCESSOR
the
to shown is the data PUSH
to arithmetic zero addition by in subtraction
holds
eight carry of TF after OFbe Flag bits ZF
SF
TF D8 beportion a destination source from base at
t th e 0. ar e classified
are means in stack
the Otherwise, the register
(normally XXXXOH. even 8086, data which
debug If and the
e D7 in the pointer. or
S after called thcalled in
or segment.
=
result orDAA bit the bits different
if position of execution of Fig . that 1 th e of data indexwritten POP the
subtraction, D6 byte. the thindex
e ARCHITECTURE,
a the 0, Z=0, of or carry operation. the the thmaximum
e
ancontrol status into set 13. 2 . reasonThe extra segment,register.instruction, It data
program sign the the
of an the it
result 8-bit flags status 8086 to0) D5 starting memory register. into is
3 is segment also is SP
arithmetic DAS (the after set or flags, flags,
of AF D4 segment, the to is
bitresult result are an flags used FEATURES,
is respectively. addition
LSB tohave 16-bit addresS size while It
stack used be
using instruction I. an as
arithmetic as D3 thfiosr where It respectively.
is
0after is or always of is topushed along
an d not is odd
follows: theyas they and PF- D2DI while executing
used used
the lo gic or addition athe segment. hold AND
the an zero. control is of segment
control indicate with SIGNALS
treated the
parity explained begins
a data, executing to to the or
single-step ariresulthmet or segment hold hold popped, the
t ic operation adjustto borow as or logic flags. CF code,
(i.e., DO at can string the offset
is bit th e th e the the SS 421
a
 ONTRDAFRS
422 MWAAS
te thecode segment
ie.,TE l), RO86 gets ddressof
technique, If itisset executionof each
Mep interruptj
afterthe
trapping or
iritermuptheed
instruction in
sddinefour binary(%
byhexadecimal digit 0)
detaigging feature
vH) DF
direction
TF Oj,

Sl
the
iscleared(ie,Ag) DE selects either the
register,
the Dl and/or are automatically
increment
during the execution of
or
string
ydeectgeratm content

ddressis
ete

akressofthe
Therefore, the
ofCS.
2000H. Similarly.
dataasegment,
0,the registers incremented,
decremented,This flag can be set and
if D
he hase and extra segment
wrert

automatically
and C1D
instrsctions,
Aag): IF
respectively.
controls the operation of the
leared usirnegistthse Stt%e e segment,
K000H, and 8000OH.
epectivelyFigure
13.3shows the
fvHi) IF
(interrupt
the8086. HIF0, INTR inter up pjn g
the INTR pin is disabled and if 1F 1, the
set and cleared Using the STI
bation
these
of
segments in the
serent

enabied This Magcan be and CL segments

two different
instru
emory
respectively. sizeof
Signed ncgative numbers are the
than64KB,it
is possible that
(ix) OF (overflow Rag): microprocessor, When
signedreprenumber
senteds in may overlap (i.e.,
less
segments
complement formin the the T s
An overflow are segment may begin within
two
or subtracted, an overtlow may OCCur.
has exceeded thecapacity of the the
machine. For indicates raleuealAh
example, that
if thes he
nother allocated to a segment).
KB
64K
a particular
data 7EH ( +126) is added with 8-bit
signed data 02H 8-bit sigmed the
For
example, let
the 8086 require a
result is 8OH(-128 in the 2's complement form). This result sgplicationin and
overflow flag is set segmentofssize 1 KB la data
givenindisgned
cae,
an overflow condition and the during
addition operation. In an 8-bit register, the minimum and the code ofsize 2 KB. If the code
segment Fig. 13.3 Locaticn of varicus
of the signcd number that can be stored is -1283(= 80H) aand
respectively. In a 16-bit register, the minimum and
maxi+127mum(=TFH,
value segment is stored
address
in the memory
2000OH, it will end in memory
segments
maximum
the signed number that can be stored is -32,768 (= 8000H) and value of
from the
the memory
address 203FFH. The data segment can be stored from the
address
at20400H
(= 7FFFH),respectively. For operations on unsigned data, OF is +32,16] (which ís the next immediate 16-byte boundary in the memory). The CS
13.2.2 Bus Interface Unit
ignored. and DS registers are Joaded with the values 2000H and 2040H, respectively, for
running this application in the 8086.
There are four segment registers CS, DS, SS, and ES in the 8086. The funcion
of these registers is to indicate the starting or base address of thecode segment, 133 ACCESSING MEMORY LOCATIONS
data segmernt, stack segment, and extra segment, respectively, in the memory, Te
code segment contains the instructíons of a program and the data segment contains Each address in the physical memory (ROM/EPROM) is called aphysical address.
data for the program. The stack segment holds the stack of the program, which To access an operand (either data or instruction) from aparticular segment of the
is needed while executing the CALL and RET ínstructions and also to hand; memory, the 8086 has to first calculate the physical address of that operand. To
interrupts. The extra segment is an additional data segment that is used by some accomplish this task, the 8086 adds the base address of the corresponding segment
string instrucions. with an offset address, which may be the content of a register, an 8-bit or 16
The base address of any segment can be obtained by adding four binary (s bit displacement given in the instruction, or a combination of both, depending
1o the farthest right portíon of the content of the corresponding segment regista, upon the addressing mode used by the instruction. The designers of the 8086 have
which is the same as adding the hexadecimal digit 0. It is also equivalent to shitng asigned certain register(s) as default offset register(s) for the segment registers,
the content of the segmnent register right by four bits. Hence, a segment in he bUm as shown in Table
registers in the 8O86
always starts at amenory address that is divisible by the decimal number lo (0 13.1. However, this Table 13.1 Segment registers and default offset
known as l6-byte boundary). This is illustrated with an example as follows: default assignment Segment registers Defaut offset registers
can be changed by
CS IP
Example 13.1: using the segment
Let us assume that the Override prefix in the DS BX, SI, DI, 8- or 16-bit displacement
segment registers have following values Storedin them:
CS
DS ES instruction, which is SS SP and BP

2000H 4000H
SS
explained in Chapter
14 (Section 14.2). ES DI for string instructions
6000H 8000H
 MICROCONTRCLLERS INTEL A086
MICROPROCESSORSAND MICROPROCESSOR A
424
byteof AX) is pushed into
the offset
ARCHTECTURE, FEATURES, ANO SIGNALS 425
Example13,2: memory in
The fetching of an
instnuction from the the 8086 is
(upper
segment,as
againdecremented by
stack
shown in Fig. 13.5 (a),.
I (ie.. SP
address specified by SP in the
example. thatthe CS
registerhas the value 3000H and SPis (lower
byte of AX) is pushedlinto 0103H) and the
Let us assume fetch aninstructionfromthe
shown in Fig. 13.5the(b).offset addresScontent theby ALSP
ri register of
To memory, the
the value 2000H.from which the next instruction is to be thestack
segment, as
specified
CSx10H
address
memory 30000HBase address ofthe code

+1P= 2000H
-0ffsetaddress
fe tched, fol owg
segment s
in

Mermory Address
32000H-- Memory address from wherethe next
Example13.3:
Let us sec the
fetching of data from the memory using the DS
instnuctioM 0s
taken
AH

JCH
AL

2BH SP a1044
stack segment(SS X
10H)

withanexample.
Consider the execution of the instruction MOVand BX
instructionBX indicates AX,that (BrX)eis,tery
3CH
around BX in thËs 301944SSX10H+SP)
The square bracket the memory; the
Specified by the BX register is in register he
fromholds the ala
The
segment. data obtained
address of the datain the data
moved to the AX register. Let us
assume that DS and BX the oi sa is
and 3000H, respectively. To
thhe
calculate the memory address from
have
memo
values I00ry a

has to be taken, the CPUdoes the following operation: where the data Memory
Address
DS x 10H =10000H’ Base address of the data segment
+BX= 3000H Offset address
AL 3OCOOH SSX10H)
13000H Memoryaddress from where the AH
datais taken
This is also explained in Fig. 13.4. 3CH 2BH
SP =0103H

Memory
Address 2BH
30103H SSX 10H+SP)
3CH
30104H
AH AL 10000H
4BH 3AH 3000H (offiset)
(b)
Eio. 13.5 PUSH AX: (a) pushing the first byte of AX onto the stack segment (b) pushing the
3AH 13000H
4BH
second byte of AX onto the stack segment
130014
The instruction queue is six bytes long and stores the pre-fetched instructions
from the code segment. From there, the instruction is taken to the instruction
1byte decoder, where it is decoded. The decoder passes the decoded information to the
timing and control circuit, which in turn generates the various control signals to
execute the instruction. Whenever this decoded instruction requires branching
Fig. 13.4 Execution of the instruction MOV AX, [BX] (Which arises when conditional or unconditional jump instructions are decoded),
Example 13.4: he instruction queue is flushed and the instruction bytes from the branch address
Let us see the pushing of data into the stack segment using the PUSH re tetched into the queue. The BIU fetches the instruction bytes from the memory
with an example. instruciol, Wnenever the EU is not using the address/data bus and puts them in the instruction
queue. Fetching and execution of instructions can take place simultaneously. Thus
Assume that the SS and SP registers have the values 3000H and 0105H, theinstruction queue reduces the execution time of a program.
respectively. Consider the execution of the instruction PUSH AX bythe 8086.The allows
steps carried out by the The
segment and offset mechanis1m for accessing the memory in the 8086
8086 to execute the PUSH AX instruction areasfollows structures, Arelocatable
i) SP is
decremented by 1(i.e., SP=0104H) and thecontent of the AH register programmer to write relocatable programs or data
memory map
program or data structure is one that can be placed anywhere in the
 MICROCONTROLLERS
MCROPROCESSORSAND INTEL 8n96
426 MICROPROCES9OR
and executed
without any
modification
This
is not addresssignals A19-A16
ARCHTECTURE,
and the status bits FEATURES SIONALS 427
MNO
of the 8086
microprocessor. In a relocatable program, the jump
possible
instructions the pins.carry the address and
when ALE-0, theyS6-S3. When ALE =.
(positive or
to
negative) with respect the progTam counter, use the these
oneexternal octal latch
(74373)
values calculated. In addition, in a relocatable
jump address is offset address inthe data segment or the Anta Using whch t Using
canbe de-multiplexed into the
along with thecarryALEthe status lines.
extstertaure, the dta
address bus
A19-Aby16)theandsi8086
gnalthe, these
pins
(S6-S3). S3 and S4
referredto usingthe indicate theinsegment (accessed
13.4 PIN DETAILS
OF8086
following two:
segmet. bus
the
currentt bus cycle. This is shown
Table 13.2
Table 13.2.

Function of status bits SA and S3

status
duing
in any one ot the
The 8086 can operate minimum mode, all the
maximum mode. Inthe
VO are generated by
the 8086. Inthe maximum
the
mode,
addition of some
modesminimthume memmo¡rdye aandnd
control signals for
control
n
0
Segment accessed
Extra segment
such as the 8288tothe
This requires an
beexternaly generated.8086. Some pins in the 8086 have external
the same Signals muSA
bus 1
Stack segment
functions. Figure 13.6 shows
the funcionconitnrbotoofleh, Code segment or no
different 0
modes; other pins have
pin segment
8O86. details the
1 1
Data segment
Max. mode (Min. mode) S5indicates the condition of the IF bit;
40 statusbit S6 always
GND
AD15
The remains at logic
UUUUUWUTUUTAD4 NMI: The non-maskable
A16/53 interrupt (NMI) input is a hardware
AD (i)
cannotbe disabled by software. It is a positive interrupt. It
AD12
AD11
DA17/S4
A18/S5 when itoccurs, the type 2interrupt occurs in theedge-triggered
8086. interupt and
INTR: The interrTupt request (INTR) is a
AD10 A19/S6
BHE/S7 (iv) level-triggered hardware interrupt,
which depends on the status of IF. When IF =1, if
MNIMX
INTRis held high
logic 1), the 8086 gets interrupted. When IF =0, INTR is disabled. (ie.,
RD (v) CLK: The clock signal must have a duty cycle of 33% to provide proper
8086
31 RO/GTO (HOLD) internal timing for the 8086. Its maximum frequency can be 5, 8, and
ROJGT1 (HLDA)
AD 12 (WR) 10MHZ for different versions of the 8086 the 8086, 8086-2, and 8086-.
AD 13 (MIO) respectively.
AD 14 S (DTR) w) Vo This power supply pin provides a+5 Vsignal to the 8086. The variation
SO (DEN) allowed in the power supply input is +10%.
AD QSO (ALE) (vi) BHE/S7: The bus high enable (BHE) pin is used in the 8086 to enable the
NMI C17 OS1 (INTA) most significant data bus (D15-D8) during a read/write operation. The
INTR 18 23 TEST state of the status line S7 is always logic 1.
CIK 19 22 READY (vi) MN/MX: The MNMX pin is used to select either the minimum mode or
GND 20 21 RESET
the maximum mode operation for the 8086. This is achieved by connecting
this pin to either +5 V directly (for minimum mode) or to the ground (for
Fig. 13.6 Pin details of the 8086 maximum mode).
13.4.1 Function of Pins Common to Minimum and Maximum Modes (IX) RD: VWhenever the Read signal (RD) is at logic 0, the 8086 reads the data
The pins that have a common function in both the modes are as follows: Irom the memory or VO device through the data bus.,
) ADI5-ADO: These pins act as the multiplexed address and data bus or d TEST: The TEST pin is an input that is tested by the WAIT instruction. lt
functions as a NOP (n0
microprocessor. Whenever the ALE (address latch enable) pin is hignthese (n he TEST pin is at logic 0. the WAIT instruction
logic 1, the WAIT instruction
1), these pins carry the address, and when the ALE pin is low (i.e., 0),along Cperaton) instruction, If the TEST pin is at pin is often connected to
74373s waits for the TEST pin to become logic 0. This
pins carry data. Using two external octal latches such as two floating-point
with the ALE signal, these pins can be de-multiplexed intotheaddress
bus the BUSY pin of the 8087 (numeric coprocessor)to perform
(A15-A0) and data bus (D15-D0). operations. into the timing cycle of
the
states
(i) multiplexedtoprovide (xi) READY: This input is used toinsert wait
A19/S6-A16/S3: These pins (address/status bus) are
 INTEL 8086
MICROPROCESSOR
428
MICROCONTROLLERS
MICROPROCESSORSANO
Table 13.3
ARCHITECTURE, FEATURES, AND SIGNALS
Function of S2, S1, and 429
t, it has no
READY pinisatlogic effect on the. SÑ pins
8086. Ifthe Ifitisatlogic 0,the R086 enters the wait
microprocessor. interfacetheslowly
is used to operating operaton with S0
Function
penpherals
0
idle.This pin
8086. causes the 8086 toreset, if it is held t
(0
Int/Oerrupt
read
acknowiedge
This input periods.
Whenever the 808% is
(xii) RESET: of fourclocking
0
minimum 1 UO write
are
initializedto
initialized to
FFFFH and0000H, respectively, and all
0000H. This
memoryaddress
causesthe 808% to
FFFFOH. begin olhre
er
executing asct,S and t
regsters 0
1
Halt
Opcode fetch

up ly nfsotrructin
from the
GND connection
isthe return for the power Memory read
(xii) GND: The
GNDpins and both
must be
connected sground 1
Memory write
SO86 has two
operation.
Mode
used in Minimum followe.
to
(d.Thepropga 1
1
Passive (inactíve)
( )LOCK:The Lock output is usedIto lock peripherals off the system. This pin
134.2FunctionofPins minimum mode are as isactivated by usingthe. LOCK prefix on any instruction.
The pins used in the indicates whetherthe 8086 is (i)ROGTOand RQ/GTI: The request/grant pins request DMA during the
() MÍO: This pin performing operation of the 8086. These
l) or VO read/write operation
(MIOmemory Tead
maximum mode
write operation(MMO = areusedIto request and grant a DMA operation. lines are bidirectional
data =0).
indicates that the 8086 is and
(i) WR: The Write signal logic 0, the sending
data bus contains toa iv) QSIand OS0: The queue status bits show the status of the internal
or /O device. When WR is at
the memory or I/0. yalid medatmaoryior instruction queue in the 8086. These pins are
provided for
(i) DTR: The Data Transmit/Receive signal
indicates that
the 8086 numeric coprocessor (8087). Table 13.4 the shows function ofaccess by the
the QSl and
(DTR= 1) or receiving (DT/R = 0) data.
transmitting(D
control the data flow irection in external data bus buffers,This signal datisa usedbus tois OSObits.
Table 13.4 Function of QS1 and QS0 pins
(iv) DEN: The Data Bus Enable signal activates external data bus
data is transferred through the data bus of the 8086, this
When DEN is high, no data flows in the data bus.
signalbuffers.loWhengic,.
is at QSO Function

0 Oueue is idle (or no operation).

(v) ALE: When the Address Latch Enable (ALE) signal is high, it 0
that the 8086 multiplexed address/data bus (AD15-ADO) :and indicates 1 First byte of opcode is read from the queae.
address/status bus (A19/S6-A16/S3) contain an address, which multipcanleedbe 1 Queue is empty.
either a memory address or an IOport address. 1 1 Subsequent byte of opcode is read from the queue.
(vi) INTA: The Interrupt Acknowledge signal is a response to the INTR inu
pin. The INTA signal is used to place the interrupt type or vector nunbetin
the data bus, in response to the INTR interrupt. POINTS TO REMEMBER
(vii) HOLD: The Hold input requests a direct memory access (DMA) and is
The internal architecture of the 8086 mainly contains two units the bus interface unit
generated by the DMA controller. If the Hold signal is at logic 1, the 086 (BIU) and the execution unit (EU).
completes the execution of the current instruction and places its adirs The BIU fetches instructions and data from the memory to the
data, and control buses in the high impedance state. If the Hold signal is al processor, using the
content of a segment register and an offset.
logic 0, the 8086 executes the instructions normally. "There exists a six-byte instruction queue in the 8086, which is used to store the recently
(vii) HLDA: The Hold Acknowledge signal indicates that the 8086 has entered fetched instructions in the CPU. This is used to speed up the execution of a program.
the hold state and is
connected to the HLDA input of the DMA Controlet. nere are four memory segments code, data, stack, and extra segments in the 8086 and
13.4.3 Function of Pins used in Maximum Mode r Dase address is indicated by adding four binary Os to the right of the coresponding
The pins used in the maximum mode are as segment register's content. The maximum size of a memory segment is 64 KB.
" For
() S2, SI, and S0: The status bits follows: fetching either an instruction byte or a data, the 8086 adds the base address of the
ethe function of the current bus cycle particular segment with an offset address present in aregister,,available as an &- or l6-
These signals are normally indicate the 8288 (bus controller). Table bit
13.3 shows the decoded by
function of these three status bits in the maximum mode. The displacement in the
designers of the instruction,
or obtained by a combination of both.
8086 have fixed the default offset register(s) for every segment