10/4/2024

Lecture 3: 80x86 Microprocessor

Architecture
Seyed-Hosein Attarzadeh-Niaki

Some slides from Hongzi Zhu

Microprocessors and Interfacing 1

Review:
Microprocessors and Microcontrollers

Microprocessors and Interfacing 2

1
 10/4/2024

Outline
• 8086 internal structure
• 8086/88 pins, signals, and buses

Microprocessors and Interfacing 3

Evolution of 80X86 Family

• 8086, born in 1978
– First 16-bit microprocessor
– 20-bit address data bus, i.e. 220 = 1MB memory
– First pipelined microprocessor
• 8088
– Data bus: 16-bit internal, 8-bit external
– Fit in the 8-bit world, e.g., motherboard, peripherals
– Adopted in the IBM PC + MS-DOS open system
• 80286, 80386, 80486
– Real/protected modes
– Virtual memory
Microprocessors and Interfacing 4

2
 10/4/2024

Internal Structure of 8086

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data
already been fetched by the BIU. from memory and I/O ports, writes
BIU and EU functions separately. data to memory and I/O ports.
Microprocessors and Interfacing 5

Bus Interface Unit

• Take in charge of data transfer between CPU
and memory and I/O devices as well
– Instruction fetch, instruction queuing,
operand fetch and storage, address relocation and Bus control
• Consists of
– Four 16-bit segment registers: CS, DS, ES, SS
– One 16-bit instruction pointer: IP
– One 20-bit address adder: e.g., CS left-shifted by 4 bits + IP (CS*16+IP)
– A 6-byte instruction queue
• While the EU is executing an instruction, the BIU will fetch the
next one or several instructions from the memory and put in
the queue

Microprocessors and Interfacing 6

3
 10/4/2024

Bus Interface Unit

Dedicated Adder to generate
20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Instruction queue

• A group of First-In-First-Out
(FIFO) in which up to 6 bytes of
instruction code are pre-fetched
from the memory ahead of time.
• This is done in order to speed up
the execution by overlapping
instruction fetch with execution.
• This mechanism is known as
pipelining.

Microprocessors and Interfacing 7

EU decodes and executes

Execution Unit
instructions.

A decoder in the EU control

system translates
instructions.
16-bit ALU for
performing arithmetic
and logic operation

Four general purpose

registers (AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as:
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can
Microprocessors andbe used
Interfacing as CH and CL 8
DX can be used as DH and DL

4
 10/4/2024

Registers
• On-chip storage: super fast & expensive
• Store information temporarily

• Six groups

Microprocessors and Interfacing 9

Execution Unit Registers I

Accumulator Register (AX)
• The I/O instructions use the AX or AL for inputting/outputting 16 or 8 bit data to or
from an I/O port.
• Multiplication and Division instructions also use the AX or AL.

Base Register (BX)

• This is the only general purpose register whose contents can be used for addressing
the 8086 memory.
• All memory references utilizing this register content for addressing use DS as the
default segment register.

Counter Register (CX)

• Instructions such as SHIFT, ROTATE and LOOP use the contents of CX as a counter.

Data Register (DX)

• Used to hold the high 16-bit result (data) in 16x16 multiplication or the high 16-bit
dividend (data) before a 32/16 division and the 16-bit reminder after division.
Microprocessors and Interfacing 10

5
 10/4/2024

Execution Unit Registers II

Stack Pointer (SP) and Base Pointer (BP)
• SP and BP are used to access data in the stack segment.
• SP is used as an offset from the current SS during execution of instructions
that involve the stack segment in the external memory.
• SP contents are automatically updated (incremented/ decremented) due to
execution of a POP or PUSH instruction.
• BP contains an offset address in the current SS, which is used by instructions
utilizing the based addressing mode.

Source Index (SI) and Destination Index (DI)

• Used in indexed addressing.
• Instructions that process data strings use the SI and DI registers together with
DS and ES respectively in order to distinguish between the source and
destination addresses.

Microprocessors and Interfacing 11

Flag Register
Auxiliary Carry Flag Carry Flag

This is set, if there is a carry from the This flag is set, when there is
lowest nibble, i.e, bit three during a carry out of MSB in case of
addition, or borrow for the lowest addition or a borrow in case
nibble, i.e, bit three, during subtraction. of subtraction. (8-/16-bit op.)
Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s; for odd number of
zero 1’s, set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Overflow Flag Tarp Flag

This flag is set, if an overflow occurs, i.e, if the result of a signed If this flag is set, the processor
operation is large enough to accommodate in a destination enters the single step execution
register. The result is of more than 7-bits in size in case of 8-bit mode by generating internal
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set.
each instruction

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.12
Microprocessors
towards the lowest address, i.e., and Interfacing
auto decrementing mode. 12

6
 10/4/2024

More about Signed Numbers

CF and OF
• The most significant bit (MSB) as sign bit, the rest of
bits as magnitude
– For negative numbers, D7 is 1, but the magnitude is
represented in 2’s complement
• CF is used to detect errors in unsigned arithmetic
operations
• OF is used to detect errors in signed arithmetic
operations
– E.g., for 8-bit ops, OF is set when there is a carry from d6
to d7 or from d7 out, but not both

Microprocessors and Interfacing 13

Examples of Conditional Flags

How can CPU know

whether an operation is
unsigned or signed?

OF = 0 since there is no carry from d6 to d7 and no carry beyond d7

Microprocessors and Interfacing 14

7
 10/4/2024

Pipelining in 8086
• BIU fetches and stores instructions once the queue has more than two
empty bytes
• EU consumes instructions pre-fetched and stored in the queue at the
same time
• Increases the efficiency of CPU
• When it works?
– Sequential instruction execution
– Branch penalty: when jump instruction executed, all pre-fetched instructions
are discarded

Microprocessors and Interfacing 15

8086/8088 Pins
(Compare them and tell the difference)
GND 1 40 VCC(+5V) GND 1 40 VCC(+5V)
AD14 2 39 AD15 A14 2 39 A15
AD13 3 38 A16/S3 A13 3 38 A16/S3
AD12 4 37 A17/S4 A12 4 37 A17/S4
AD11 5 36 A18/S5 A11 5 36 A18/S5
AD10 6 35 A19/S6 A10 6 35 A19/S6
AD9 7 34 BHE/S7 A9 7 34 SS0
AD8 8 8086 33 MN/MX A8 8 8088 33 MN/MX
AD7 9 32 RD AD7 9 32 RD
CPU 31 HOLD(RQ/GT0)
CPU 31 HOLD(RQ/GT0)
AD6 10 AD6 10
AD5 11 30 HLDA(RQ/GT1) AD5 11 30 HLDA(RQ/GT1)
AD4 12 29 WR(LOCK) AD4 12 29 WR(LOCK)
AD3 13 28 M/IO(S2) AD3 13 28 M/IO(S2)
AD2 14 27 DT/R(S1) AD2 14 27 DT/R(S1)
AD1 15 26 DEN(S0) AD1 15 26 DEN(S0)
AD0 16 25 ALE(QS0) AD0 16 25 ALE(QS0)
NMI 17 24 INTA(QS1) NMI 17 24 INTA(QS1)
INTR 18 23 TEST INTR 18 23 TEST
CLK 19 22 READY CLK 19 22 READY
GND 20 21 RESET GND 20 21 RESET
Microprocessors and Interfacing 16

8
 10/4/2024

Signals Common to Min/Max Modes

AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals

Microprocessors and Interfacing 17

17

Signals Common to Min/Max Modes

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when low.
Microprocessors and Interfacing 18
18

9
 10/4/2024

Signals Common to Min/Max Modes

READY

This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.
Microprocessors and Interfacing
The signal is active high. 19
19

Signals Common to Min/Max Modes

RESET (Input)

Causes the processor to immediately

terminate its present activity.

The signal must be active HIGH for at

least four clock cycles.

CLK

The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled

during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.

This signal is active high and internally

Microprocessors and Interfacing
synchronized. 20
20

10
 10/4/2024

Min/Max Pins
The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor is not associated with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

Microprocessors and Interfacing 21

21

Minimum Mode Signals I

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches

Microprocessors and Interfacing 22

22

11
 10/4/2024

Minimum Mode Signals II

HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.

Microprocessors and Interfacing 23

23

Control Signals

• MN/~MX: Minimum mode (high level), Maximum mode (low level)

• ~RD: output, CPU is reading from memory or IO

• ~WR: output, CPU is writing to memory or IO
• M/~IO: output, CPU is accessing memory (high level) or IO (low level)
• READY: input, memory/IO is ready for data transfer

• ~DEN: output, used to enable the data transceivers

• DT/~R: output, used to inform the data transceivers the direction of data transfer,
i.e., sending data (high level) or receiving data (low level)

• ~BHE: output, ~BHE=0, AD8-AD15 are used, ~BHE=1, AD8-AD15 are not in use
• ALE: output, used as the latch enable signal of the address latch

Microprocessors and Interfacing 24

12
 10/4/2024

Control Signals

• HOLD: input signal, hold the bus request

• HLDA: output signal, hold request ack

• INTR: input, interrupt request from 8259 interrupt controller, maskable by

clearing the IF in the flag register
• INTA: output, interrupt ack
• NMI: input, non-maskable interrupt, CPU is interrupted after finishing the
current instruction; cannot be masked by software

• RESET: input signal, reset the CPU

– IP, DS, SS, ES and the instruction queue are cleared
– CS = FFFFH
– What is the address of the first instruction that the CPU will execute after
reset?
Microprocessors and Interfacing 25

Minimum Mode Configuration

8086/88’s two work modes

◼ Minimum mode：MN / MX =1
◼ Single CPU;

◼ Control signals from the CPU

◼ Maximum mode：MN / MX =0
◼ Multiple CPUs (8086+8087)

◼ 8288 control chip supports

Microprocessors and Interfacing 26

13
 10/4/2024

Address/Data Demultiplexing &

Address latching
ALE STB Address
Latch Bus
BHE
A19~A16 8282或
74LS373
AD15~AD0
BHE

8086 Data Data

transceivers Bus
CPU 8286或
DT/R T 74LS245
Clock READY
DEN OE
8284 RESET
RES CLK WR
RD
M/IO
INTR
INTA
NMI Control Bus
+5V MN/MX
HOLD
HLDA
TEST

READY

RESET Microprocessors and Interfacing 27

Data Bus Transceiver

ALE STB Address

Latch Bus
BHE
A19~A16 8282或
74LS373
AD15~AD0
BHE

8086 Data Data

transceivers Bus
CPU 8286或
DT/R T 74LS245
Clock READY
DEN OE
8284 RESET
RES CLK WR
RD
M/IO
INTR
INTA
NMI Control Bus
+5V MN/MX
HOLD
HLDA
TEST

READY

RESET
Microprocessors and Interfacing 28

14
 10/4/2024

Memory/IO Control Signals

Microprocessors and Interfacing 29

8086/88 Bus Cycle (for data transfers)

T1 T2 T3 TW T4
CLK
At least 4 clock cycles
M/IO Low level for IO, high for memory
A19/S6~A16/S3
Addr BHE State Output
BHE/S7 Common
signals
ALE

DEN

AD15~AD0 Addr Output Data Input

Read
DT/R Cycle

RD

AD15~AD0 Addr Output Data Output

Write
DT/R Cycle

WR

READY

Microprocessors and Interfacing 30

15
 10/4/2024

Next Lecture
• 80x86 memory organization
– Memory segments
• Addressing modes

Microprocessors and Interfacing 31

16