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Fgpa Course

The document provides an introduction to FPGA design for embedded systems, detailing tools, reference books, and target FPGA specifications. It discusses the architecture of Complex Programmable Logic Devices (CPLDs) and FPGAs, highlighting their differences, advantages, and the FPGA development process. FPGAs are emphasized as flexible, scalable solutions for larger designs, with various configuration memory technologies impacting cost and performance.

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22 views2 pages

Fgpa Course

The document provides an introduction to FPGA design for embedded systems, detailing tools, reference books, and target FPGA specifications. It discusses the architecture of Complex Programmable Logic Devices (CPLDs) and FPGAs, highlighting their differences, advantages, and the FPGA development process. FPGAs are emphasized as flexible, scalable solutions for larger designs, with various configuration memory technologies impacting cost and performance.

Uploaded by

adilrchanna
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as TXT, PDF, TXT or read online on Scribd
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INTRO TO FPGA DESIGN FOR EMBEDDED SYSTEMS:

----------------------------------WEEK 1----------------------------
Tools to use: Quartus Prime, INTEL Qsys Pro System Integration Tool,
Timequest Timing Analyzer, INTEL-ModelSim, DSP Builder for INTEL FPGA
and Power Analyzer

REFERENCE BOOKS:
1. Rapid Prototyping of Digital Systems (SOPC Ed.) by J. O. Hamblen
2. Design Recipes for FPGAs using Verilog & VHDL by Peter Wilson

Target FPGA: Terasic DE10-lite

Complex PLD ARCHITECTURE:-


AND and OR plane, Sum of Products Logic Functions
Either Programmable AND, Fixed OR <- Programmable Array Logic (PALs)
or Fixed AND, Programmable OR

Registered array of PALs leads to CPLDs


Programmed interconnects of CPLDs is stored in on-chip EE prompt

CPLDs are hierarichal devices consisting of:


- LABs (Logic Array Blocks)
- PIA (Programmable Interconnect Array) routing b/w LABs

SUMMARY:-
CPLDs introduced reprogrammability to programmable logic devices,
CPLDs also reinforced hierarchical design methods. The architecture
of CPLDs allows for easy design of wide input combinational logic
functions like address decoders & state machines with deterministic
timing. However, the CPLD architecture did not scale effectively for
designs that required many flip flips, which is the advantage of
FPGA, along with easy scalability.

FPGA Architecture and LUTs:-


A Logic Element (LE) usually consists of,
1. 4-input LUT (two 3 input LUTs are used with a mux for normal mode)
2. Full Adder (used for arithmetic mode)
The middle MUX selects the mode
3. D Flip Flop (and output MUX on the right side)

Types of FPGA Architecture:


1. Antifuse FPGAs are known for reliability but they are one time
programmable and expensive.
2. FLASH FPGAs are also very reliable and
there are also re-programmable, but higher price than SRAM FPGAs.
3. SRAM FPGAs are programmable with highest density and lowest cost
for equivalent logic.

FPGA Development Process Design Flow:


1. Design Entry Schematic or HDL
2. Functional Simulation (back to 1 if failed)
3. Synthesis or Mapping
4. Place & Route or Fitting
5. Simulation (back to 1 if failed)
6. Programming
7. Test & Integration (back to 1 if failed)
8. Release
FPGA Architecture SUMMARY:
FPGAs are highly flexible general purpose digital logic devices, due
to the use of memory elements as LUTS for the base logic cell.

FPGAs scale better than CPLDs, creating low cost solutions for larger
designs and designs that require many flip-flops. Because FPGA
architecture is finer grained, routing has more impact on performance

FPGA configuration memory can be implemented using one of several


different technologies, including SRAM, Flash and Antifuse, this
choice impacts cost and performance

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