Scribd
Upload
11 views18 pages

Ee618 Assignment1

The document outlines an assignment for EE618 CMOS Analog VLSI Design, focusing on DC analysis of PMOS devices. It includes detailed instructions for plotting ID vs VSD and ID vs VSG for various voltage values, as well as extracting key parameters like gm and rout. Observations from the simulations highlight the relationship between channel length modulation and the characteristics of the MOSFETs.

Uploaded by

abhijeetdarekar2000
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
11 views18 pages

Ee618 Assignment1

The document outlines an assignment for EE618 CMOS Analog VLSI Design, focusing on DC analysis of PMOS devices. It includes detailed instructions for plotting ID vs VSD and ID vs VSG for various voltage values, as well as extracting key parameters like gm and rout. Observations from the simulations highlight the relationship between channel length modulation and the characteristics of the MOSFETs.

Uploaded by

abhijeetdarekar2000
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 18

EE618 CMOS Analog VLSI Design Assignment 1

24M1209 Abhijeet Darekar

Q1 (a). Run DC analysis for a PMOS device and plot the following large signal characteristics: [1 point]

a)
Part a)
a) ID v/s VSD, VDD = 1.8V for four VSG values: 0.4V, 0.8V, 1V & 1.2V

Code
.include "models-180nm.cir"
vsd 2 0 dc 1.8v

vsg 2 1 dc 1.2v

MP1 0 1 2 2 cmosp L=0.18u W=2u

.dc vsd 0 1.8 0.1 vsg 0.4 1.2 0.2

.controlrun

plot -i(vsd)

.endc

.end

Results

Observations
We know for same value of VSD, Current increases with increase in the voltage
VSG and hence the curve will shift upwards in ID vs VSD graph, which we can
clearly observe from the above plot.

Part b)
b) ID v/s VSG, VDD = 1.8V for four VSD values: 0.4V, 0.8V, 1V & 1.2V
Code
.include "models-180nm.cir"

vsd 2 0 dc 1.8v

vsg 2 1 dc 0

MP1 0 1 2 2 cmosp L=0.18u W=2u

.dc vsg 0 1.8 0.05 vsd 0.4 1.2 0.2

.control

run

plot -i(vsd)

.endc.end

Results

Observations:
We have plotted ID vs VSG for different voltage values of VSD. We know for same
voltage VSG current increase with increase in voltage VSD, so the curve should
move upwards with increase in VSD. This can be verified from the results
obtained.

Q1 (b). Using the simulation results obtained above, extract the following parameters for VSG = 1 V and
VSD = 1.2 V. [2 points]

a) gm

b) rout

c) λ (channel length modulation parameter)

d) ID

e) VTH

f) µpCox
Code for ID and gm calculation:
.include "models-180nm.cir"

vsd 2 0 dc 1.2v

vsg 2 1 dc 1.2v

MP1 0 1 2 2 cmosp L=0.18u W=2u

.dc vsg 0 1.2 0.01

.control

run

plot -i(vsd)

plot -deriv(i(vsd))

.endc

.end

Result
Console
Console

Code for rout calculation:


.include "models-180nm.cir"

vsd 2 0 dc 1.8v

vsg 2 1 dc 1v

MP1 0 1 2 2 cmosp L=0.18u W=2u

.dc vsd 0 1.8 0.01

.control

run

plot -deriv(i(vsd))

.endc
.end

Result

Console
Hand calculations:
Q2. Run DC analysis for a PMOS device and plot ID v/s VSD, with VSG = 0.8 V and VDD = 1.8 V. Repeat for
the three given values of W and L (W/L ratio constant). State your observations. [2 points]

a) W/L = 0.5u/0.18u

b) W/L = 2u/0.72u

c) W/L = 8u/2.88u

Simulation results of all W/L should be on the same window for comparison

Code
.include "models-180nm.cir"

vsd 2 0 dc 1.8v

vsg 2 1 dc 0.8v

MP1 0 1 2 2 cmosp L=0.18u W=0.5u

.dc vsd 0 1.8 0.01

.control

run

alter @MP1[L]=0.72U

alter @MP1[W]=2U

run

alter @MP1[L]=2.88U

alter @MP1[W]=8U

run

plot abs(dc1.i(vsd)) abs(dc2.i(vsd)) abs(dc3.i(vsd))

.endc

.end

Results
Observations:
• Here Blue, Red & Green curves represents p channel MOSFETS with channel
lengths 2.88um, 0.72um and 0.18 um respectively. We know the relation
between channel length modulation parameter (Lambda) and channel
length of the MOSFETS.
• Also channel length modulation parameter represents slope of the ID vs
VSD characteristics of the MOSFETS in the saturation region of operation.
Larger the value of Lambda larger will be the slope.
• So Green curve (L=0.18um) will have highest slope, followed by Red curve
(L=0.72um) and Blue curve (L=2.88um) respectively, which we can clearly
observe from the curves plotted
Q3. Run DC analysis for a PMOS device and plot ID v/s VSD, with VSG = 0.6 V, VDD = 1.8 V and body
terminal at: (i) VDD (ii) VDD /2. [1 point]

(i)VDD
Code
.include "models-180nm.cir"

vsd 2 0 dc 1.8v
vsg 2 1 dc 0.6v
vsb 2 3 dc 0v
MP1 0 1 2 3 cmosp L=0.18u W=2u
.dc vsd 0 1.8 0.01
.control
run
plot -i(vsd)
.endc
.end

Results
(ii) VDD/2
Code
.include "models-180nm.cir"

vsd 2 0 dc 1.8v

vsg 2 1 dc 0.6v

vsb 2 3 dc 0.9v

MP1 0 1 2 3 cmosp L=0.18u W=2u

.dc vsd 0 1.8 0.05

.control

run

plot -i(vsd)

.endc
.end

Results

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy