_______________________________________________________

Name: PRAJWAL DESHMUKH

MIS: 112007017 (BATCH-A)
Branch : TY B.Tech E & TC
Course : CMOS LAB
Year : 2022-23
_______________________________________________________
 INDEX
Sr. No. Title Page

No.

1 DC and Transient analysis of NMOS and PMOS Transistors using NGSPICE. 1

2 DC and Transient analysis of CMOS Inverter using NGSPICE. 8

3 Estimation of threshold voltage and noise margin using NGSPICE 13

4 Design of five stage ring oscillator using NGSPICE. 19

5 Design of CMOS inverter schematic in Cadence Virtuoso tool 25

6 Symbol generation for CMOS inverter schematic in Cadence Virtuoso tool 28

7 Simulation of CMOS inverter in Cadence Virtuoso tool 31

8 Layout design and physical verification for CMOS inverter in Cadence 36

Virtuoso tool

9 Design and physical verification for CMOS NOR gate design 39

Experiment 1
Aim: DC and Transient analysis of NMOS and PMOS Transistors using NGSPICE.
Software: NGSPICE

Code:
A. NMOS
a. Input characteristics:
1. .include tsmc_180nm.txt
M1 2 1 0 0 CMOSN W=360n L=180n
Vgs 1 0 1.8
Vds 2 0 1.8
.control
run
dc Vgs 0 1.5 0.1
plot -i(Vds)
.endc
.end
2. .include tsmc_180nm.txt
M2 2 1 0 0 CMOSN W=360n L=180n
Vgs 1 0 1.8
Vds 2 0 1.8
.control
run
dc Vgs 0 1.5 0.1 Vds 0 1.5 0.1
plot -i(Vds)
.endc
.end
b. Output characteristics
1. .include tsmc_180nm.txt
M3 2 1 0 0 CMOSN W=360n L=180n
Vgs 1 0 1.8
Vds 2 0 1.8
.control
run
dc Vds 0 1.5 0.05
plot -i(Vds)
.endc
.end

2. .include tsmc_180nm.txt
M4 2 1 0 0 CMOSN W=360n L=180n
Vgs 1 0 1.8
Vds 2 0 1.8
.control
 Run
dc Vds 0 1.5 0.05 Vgs 0 1.5 0.05
plot -i(Vds)
.endc
.end
B. PMOS
a. Input characteristics:
1. .include tsmc_180nm.txt
M1 2 1 0 0 CMOSP W=360n L=180n
Vgs 1 0 1.8
Vds 2 0 1.8
.control
run
dc Vgs 0 1.5 0.1
plot -i(Vds)
.endc
.end
2. .include tsmc_180nm.txt
M2 2 1 0 0 CMOSP W=360n L=180n
Vgs 1 0 1.8
Vds 2 0 1.8
.control
run
dc Vgs 0 1.5 0.1 Vds 0 1.5 0.1
plot -i(Vds)
.endc
.end

c. Output characteristics
1. .include tsmc_180nm.txt
M3 2 1 0 0 CMOSP W=360n L=180n
Vgs 1 0 1.8
Vds 2 0 1.8
.control
run
dc Vds 0 1.5 0.05
 plot -i(Vds)
.endc
.end
2. .include tsmc_180nm.txt
M4 2 1 0 0 CMOSP W=360n L=180n
Vgs 1 0 1.8
Vds 2 0 1.8
.control
run
dc Vds 0 1.5 0.05 Vgs 0 1.5 0.05
plot -i(Vds)
.endc
.end

Results:
A. NMOS
a. Input characteristics:
b.
c. Output characteristics
B. PMOS
a. Input characteristics:
b. Output characteristics
Conclusion:
The DC and Transient characteristics of NMOS and PMOS transistors have
been studied using NGSpice.

Experiment 2
DC and Transient analysis of CMOS Inverter using NGSPICE.
Aim: To perform DC and Transient analysis of CMOS Inverter using
NGSPICE.

Software: NGSPICE
Code:
1. .include tsmc_180nm.txt
M1 3 1 0 0 CMOSN W=360n L=180n
M2 3 1 2 2 CMOSP W=360n L=180n
Vdd 2 0 1.8
vin 1 0 1.8
.control
run
dc vin 0 1.8 0.05
plot v(3) v(1)
.endc
.end
2. .include tsmc_180nm.txt
M1 3 1 0 0 CMOSN W=360n L=180n
M2 3 1 2 2 CMOSP W=360n L=180n
Vdd 2 0 1.8
vin 1 0 1.8
.control
run
dc vin 0 1.8 0.05 Vdd 0 1.8 0.2
plot v(3) v(1)
.endc
.end

3. .include tsmc_180nm.txt
M1 3 1 0 0 CMOSN W=360n L=180n
M2 3 1 2 2 CMOSP W=360n L=180n
Vdd 2 0 1.8
vin 1 0 1.8
Vref ref 0 -1
.control
run
dc vin 0 1.8 0.05
plot deriv(v(3)) v(3) v(ref) v(1)
.endc
 .end
4. .include tsmc_180nm.txt
M1 3 1 0 0 CMOSN W=360n L=180n
M2 3 1 2 2 CMOSP W=360n L=130n
Vdd 2 0 1.8
vin 1 0 pulse(0 1.8 0 0.2u 0.2u 1u 2u)
.control
run
tran 0.1u 10u
plot v(3) v(1)
.endc
.end
5. .include tsmc_180nm.txt
M1 3 1 0 0 CMOSN W=360n L=180n
M2 3 1 2 2 CMOSP W=360n L=130n
Vdd 2 0 1.8
vin 1 0 pulse(0 1.8 0 0.2u 0.2u 1u 2u)
c1 3 0 5pf
.control
run
tran 0.1u 10u
plot v(3) v(1)
.endc
.end

Results:

1.
2.

3.
4.

5.
Conclusion:
The DC and Transient characteristics of a CMOS inverter have been studied
using NGSpice.

Experiment 3
Estimation of threshold voltage and noise margin using NGSPICE.
Aim: To estimate threshold voltage and noise margin using NGSPICE.

Software: NGSPICE

Code:
1. Saturation current method
.include ibm_130nm.txt
M1 2 1 0 0 CMOSN W=260n L=130n
Vgs 1 0 1.8
 Vds 2 0 1.8
.control
run
dc Vgs 0 1.5 0.05
plot -i(Vds) deriv(-i(Vds))
.endc
.end
2. Square root slope method
.include ibm_130nm.txt
M1 2 1 0 0 CMOSN W=260n L=130n
Vgs 1 0 1.8
Vds 2 0 1.8
.control
run
dc Vgs 0 1.5 0.05
plot -i(Vds)/(deriv(sqrt(-i(Vds))))
.endc
.end

3. Square Root method

.include ibm_130nm.txt
M1 2 1 0 0 CMOSN W=260n L=130n
Vgs 1 0 1.8
Vds 2 0 1.8
.control
run
dc Vgs 0 1.5 0.05
plot sqrt(-i(Vds))
.endc
.end
4. Derivative method
.include ibm_130nm.txt
M1 2 1 0 0 CMOSN W=260n L=130n
Vgs 1 0 1.8
Vds 2 0 1.8
.control
run
 dc Vgs 0 1.5 0.05
plot deriv(deriv(-i(Vds)))
.endc
.end

Results:
1.

Calculations:
(Extend the flat peak of red line downwards on the green line and draw a
tangent to the green line at that point)

Dy/dx = y0/(x0-Vth)
0.00044 = 3.3*10-5 /(0.5725-Vth)
Vth = 0.4975V

2.

Calculations –
(Draw a tangent to the linear region)
Vth = y0/(slope)
Vth = 0.013/0.0278
Vth = 0.46V
3.
Calculations –
Calculate the slope of the linear region
Dy/dx = y0/(x0-Vth)
0.026 = 0.0059/(0.59 - Vth)
Vth = 0.37 V

4.

4.
Calculations –
The x coordinate of the peak value is the Vth.
Vth = 0.45 V

Experiment 4
Design of five stage ring oscillator using NGSPICE.
Aim: To design three and five stage ring oscillators using NGSPICE.

Software: NGSPICE

Code:
1. Ideal 3 stage ring oscillator
.include tsmc_180nm.txt
M1 3 1 0 0 CMOSN W=360n L=180n
M2 3 1 2 2 CMOSP W=360n L=180n
M3 4 3 0 0 CMOSN W=360n L=180n
M4 4 3 2 2 CMOSP W=360n L=180n
M5 5 4 0 0 CMOSN W=360n L=180n
M6 5 4 2 2 CMOSP W=360n L=180n
Vdd 2 0 1.8
 vin 1 0 pulse(0 1.8 0 0.2u 0.2u 1u 2u)
.control
run
tran 0.1u 10u
plot v(5) v(1)
.endc
.end
2. Practical 3 stage ring oscillator (with capacitors)
.include tsmc_180nm.txt
M1 3 1 0 0 CMOSN W=360n L=180n
M2 3 1 2 2 CMOSP W=360n L=180n
C1 3 0 10pf
M3 4 3 0 0 CMOSN W=360n L=180n
M4 4 3 2 2 CMOSP W=360n L=180n
C2 4 0 10pf
M5 1 4 0 0 CMOSN W=360n L=180n
M6 1 4 2 2 CMOSP W=360n L=180n
C3 1 0 10pf
Vdd 2 0 1.8
.control
run
tran 0.1u 10u
plot v(1)
.endc
.end
3. 5 stage ring oscillator
.include tsmc_180nm.txt
.subckt inverter 1 2 3 0
M1 3 1 0 0 CMOSN W=360n L=180n
M2 3 1 2 2 CMOSP W=360n L=180n
C1 3 0 10pf
.ends
Vdd 2 0 1.8
xinv1 5 2 6 0 inverter
xinv2 6 2 7 0 inverter
xinv3 7 2 8 0 inverter
xinv4 8 2 9 0 inverter
xinv5 9 2 5 0 inverter
.control
run
 tran 0.1u 10u
plot v(9)
.endc
.end

Results:
1.
Calculations
Dx = 10-6s
T = 1us
F = 1/T
F = 1MHz

2.
Calculations –
Calculate period and frequency of oscillation.
Dx = T
T = 0.447 us
F = 1/T
F = 2.237 MHz
F = 1/2nT(pd)

3.

Calculations –
Calculate period and frequency of oscillation.
Dx = T
T = 0.866 us
F = 1/T
F = 1.154 MHz
Conclusion:
An ideal and practical three stage ring oscillator has been studied and
implemented in NGSpice. A five-stage ring oscillator has been successfully
implemented too. The time period and frequency of oscillations has been
calculated for every case.

Experiment 5

Aim: Design of CMOS inverter schematic in Cadence Virtuoso tool.

Software: Cadence Virtuoso

Procedure:

Cadence virtuoso startup:

1. Start Red Hat Enterprise Linux on your computer.
2. Open terminal.
3. Navigate to the directory in which you would like to create your folder by
using the cd command.
4. Create a new folder using mkdir <folder_name>.
5. Enter the following commands one after another:
>>csh
>> source /home/install/cshrc
6. In the new window (Cadence Design Suite) , type virtuoso
7. The log file window for the cadence virtuoso tool will open.

Schematic:
1. Go to File-> New -> Library.
 2. In the New Library window, name your library file and choose the
option ‘Attach to an existing technology library’
3. Choose that library to be gpdk180.
4. Go to File-> New -> Cellview and create a new cellview.
5. The schematic editor window will open.
6. Press I to open the Create instance popup and choose NMOS, PMOS to
place from the gpdk180 library.
7. Press P to open Create pin popup and create pins for input, output, ground
and Vdd with appropriate signal directions.
8. Press W and make the necessary connections. The schematic for CMOS
inverter is created.
Results:
 Conclusion: The schematic diagram for CMOS inverter is created using the Cadence
Virtuoso design tool.

Experiment 6

Aim: Symbol generation for CMOS inverter schematic in Cadence Virtuoso

tool.
Software: Cadence Virtuoso

Procedure:

Cadence virtuoso startup:

1. Start Red Hat Enterprise Linux on your computer.
2. Open terminal.
3. Navigate to the directory in which you would like to create your folder by
using the cd command.
4. Create a new folder using mkdir <folder_name>.
5. Enter the following commands one after another:
>>csh
>> source /home/install/cshrc
6. In the new window (Cadence Design Suite) , type virtuoso
7. The log file window for the cadence virtuoso tool will open.
Symbol generation:
1. In the schematic window Go to Create-> Cellview -> Cellview from
Cellview.
 2. In the Symbol generation options window, Specify the positions of your
pins and click Ok.
3. The Symbol will be created.
4. Select and delete the inner rectangle in your symbol.
5. Draw the inverter symbol using line and circle tools.

Results:

Conclusion: The symbol for CMOS inverter was generated in the Cadence
virtuoso tool by using the schematic created in experiment number 5.
 Experiment 7

Aim: To simulate and observe the behaviour of a CMOS inverter in Cadence

Virtuoso design tool
Software: Cadence Virtuoso

Procedure:

Cadence virtuoso startup:

1. Start Red Hat Enterprise Linux on your computer.
2. Open terminal.
3. Navigate to the directory in which you would like to create your folder by
using the cd command.
4. Create a new folder using mkdir <folder_name>.
5. Enter the following commands one after another:
>>csh
>> source /home/install/cshrc
6. In the new window (Cadence Design Suite) , type virtuoso
7. The log file window for the cadence virtuoso tool will open.
Simulation:
A. From Schematic:
1. Create instances for Vin and Vdd from analoglib library.
 2. For Vin, choose Vpulse
Voltage1: 0 V
Voltage2: 1.8 V
Period: 20 ns
Delay: 0 s
Rise time: 1ns
Fall time: 1ns
Pulse width: 10ns
3. For Vdd, choose Vdc with a value of 1.8 V.
4. In the editor window, go to
5. Draw the inverter symbol using line and circle tools.

Diagrams:
Results:
Conclusion: The symbol for CMOS inverter was generated in the Cadence
virtuoso tool by using the schematic created in experiment number 5.

Experiment 8

Aim: To design physical layout for CMOS inverter in 180 nm technology using
Cadence Virtuoso design tool
Software: Cadence Virtuoso

Procedure:

Cadence virtuoso startup:

1. Start Red Hat Enterprise Linux on your computer.
2. Open terminal.
3. Navigate to the directory in which you would like to create your folder by
using the cd command.
4. Create a new folder using mkdir <folder_name>.
5. Enter the following commands one after another:
>>csh
>> source /home/install/cshrc
 6. In the new window (Cadence Design Suite) , type virtuoso
7. The log file window for the cadence virtuoso tool will open.
Layout design:
1. From the schematic editor go to Launch-> Layout XL.
2. In the new Layout XL startup window, choose Create New and keep the
configuration as automatic. In the New File popup window make sure the right
library and cell name is chosen.
3. The Layout XL editor window will open.
4. Go to Connectivity -> Generate -> All from source
5. In the new generate layout window,
Minimum separation: 0.12 and make sure that necessary boxes
are checked
6. Press Shift + F to switch to the offside view of the layout.
7. Select PMOS then right click -> Edit instance properties, in the window
that appears go to the parameter tab.
8. Change Bodytie type to integrated and check the Left tap. Follow the
same procedure for NMOS.
9. Press P And connect the gate and drain terminals of NMOS and PMOS.
10.Connect the drain line to the Vout pin.
11.To connect the input pin to the gate terminals, a junction needs to be
create as the input pin is metal whereas the gate terminals are made from
poly material.
12.For that right click when starting the connection from the input pin, go to
Via down to -> Poly. Place the junction and complete the connection.

Physical Verification:
1. Go to Assura -> Technology. Assura is one of the tools that can be used
for physical verification.
2. In the file selector window, keep clicking on the ‘..’ (previous directory)
till ‘install’ directory is visible.
3. Go to FOUNDRY -> analog -> 180 nm. Then choose assura_tech.lib file
in the files tab. Click on Ok.
4. Go to Assura -> Run DRC. Check results and ensure that there are not
DRC errors found.
5. Follow the same procedure for LVS verification.
Circuit diagrams:

Results:
Conclusion: Physical verification for the inverter Layout was performed using
Assura DRC and LVS check in the Cadence Virtuoso design tool.

Experiment 9

Aim: To design CMOS NOR gate in 180 nm technology using Cadence

Virtuoso design tool.
Software: Cadence Virtuoso
Procedure:
Cadence virtuoso startup:
1. Start Red Hat Enterprise Linux on your computer.
2. Open terminal.
3. Navigate to the directory in which you would like to create your folder by
using the cd command.
4. Create a new folder using mkdir <folder_name>.
5. Enter the following commands one after another:
>>csh
>> source /home/install/cshrc
6. In the new window (Cadence Design Suite), type virtuoso
7. The log file window for the cadence virtuoso tool will open.
Schematic:
1. Go to File-> New -> Library.
2. In the New Library window, name your library file and choose the
option ‘Attach to an existing technology library’
3. Choose that library to be gpdk180.
4. Go to File-> New -> Cellview and create a new cellview.
5. The schematic editor window will open.
6. Press I to open the Create instance popup and choose NMOS, PMOS to
place from the gpdk180 library.
7. Press P to open Create pin popup and create pins for input, output, ground
and Vdd with appropriate signal directions.
1. Press W and make the necessary connections. The schematic for the
CMOS NOR gate is created.
2. File -> Check & Save.
Symbol generation:
1. In the schematic window Go to Create-> Cellview -> Cellview from
Cellview.
2. In the Symbol generation options window, Specify the positions of your
pins and click Ok.
3. The Symbol will be created.
4. Select and delete the inner rectangle in your symbol.
5. Draw the NOR symbol using curve and circle tools.

Layout design:
1. From the schematic editor go to Launch-> Layout XL.
2. In the new Layout XL startup window, choose Create New and keep the
configuration as automatic. In the New File popup window make sure the right
library and cell name is chosen.
3. The Layout XL editor window will open.
4. Go to Connectivity -> Generate -> All from source
5. In the new generate layout window,
Minimum separation: 0.12 and make sure that necessary boxes
are checked
6. Press Shift + F to switch to the offside view of the layout.
 7. Select PMOS then right click -> Edit instance properties, in the window
that appears go to the parameter tab.
8. Change Bodytie type to integrated and check the Left tap. Follow the
same procedure for NMOS.
9. Press P And connect the gate and drain terminals of NMOS and PMOS.
10.Connect the drain line to the Vout pin.
11.To connect the input pin to the gate terminals, a junction needs to be
create as the input pin is metal whereas the gate terminals are made from
poly material.
12.For that right click when starting the connection from the input pin, go to
Via down to -> Poly. Place the junction and complete the connection.

Physical Verification:
1. Go to Assura -> Technology. Assura is one of the tools that can be used
for physical verification.
2. In the file selector window, keep clicking on the ‘..’ (previous directory)
till ‘install’ directory is visible.
3. Go to FOUNDRY -> analog -> 180 nm. Then choose assura_tech.lib file
in the files tab. Click on Ok.
4. Go to Assura -> Run DRC. Check results and ensure that there are not
DRC errors found.
5. Follow the same procedure for LVS verification.
Circuit Diagram:
Input:

Output:
Conclusion:
Output for nor gate has been verified by doing simulation in Virtuoso. Physical
verification for the NOR gate Layout was performed using Assura DRC and
LVS check in the Cadence Virtuoso design tool.