Department of Computer Science

Institute of Business Administration, Karachi

Lab #8: System Verilog Simulation of

Combinational Logic: 8-bit Adders/Subtractors
and Moore sequence detector

Digital Logic Design

October 10, 2024

1 Introduction
This lab has two purposes-one is to understand the 8-bit adder/subtractor logic circuit of
SAP-1(Simple as Possible) microcomputer and the other is to introduce three different styles
of designing combinational logic in SystemVerilog.

2 8-Bit Adder/Subtractor in SAP-1

The 8-bit adder/subtractor logic circuit adds/subtracts the data contents of registers Ac-
cumulator and B Register. It takes 8-bit binary numbers from both the registers and
adds/subtracts these if Su is low/high. It sends the result to the bus if Eu is high otherwise
the output of this 8-bit adder/subtractor is made High-Z if Eu is low. This is known as
tristate-buffering.

3 SystemVerilog Codes of Combinational Logic

The SV code is to be summarized like this, ”The always block describes the behavior of the
module. It is sensitive to changes in any of the input signals (a and b). Inside the always
block, the outputs (OR, AND, NAND, NOR, INV, XOR, and XNOR) are assigned values
based on the logic operations performed on the inputs.The outputs are registered, meaning

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they will retain their values until a new value is assigned to them in the always block.”

Figure 1: SystemVerilog Code of Combinational Logic Design

There are two combinational logic tasks required in 8-bit Adder/Subtractor-one is to choose
from addition and subtraction on the basis of input Su and the other is to tristate-buffering
of the output on the basis of input Eu.

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 Figure 1: 8-Bit Adder/Subtractor (red-highlighted) in SAP-1 Microcomputer

3.1 Addition or Subtraction

Since the 8-bit adder/subtractor decides about the addition or subtraction on the basis
of logical value of input Su thus it can be implemented as multiplexing of addition and
subtraction. A multiplexing action can be implemented with following three combinational
logic coding styles

1. case statement encapsulated in always comb or always@(*) . Similar to Switch

statement in C or Java

2. if-else statement encapsulated in always comb or always@(*) . Similar to Switch

statement in C or Java
3. assign statement

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3.2 Tristate-Buffering
The result of addition or subtraction is sent to the bus through the 8-bit adder/subtractor
output therefore tristate-buffering is required at the output. A tristate-buffering can be
implemented with following two combinational logic coding style

1. multiplexing between the High-Z and output of 8-bit adder subtractor encapsulated
in always comb or always@(*)

2. multiplexing between the High-Z and output of 8-bit adder subtractor implemented
through nested multiplexing using assign statement

Figure 2: Three Different Styles of SystemVerilog Coding for Choosing between Addition
and Subtraction and Tristate-Buffering

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4 Test Bench

Figure 3: TestBench

5 Simulation

Figure 4: Simulation

Introduction:
Logisim-Evolution is a Java application, so a Java runtime environment will need to be installed before
using the application. Many students who are taking a digital logic class already have a Java runtime on
their computer and can skip this step, but those who do not will need to install the Java runtime. That
process is not covered in this man- ual but information about installing the Java runtime environment is
available at http://www.oracle.com/technetwork/java/javase/downloads/index.html. It can be
confusing to know which version of Java to download but students working on the labs in this manual
only need the runtime, called JRE on the website. Students
5 who are also in programming classes will
likely already have the runtime as part of the Java Developer’s Kit (JDK). It can be tricky testing the Java
installation since the Chrome, Firefox, and Edge browsers will not run Java apps, but students can open a
command prompt and enter java -version to see what version of Java their computers are running, if
any.
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Logisim-Evolution (logisim-evolution download | SourceForge.net) is available as a free download. Visit
the website and about halfway down the page find a section named “Running Logisim-evolution.” Click
the “here” link at the end of the first sentence in that section.
Since the Logisim-Evolution file is a Java application, it does not need to be installed like most software.
To start Logisim-Evolution, double- click the Logisim-Evolution shortcut. That will start Java and then run
the Logisim-Evolution application. Also, Logisim-Evolution will not need to be uninstalled when it is no
longer needed since it is not actually installed, the Logisim-Evolution file can simply be deleted.

1.1.1 Beginner’s Tutorial

Logisim-Evolution comes with a beginner’s tutorial available in Help

-> Tutorial. That tutorial only takes a few minutes and introduces.
students to the major components of the application. Students should complete that tutorial before
starting this lab.

1.1.2 Logisim-evolution Workspace

Start Logisim-Evolution by double-clicking its icon. The initial Logisim- Evolution window will be similar to
Figure 1.1.

Figure 1.1: Logisim-evolution Initial Screen

The Logisim-Evolution space is divided into several areas. Along the top is a text menu that includes the
types of selections found in most programs. For example, the “File” menu includes items like “Save” and
“Exit.” The “Edit” menu includes an “Undo” option that is useful. In later labs, the various options under
“Project” and “Simulate” will be described and used. Items in the “FPGAMenu” are beyond the scope of
this class and will not be used. Of particular importance at this point is “Library Reference” in the “Help”
menu. It contains information about every logical device available in Logisim-Evolution and is very useful
while using those components in new circuits. 6
Under the menu bar is the Toolbar, which is a row of eight buttons that are the most commonly used
tools in Logisim-Evolution :
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• Pointing Finger: Used to “poke” and change input values while the simulator is running.
• Arrow: Used to select components or wires in order to modify, move, or delete them.
• A: Activates the Text tool so text information can be added to the circuit.
• Green Input Port: Creates an input port for a circuit.
• White Output Port: Creates an output port for a circuit.
• NOT Gate: Creates a NOT gate.
• AND Gate: Creates an AND gate.
• OR Gate: Creates an OR gate.

The Explorer Pane is on the left side of the workspace and contains a folder list. The folders contain
“libraries” of components organized in a logical manner. For example, the “Gates” folder contains vari-
ous gates (AND, OR, XOR, etc.) that can be used in a circuit. The four icons across the top of the Explorer
Pane are used for advanced operations and will be covered as they are needed.
The Properties panel on the lower left side of the screen is where the properties for any selected
component can be read and set. For ex- ample, the number of inputs for an AND gate can be set to a
specific number.
The drawing canvas is the largest part of the screen. It is where circuits are constructed and simulated.

Moore Sequence Detector:

A Moore Sequence Detector is a digital circuit that detects a specific sequence of input signals and
generates an output accordingly.

Following is the circuit diagram for implementation of 101 sequence detector.

Method:

1. Set SIMUlATE -> TICk FREqUEnCY to 4 Hertz. This will simulate clock that ticks once
per second.

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2. Click SIMUlATE -> CHROnOGRAM to set up the

chronogram.

3. Click Start Chronogram and the screen illustrated in Figure 1.2 pops
up.

Figure 1.2: Chronogram Starting

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4. The chronogram has five buttons that control the simulator.

Figure 1.13: Chronogram Controls

• Button One: Start/Stop the simulation.

• Button Two: Simulate one step.
• Button Three: Start/Stop sysclk. This will “turn on” the
chronogram and begin creating a timing diagram.
• Button Four: Step one sysclk tick. This will tick the sysclk
one time. Since this lab set up the sysclk for four ticks per
second this button would need to be clicked four times to
extend the timing diagram one second.
• Button Five: Step one clk tick. This extends the timing di- agram
by one complete clock tick, or one second in this circuit.

5. Click button three to start the chronogram and watch the timing
diagram unfold. After a few seconds click that button a second
time to stop the chronogram.

6. The following can be done once the timing diagram is complete.

• Click on the timing diagram to set the cursor (indicated by a

red line). Once the cursor is set the values for each signal at
the cursor’s location are printed next to the signal’s label on
the left edge of the timing diagram.
• Hover the mouse over the timing diagram and roll the
mouse wheel to zoom the timing diagram appearance.

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• Click “Export” to save the timing diagram signal levels in a text file.
That file can later be loaded to reevaluate the timing diagram.
• Click “Export as image” to save the timing diagram as a PNG file.

6 Student Tasks
1. Write SystemVerilog and Test bench code of 3-bit input design for combinational logic of AND,
OR, NOT, NOR, NAND, XOR, XNOR gates.

2. Write SystemVerilog code of an 8-bit adder/subtractor

3. Try merging the two always blocks, adder/subtractor & tristate-buffering, into one
always block in case statement and if-else statement examples. If possible.
4. Save results in EDAPlayground and share with the instructor
5. Design and simulate the Moore sequence detector for 101 sequences as shown below
in the Logisim-evolution and attach the screenshots of their timing diagram as well.

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