MUHAMMAD WASEEM SABRI

Hardware

Logic gates & circuit design

Logic gates: A component of a logical circuit that can perform a Boolean operation (logical

function).

 AND Gate: A.B\ = \ XA.B = X

A B X
0 0 0
0 1 0
1 0 0
1 1 1

 OR Gate: A + B = XA+B=X

A B Output
0 0 0
0 1 1
1 0 1
1 1 1

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 NOT Gate: \overline{A}\ = \ XA = X

A Output
0 1
1 0

 NAND Gate: \overline{A.B}\ = \ XA.B = X

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A B Output
0 0 1
0 1 1
1 0 1
1 1 0

 NOR Gate: \overline{A + B} = XA+B=X

A B Output
0 0 1
0 1 0
1 0 0
1 1 0

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 XOR Gate: A.\overline{B} + \overline{A}.B = XA.B+A.B=X

A B Output
0 0 0
0 1 1
1 0 1
1 1 0

 Logic circuits: A circuit that performs logical operations on symbols.

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 Sequential circuit: a circuit whose output depends on the input values and the previous output

values. Eg: - Flip-flops (Section 3.3.4)

 Combinational circuit: a circuit whose output is dependent only on the input values

 Half-Adder: A logic circuit that adds two bits together and outputs their sum.

Input Output
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
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Boolean algebra

 Double Complement: \overline{\overline{A}} = AA=A

 Identity Law

 1.A\ = \ A1.A = A

 0 + A\ = \ A0+A = A

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 Null Law

 0.A\ = 00.A =0

 1 + A\ = \ 11+A = 1

 Idempotent Law

 A.A\ = \ AA.A = A

 A + A = AA+A=A

 Inverse Law

 A.\overline{A} = 0A.A=0

 A + \overline{A}\ = \ 1A+A = 1

 Commutative Law

 A.B\ = \ B.AA.B = B.A

 A + B\ = \ B + AA+B = B+A

 Associative

 (A.B).C\ = \ A.(B.C)(A.B).C = A.(B.C)

 (A + B) + C\ = \ A + (B + C)(A+B)+C = A+(B+C)

 Distributive Law

 A + B.C\ = \ (A + B).(A + C)A+B.C = (A+B).(A+C)

 A.\left( B + C \right) = A.B + A.CA.(B+C)=A.B+A.C

 Adsorption

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 A.\left( A + B \right) = AA.(A+B)=A

 A + A.B = AA+A.B=A

 De Morgan’s Law

 (\overline{A.B})\ = \ \overline{A}\ + \ \overline{B}(A.B) = A + B

 \left( \overline{A + B} \right) = \overline{A}.\overline{B}(A+B)=A.B

{S15-P33} Question: 5

a) i. Complete the truth table for this logic circuit:

ii. Complete the truth table for this logic circuit:

b) A student decides to write an equation for X to represent the full behaviour of each logic

circuit.

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i. Write the Boolean expression that will complete the required equation for X for each circuit:

 Circuit 1: X =

 Circuit 2: X =

ii. Write the De Morgan’s Law which is shown by your answers to part (a) and part (b)(i).

c) Write the Boolean algebraic expression corresponding to the following logic circuit:

d) Using De Morgan’s laws and Boolean algebra, simplify your answer to part (c).

 Show all your working.

Solution:

Part a):

 i. Assume that the letter “C” equates to the first function/logic gate.

 A + B = CA+B=C

A B C
0 0 0
0 1 1
1 0 1
1 1 1
0 = 0 $$

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De Morgan's law: the inverse of a Boolean product becomes the sum of the inverses of the

individual values in the product. The inverse of a Boolean sum is the product of the individual

inverses.

 Not (A and B) is the same as Not A or Not B.

 Not (A or B) is the same as Not A and Not B.

RISC processors give the opportunity of providing efficient pipelining. Pipelining is instruction

level parallelism. Its underlying principle is that the fetch decode execute cycle can be

separated into a number of stages. One of the possibilities include:

1. Instruction fetch (IF)

2. Instruction decode (ID)

3. Operand fetch (OF)

4. Instruction execute (IE)

5. Result write back (WB)

PIPELINING FOR FIVE STAGE INSTRUCTION HANDLING

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For pipelining to be implemented, the construction of the processor must have five

independent units with each handling one of the five stages identified. This explains the need

for a RISC processor to have many register sets. Each processor unit must have access to its

own set of registers. The representation 1.1, 1.2 and so on are used to define the instruction

and the stage of the instruction. Initially only the first stage of the first instruction has entered

the pipeline. At clock cycle 6 the first instruction has left the pipeline, the last stage of

instruction 2 is being handled and instruction 6 has just entered. Once under way, the pipeline

is handling 5 stages of 5 individual instructions. At each clock cycle the complete processing of

one instruction has finished. Without the pipelining the processing time would've been 5 times

longer.

One disadvantage is interrupt handling. There will be 5 instructions in the pipeline when an

interrupt occurs.

1. Erase the pipeline contents for the latest 4 instructions to have entered. Then the normal

interrupt handling routine can be applied to the remaining instruction.

2. Construct the individual units in the processor with individual program counter registers. This

allows current data to be stored for all of the instructions in the pipeline while the interrupt Is

handled.

Karnaugh Maps

 Karnaugh maps: a method of obtaining a Boolean algebra expression from a truth table

involving the

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 Benefits of using Karnaugh Maps:

 Minimises the number of Boolean expressions.

 Minimises the number of Logic Gates used, thus providing a more efficient circuit.

 Methodology

 Try to look for trends in the output, thus predict the presence of a term in the final expression

 Draw out a Karnaugh Map by filling in the truth table values into the table

 Column labelling follows Gray coding sequence

 Select groups of ‘1’ bits in even quantities (2, 4, 6 etc), if not possible then consider a single

input as a group

 Note: Karnaugh Maps wrap around columns

 Within each group only the values that remain constant are retained

{S17-P31} Question: 3

Consider the following logic circuit, which contains a redundant logic gate.

(a) Write the Boolean algebraic expression corresponding to this logic circuit. (3 Marks)

(b) Complete the truth table for this logic circuit. (2 Marks)

A B C Working Space X

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0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Flip-flops

 SR flip-flop: SR(Set-Reset) flip-flop or “Latch”

 Used as a storage device for 1 bit in the RAM, since it’s values can be altered

 Issue: When the both the input signals are 1 (invalid state) the flip-flop sets the value of Q and

Q’ to 0.

Input signals Initial state Final state

S R Q Q’ Q Q’
0 0 1 0 1 0
1 0 1 0 1 0
0 1 1 0 0 1
0 0 0 1 0 1
1 0 0 1 1 0
0 1 0 1 0 1
J K Clock Q
0 0 ↑ Q unchanged
1 0 ↑ 1
0 1 ↑ 0
1 1 ↑ Q toggles
 Flip-flops are used to build:

 Data storage elements

 Digital circuits

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RISC processors

 RISC: Reduced Instruction Set Computers.

 CISC: Complex Instruction Set Computers.

RISC CISC
Fewer instructions More instructions
Simpler instructions Complicated instructions
Small number of instruction formats Many instruction formats
Single-cycle instructions whenever possible Multi-cycle instructions
Fixed-length instructions Variable-length instructions
Only load and store instructions to address May types of instructions to address
memory memory
Fewer addressing modes More addressing modes
Multiple register sets Fewer registers
Hard-wired control unit Microprogrammed control unit
Pipelining easier Pipelining much difficult
 Pipelining: Instruction level parallelism

 Used extensively in RISC processor based systems to reduce the time taken to run processes

 Multiple registers are employed

 Interrupt handling in CISC and RISC Processors:

 As soon the interrupt is detected the current processes are paused and moved into registers

 The ISR (Interrupt Service Routine) is loaded on to the pipeline and is executed.

 When the interrupt has been serviced, the paused processes are resumed by bringing them

back from the registers to the pipeline

Parallel processing

 SISD

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 Single Instruction Single Data stream

 Found in the early computers

 Contains single processor thus no pipelining

 SIMD

 Single Data Multiple Instruction stream.

 Found in array processors

 Contains multiple processors, which have their own memory.

 MISD

 Multiple Instruction Single Data stream

 Used to sort large quantities of data.

 Contains multiple processors which process the same data

 MIMD

 Multiple Instruction Multiple Data.

 Found in modern personal computers.

 Each processor executes a different individual instruction.

 Massively parallel computers

 Computers that contain vast amounts of processing power.

 Has a bus structure to support multiple processors and a network infrastructure to support

multiple ‘Host’ computers.

 Commonly used to solve highly complex mathematical problems.

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