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©LLC i n Aug ust 201 1

Department of Electrical and Computer Engineering

EE4218
EMBEDDED HARDWARE SYSTEMS

A Step-by-Step Guide for

VHDL Simulation and FPGA Implmentation
Using Xilinx Vivado 2014.2

VHDL Design and Simulation Using Xilinx Vivado 2014.2:

This manual illustrates step-by-step instructions on how to use Xilinx’s Vivado 2014.2 software for simulation and synthesis of digital circuits using
VHDL.

NOTE:
 Save all your work in D:\MyWork if you are using a lab PC. Any files saved on the hard drive of the computers in the lab will be cleared
on a daily basis.

The procedures described in this manual involve 4 major steps:

1. Creating a new VHDL project using Xilinx Vivado 2014.2.

2. Using the VHDL Editor for coding and syntax checking.
3. Simulating the design using VHDL Test Bench and ISE Simulator.
4. FPGA implementation of a VHDL design.

After that, there is one assignment specified in Section 5 and some notes in Section 6.

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1. Xilinx Vivado: Creating a New VHDL Project

1. You can run the Xilinx Vivado 2014.2 either by

clicking the icon on Desktop or going to Start
Menu  All Programs  Xilinx Design Tools
 Vivado 2014.2  Vivado 2014.2

2. After launching the Vivado, click on Create

New Project.
The Create New Project window will appear.

3. Click Next then enter the Project Name and

Project Location
4. Click Next again and make sure the RTL
Project is selected and the Do not specify
sources at this time box is checked. Then
Next

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5. Now we need to select the FPGA device that

we are working on. Since we use the
Zedboard which is officially supported by
Xilinx, we can select the board from the
provided list.
The board is Zedboard Zynq Evaluation and
Development Kit.
Click Next to go to New Project Summary
and Finish to create the project.

6. This is the main workspace of the project

that we have just created.
The left pane, Flow Navigator, lists all the
tools we need to implement the system from
making design files to simulating the system,
generating the bitfile and finally,
downloading it to the device.
The Sources window shows all the files used
in the project.

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2. Xilinx VHDL Editor: Adding Sources – Programming – Syntax Checking

1. Click on Add Sources under Project Manager

in the Flow Navigator pane to add the design
sources.
Make sure that the Add or Create Design
Sources is selected.

2. Click Next then Create File.

Select VHDL in the drop down list.
Specify the desired file name, for example,
adder
Click OK then Finish

3. After that, we define the module as in the

picture on the left.
Since this is the simple half adder, the input
and output ports are only one bit.
Click OK to generate the VHDL file.

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4. New the newly created file is added to the

project under Design Sources.
Double click the file to open it and add the
following lines to the architecture
specification of the entity the save the file.

SUM <= A xor B;

CARRY <= A and B;

5. Basically, Vivado checks the syntax of VHDL

code whenever you save the file.
If you want further analysis of the design files
without going through the lengthy complete
synthesis process, you can click Open
Elaborated Design under RTL Analysis in the
Flow Navigator.
It will also show the schematic of the design
if there is no problem with it.

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3. A) Behavioural Simulation: Using VHDL Test Bench for Combinational

Circuits

Behavioural simulation is performed before actual design implementation on hardware to verify that the logic created is correct.

1. Click Add Sources and select Add or Create

Simulation Sources.
Click Next then Create File to create the new
VHDL file.
Choose the VHDL file type and specify the
name of the testbench, test_adder_vhdl.
Click OK then Finish.

2. The Define Module will appear but we do

not need to define the I/O ports because this
is the testbench.
Click OK then Yes to create the file.

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3. Then you see that there is a Syntax Error in

the just created file. Try to open the
Messages tab and locate the error.

4. Make the testbench for the half_adder

module we’ve just created.
You can make a testbench by yourself or use
any other tool to make a template for you
base on the I/O interfaces of your design.
Add the following stimuli to the VHDL test
bench code:
A <= '0';
B <= '0';
wait for 100ns;
A <= '0';
B <= '1';
wait for 100ns;
A <= '1';
B <= '0';
wait for 100ns;
A <= '1';
B <= '1';
wait for 100ns;
A <= '0';
B <= '0';

5. Now, we can simulate our design.

Click Run Simulation under Simulation then
Run Behavioral Simulation.

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6. The waveform tab will be opened.

Try to play with the tools inside the
green/red boxes to navigate around the
waveform.

Initially, you may not see the waveform as on

the figure because the time resolution is too
high, ps in this case.

You need to switch to full view. Select View

 Zoom Fit or the Zoom Fit icon inside the
green box.

7. You can click on any place inside the

waveform to move the yellow vertical line
along the timeline, the corresponding values
of input and output are shown in the Value
column.
a and b are the stimuli value, in other words,
the input.
sum and carry are the results of the stimuli,
in other words, the output.
To exit the Simulation, click the cross icon as
shown in red circle.

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B) VHDL Test Bench using TEXTIO

This section illustrates using text files for giving stimuli for the test bench. This enables fast verification of complex designs where a number of cases
have to be tested.

1. Add the 2 lines to the library declarations

2. Change the stimulus process (from section 3.A) to the following

stim_proc: process
file inputfile : TEXT open READ_MODE is "ip.txt";
file outputfile : TEXT open WRITE_MODE is "op.txt";
variable Lr, Lw : line;
variable ab : std_logic_vector(1 downto 0);
begin
while not endfile(inputfile) loop
wait for 100 ns;
readline (inputfile, Lr);
read(Lr, ab);
a <= ab(1);
b <= ab(0);
wait for 1 ns;
write(Lw, string'(" ab = "));
write(Lw, ab);
write(Lw, string'(" sum = "));
write(Lw, sum);
write(Lw, string'(" carry = "));
write(Lw, carry);
writeline(outputfile, Lw);
end loop;
file_close(inputfile);
file_close(outputfile);
wait;
end process;

3. Create a text file ip.txt using a text editor (eg: Notepad) with the
following contents, and save it in your project folder as ip.txt.

4. Proceed with the simulation (See step 5 onwards in section 3A).

You should be able to see the simulation window identical to that
in section 3.A.
Also, in the project folder, you should be able to see a file op.txt
with the contents as shown in the figure.

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C) VHDL Test Bench for Clocked Circuits

This section will show how to write a VHDL Test Bench for a clocked circuit, illustrated using a positive edge triggered D Flip-Flop

1. Similar to step Error! Reference source not found. to 3 of

section Error! Reference source not found., create the VHDL
code for a D-flip-flop. The VHDL codes will look like:

entity d_flip_flop is
Port ( clk : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end d_flip_flop;

architecture behavioral of d_flip_flop is

begin
process(clk)
begin
if clk'event and clk = '1' then
Q <= D;
end if;
end process;
end behavioral;

2. After the syntax has been determined to be correct, create a

VHDL Test Bench for this d_flip_flop. The steps are similar to
steps Error! Reference source not found. to Error! Reference
source not found. of section 3.
In this case, we need to make a clk_process to generate the
clock to the design.
Please use the clock period of 100 ns.

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3. If mathematical operations are being used for giving stimuli

in an automated fashion, the following two libraries might
have to be included as well:

use IEEE.STD_LOGIC_ARITH.ALL
use IEEE.STD_LOGIC_UNSIGNED.ALL;

In the example described in this section, the stimuli given

does not require the use of the above two libraries.

4. Insert the following stimuli in the VHDL test bench

wait for 25 ns;

D <= '1';

wait for 100 ns;

D <= '0';

wait for 100 ns;

D <= '0';

wait for 100 ns;

D <= '1';

wait for 100 ns;

D <= '1';

Note that the wait for 25 ns should preferably be wait

for 75 ns if negative edge triggered circuits are used. If
there is more than one input, these inputs can be
changed simultaneously in between the stimuli. In this
example, D is the only input that is being changed in
between stimuli.

5. Do the Behavioral Simulation similar to Step 5 onwards

of Section 3A to simulate the design.
In this figure, the D-flip-flop is triggered at every positive
clock cycle

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4. FPGA Implementation: Half-Adder

This section describes how to implement the design made in section 1 on an actual FPGA hardware.

1. First, make sure that the half_adder

entity is selected as Top.
Check whether the icon is shown
next to the design file.
If not, right click at choose Set as
Top.

2. Then click Project Settings in

the Flow Navigator to to verify
that the correct device is
selected.
This is very important because
the configuration file
generated by Vivado is unique
for each device.

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3. We need to add a constraint file to

tell Vivado where we want to map
the input/output ports of our design to
the actual physical I/O of the FPGA
chip.
Click Add Sources and select Add
or Create Constraints.

4. Specify the configurations as the

picture on the left. And click Finish
to generate the file.

5. Now we can see the new file

lab1_half_adder.xdc under the
Constraints.
Double click to open it, add the
constraints below and save it.

# Mapping A to SW<0>
set_property LOC F22 [get_ports A]
set_property IOSTANDARD LVCMOS18
[get_ports A]

# Mapping B to SW<1>
set_property LOC G22 [get_ports B]
set_property IOSTANDARD LVCMOS18
[get_ports B]

# Mapping SUM to LED<0>

set_property LOC T22 [get_ports
SUM]
set_property IOSTANDARD LVCMOS33
[get_ports SUM]

# Mapping SUM to LED<1>

set_property LOC T21 [get_ports
CARRY]
set_property IOSTANDARD LVCMOS33
[get_ports CARRY]

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6. Now click the Run Implementation

tool to generate the bitstream for
FPGA.
There may be a dialog asking you to
also launch the Synthesis and other
processes before generating
bitstream.
Choose Yes.
It takes a while to generate bitstream.

7. After finishing, Vivado asks you to

Open Implemented Design to view
the layout on FPGA or only view the
Reports.
Choose Open Implemented Design
then OK.

8. The layout of the implemented design

(half_adder) on FPGA will be
shown.
Since this is a very small design, it’s
hard to see from the full view.
You can click on the instance listed
in the red box, it will zoom in to its
location on FPGA.

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9. Click on Project Summary tab to

view the ultilization of the design.
In this design, we only need 1 LUT
(Lookup Table) and 4 IO pins.
Can you explain why?

10. The next steps are to download the

Programming Port bitstream to FPGA.

Before going further, make sure you

have connected the Programming
The jumpers setting must be like this. Port on the board to your computer
and it is powerred on. If you use the
lab PC, all the drivers should be pre-
Power Switch installed.

In additions, verify the position of the

jumpers as the left picture.

After that, in the Flow Navigator,

click Open Target  Open New
Target.

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11. The Open New Hardware Target

wizard will be shown. Click Next.

In the Hardware Server Settings,

select Local server then Next.

It takes a while for Vivado to detect

the connected device.

12. If it can’t detect the device, try to

power cycle the board, wait till the
drivers are loaded and take the steps
again.

If there is no problem, the wizard

shows the list of devices connected.
Here we have:
 the JTAG programming
interface in the Hardware
Targets (this JTAG interface is
built on the Zedboard)
 and 2 hardware devices (these
devices are on Zynq FPGA
chip).

Click the dropdown box of JTAG

Clock Frequency then select
30000000 Hz.

Select the xc7z020_1 device.

Click Next and Finish to save the

settings.

13. Now, we are ready to download the

bitstream to FPGA.
Click Program Device then
xc7z020_1.

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14. Click Program to download the

bitstream.
The process should take less than 30
seconds.

15. After that, try to adjust the switches

on the board and see the changes of
LEDs.

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5. Assignments

A. Implementation of a 4-bit counter (Assignment 1A, Classwork) (4 marks)

Implement a 4 bit counter on FPGA with the following specifications

1) The count direction (UP/̅̅̅̅̅̅̅̅̅̅) is controlled by a push button, and the count is shown on LEDs.
2) When a LOAD push-button is pressed, the counter is loaded asynchronously with a 4 bit VALUE set on a 4-bit DIP
switch.
3) The counter had 2 modes, controlled using an AUTO/̅̅̅̅̅̅̅̅̅̅̅̅̅ push button. In AUTO mode, the count changes once
every second. In MANUAL mode, the count changes by one when a TICK pushbutton is pressed (irrespective of the
duration for which it is kept pressed, assuming it is > 1 second).

[Hint: The frequency of the oscillator on the FPGA board is 100MHz. You will have to implement some kind of clock
scaling. An apparent clock rate in the order of 1s is fine (i.e., need not be precisely 1s). ]

B. Air Traffic Control (Assignment 1B, Homework) (6 marks)

Implement an ATC system described below as a modular finite state machine.

An automated take-off permission system is to be implemented in De Morgan’s Airport, where one runway is dedicated for
take-offs. The airport handles 8 different types of planes (numbered 0-7), broadly classified into two: narrow-body and
wide-body; usually referred to as light and heavy respectively by the ATC. Plane types numbered 1, 3 and 7 are in the heavy
category while the rest are light. A light jet taking off immediately behind a heavy jet is risky due to the wake turbulence left
behind by the heavy jet.
A plane requests take off by pressing a REQ push-button after setting its TYPE_NUMBER on a 3-bit DIP switch. The request
is GRANTED under the following 3 circumstances
1) The request is from a heavy jet
2) The request is from a light jet, and the previous jet which took off is also light
3) The request is from a light jet, the previous jet which took off is heavy, and 10 seconds have passed since the
previous jet was granted permission to take off
and is DENIED otherwise.
Results (GRANTED/DENIED) are shown using separate LEDs, for exactly 3 seconds (i.e., exactly 3 cycles of the divided clock)
immediately following the request, during which take-off requests (i.e pressing the REQ button) will have no effect.

[Hint : You will need to implement one or more counters, which should be used as component(s) controlled by a controller
FSM ]

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6. Appendix

The constraints for Zedboard.

## Constraint file for ZedBoard

###########################################
# Global Clock, which is 100MHz
###########################################
set_property PACKAGE_PIN Y9 [get_ports {GCLK}]

###########################################
# Buttons
###########################################
#Center
set_property PACKAGE_PIN P16 [get_ports {BTNC}]
#Down
set_property PACKAGE_PIN R16 [get_ports {BTND}]
#Left
set_property PACKAGE_PIN N15 [get_ports {BTNL}]
#Right
set_property PACKAGE_PIN R18 [get_ports {BTNR}]
#Up
set_property PACKAGE_PIN T18 [get_ports {BTNU}]

###########################################
# LEDs
###########################################
set_property PACKAGE_PIN T22 [get_ports {LD0}]
set_property PACKAGE_PIN T21 [get_ports {LD1}]
set_property PACKAGE_PIN U22 [get_ports {LD2}]
set_property PACKAGE_PIN U21 [get_ports {LD3}]
set_property PACKAGE_PIN V22 [get_ports {LD4}]
set_property PACKAGE_PIN W22 [get_ports {LD5}]
set_property PACKAGE_PIN U19 [get_ports {LD6}]
set_property PACKAGE_PIN U14 [get_ports {LD7}]

###########################################
# DIP Switches
###########################################
set_property PACKAGE_PIN F22 [get_ports {SW0}]
set_property PACKAGE_PIN G22 [get_ports {SW1}]
set_property PACKAGE_PIN H22 [get_ports {SW2}]
set_property PACKAGE_PIN F21 [get_ports {SW3}]
set_property PACKAGE_PIN H19 [get_ports {SW4}]
set_property PACKAGE_PIN H18 [get_ports {SW5}]
set_property PACKAGE_PIN H17 [get_ports {SW6}]
set_property PACKAGE_PIN M15 [get_ports {SW7}]

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Note for Clock circuit

The clock given by the Zedboard is 100MHz. To obtain a clock in the

order of 1Hz, we will need to divide it using a process as shown on
the left, and clk_div can be used as the clock of the system we are
designing.
Please noted that the declaration of clk_count is:

variable clk_count : std_logic_vector (26 downto 0) …

Hint : You might want to do the behavioral simulation without the

clock divider, and change the clock name in the main process after
introducing the clock divider

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