Introduction to EDA Playground

Course Code: CPE 016 Program: BSCPE

Course Title: Introduction to HDL Date Performed:10/13/2021
Section: CPE31S4 Date Submitted: 10/13/2021
Leader: 1. Christian Rabadon Instructor: Engr. Menchie Rosales
Members: 2.
3.
4.
5.
1. Objective(s):
The activity aims to demonstrate the procedures on how to use EDA Playground to simulate VHDL
codes.
2. Intended Learning Outcomes (ILOs):
The students shall be able to:
2.1 Test the step by step procedure in running VHDL codes to EDA Playground.
2.2 Generate the testbench and design codes.
2.3 Create VHDL codes of OR logic gate.
2.4 Generate the EPWave of OR logic gate.
3. Discussion:
EDA Playground gives engineers immediate hands-on exposure to simulating SystemVerilog, Verilog,
VHDL, C++/SystemC, and other HDLs. All you need is a web browser. The goal is to accelerate learning
of design/testbench development with easier code sharing and simpler access to EDA tools and
libraries.
(https://eda-playground.readthedocs.io/en/latest/intro.html)

I created a personalized video so you can have another reference.

https://www.youtube.com/watch?v=cx6bpG7JJMc
 Figure 3.1. EDA Playground Environment

Choose VHDL as the language to code VHDL in EDA playground and also you can run different codes
such as python. EDA playground lets you run a hardware design circuit codes such as VHDL in an easy
way compare when running it to ISE application.
4. Resources:
Computer System with internet access
5. Procedure:
1. Search the website www.edaplayground.com as seen in Fig.1.

Figure 5.1 Website

2. You need to log in using google or facebook account first as seen in Figure 5.2.
 Figure 5.2. Signed-in Account

3. Click your chosen account either through Google or Facebook like in Fig.3.

Figure 5.3 Chosen Google Account

4. You can see an empty work space in Fig. 5.4. From the left part is the word “testbench” and
on the right part is the word “design”. You can also see the Languages and Libraries located at
the leftmost part of the window. Select VHDL as your Testbench + Design.
 Figure 5.4 Testbench and Design

5. Write “SampleCode1” in Fig. 5.5 where you can see “Add a title to help you find your
playground”.
Same as the top entity name on the left side of the test bench window is the same name you
wrote on the title, if you remember I write the name “SampleCode1”.

Figure 5.5 Title and Top Entity

6. Click private (only you can view) beside the title text box as shows in Fig. 5.6.
 Figure 5.6. Selected Private Only

7. Hit save but a prompt message will appear stating that you need to choose simulators. Fig.
5.7 is the selected tools and simulators which is Aldec Riviera Pro 2017.02. Under the Tools &
Simulators beside the testbench window choose “Aldec Riviera Pro 2017.02”.

Figure 5.7 Tools and Simulators

8. Check the Open EPWave like in Fig. 5.8 after Run Options. Hit the save button again below
the testbench and design window to check errors.
 Figure 5.8 Open EPWave
Check the Open EPWave after run. Hit the save button again below the testbench and design
window to check errors.

9. Once SampleCode1 was saved, you can see the “library ieee; and use
ieee.std_logic_1164.all;” will appeared in the testbench and design area. Copy and paste the
given code below on the testbench area.
-- Testbench for OR gate
library IEEE;
use IEEE.std_logic_1164.all;

entity testbench is
-- empty
end testbench;

architecture tb of testbench is

-- DUT component
component or_gate is
port(
a: in std_logic;
b: in std_logic;
q: out std_logic);
end component;

signal a_in, b_in, q_out: std_logic;

begin

-- Connect DUT
 DUT: or_gate port map(a_in, b_in, q_out);

process
begin
a_in <= '0';
b_in <= '0';
wait for 1 ns;
assert(q_out='0') report "Fail 0/0" severity error;

a_in <= '0';

b_in <= '1';
wait for 1 ns;
assert(q_out='1') report "Fail 0/1" severity error;

a_in <= '1';

b_in <= 'X';
wait for 1 ns;
assert(q_out='1') report "Fail 1/X" severity error;

a_in <= '1';

b_in <= '1';
wait for 1 ns;
assert(q_out='1') report "Fail 1/1" severity error;

-- Clear inputs
a_in <= '0';
b_in <= '0';

assert false report "Test done." severity note;

wait;
end process;
end tb;

10. Change the names of the following:

From testbench” to “SampleCode1”
From “tb” to “SampleCode1tb”
You can see Fig. 5.9.
 Figure 5.9 Codes of testbench
And hit “Save” button at the top of the testbench area.

11. Copy and paste the following code to design area on the right side of the testbench area:
-- Simple OR gate design
library IEEE;
use IEEE.std_logic_1164.all;

entity or_gate is
port(
a: in std_logic;
b: in std_logic;
q: out std_logic);
end or_gate;

architecture rtl of or_gate is

begin
process(a, b) is
begin
q <= a or b;
end process;
end rtl;
You can see Fig. 5.10.
 Figure 5.10 Testbench and Design Codes

CHANGE the following names:

From “or_gate” to “Design or_gate”
From “rtl” to “Designrtl”
Then hit “Save” at the top of the testbench area.

12. Now inside the testbench part you can see the word component as seen in Fig. 5.11.

Figure 5.11 Checking the Component Name

Again change the name “or_gate” to “Designor_gate” and hit save again at the top of the
testbench part.

13. Click run the program in Fig. 5.12.

 Figure 5.12 Running the Program

14. You can now see the EPwave which mean EDA Playground waveform in Fig. 5.13.

Figure 5.13 EPWave

15. You can choose radix to change either hex or binary numbers for the variable value in Fig.
5.14.
 Figure 5.14 Radix Value

Once you change the radix to binary you can see the values

Figure 5.15 Binary Values

16. You can also change the zoom view in Fig. 5.16.
 Figure 5.16 Zoom View

17. Move left or right the vertical yellow line to different location in Fig.5.17.

Figure 5.17 Yellow Line1

X means no value was given from the testbench but of course since this is an OR gate logic
once there is a high value it is always equivalent to 1 in Fig.5.18.
 Figure 5.18 Yellow Line 2

Note for the errors of the codes:

 One error you might encounter is the spacing
 Always logout EDAPlayground account every after one program
 Always change the name of the top entity and the title because top entity must be the same as
the title name. Also, testbench name such as the SampleCode1 must be the same as the top
entity name
 The name of the design must be the same as the name of the design after begin architecture
(like Design_or_gate)
 The name of the design must have no spaces
 You need to type all the codes because it might cause an error
6. Activity
6.1 Create the VHDL Module of NOR gate.
6.2 Produce the EPWave of the NOR gate on the space provided.
6.1.1 Write the design code

-- Code your testbench here

library IEEE;
use IEEE.std_logic_1164.all;

entity SampleCode1 is
-- empty
end SampleCode1;

architecture SampleCode1TB of SampleCode1 is

-- DUT component
component nor_gate is
port(
a: in std_logic;
b: in std_logic;
q: out std_logic);
end component;

signal a_in, b_in, q_out: std_logic;

begin

-- Connect DUT
DUT: nor_gate port map(a_in, b_in, q_out);

process
begin
a_in <= '0';
b_in <= '0';
wait for 1 ns;
assert(q_out='0') report "Fail 0/0" severity error;

a_in <= '0';

b_in <= '1';
wait for 1 ns;
assert(q_out='1') report "Fail 0/1" severity error;

a_in <= '1';

b_in <= 'X';
wait for 1 ns;
assert(q_out='1') report "Fail 1/X" severity error;

a_in <= '1';

b_in <= '1';
wait for 1 ns;
assert(q_out='1') report "Fail 1/1" severity error;

-- Clear inputs
a_in <= '0';
b_in <= '0';

assert false report "Test done." severity note;

wait;
end process;
end SampleCode1TB;

-- Code your design here

library IEEE;
use IEEE.std_logic_1164.all;

entity nor_gate is
port(
a: in std_logic;
b: in std_logic;
q: out std_logic);
end nor_gate;

architecture rtl of nor_gate is

begin
process(a, b) is
begin
q <= a nor b;
end process;
end rtl;

6.2.1 Screenshot of EPWave for NOR gate.

 7. Question/s: (Answer the following questions based on your observation from the experiment)
7.1 What are your observations from using EDA Playground?
My observation in eda playground if you do not know basic logic gates for you it will cause confusion what
you want display of your waveform then regarding to radix and hexadecimal it causes different value of your
input and output. If yellow line higher to your corresponding it marked input or output x.

8. Data and Results:

Change the Run Time in EPAWave. Write the results in table 1.1

Table 1.1 NOR Gate in 10 ns

Every 10 ns Input(A) Input(B) Output(F)
10ns 0 1 0
20ns 0 1 0
30ns 0 1 0
40ns 0 1 0
50ns 0 1 0
50ns 0 1 0
9. Conclusion:
In this activity we get new knowledge regarding using edaplayground for coding logic gates and simulate to
visualize waveform. If notice yellow line gives possible hints about input and output of waveform if yellow
line higher marked of your values, it gets value x means no value given for the test bench. Since nor gate it
no higher value equivalent corresponding to your value.
10. Assessment (Rubric for Laboratory Performance):