Dr. B. C.

ROY POLYTECHNIC
Durgapur-713206
Program name : Computer Science and Technology

Program Name Computer Sc. & Technology

Computer System
Course Name Course Code CS207
Organization
Duration: 50 mins Sem: 3rd Lec-23 Session: 2023-26
Unit No: 4

• Instruction format

• Internal organization of register

• Fields of instruction format and

their types
Topics to be covered
• Different types of register orga-
nization

• Example of coding using register

organization

Learning Outcomes:
Students will be able to:

• Illustrate the concept of instruction format

• Fields of instruction format and their types

• Describe instruction format depending on the internal organization of register

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Note:

1 Prerequisite
1. Program: Program is a sequence of

2. Instruction: An instruction is a command given to the computer to perform a specific

operation.

• An instruction is a group of bits that instructs the computer to perform a specific

operation
• The purpose of an instruction is to specify both operation to be performed by CPU
and the set of operands (or data).
– Operation include addition, subtraction, multiplication, shift etc. Operations
are performed on data (operands)
– Operands include the input data and the result that are produced.

2 Instruction Formats
In computer organization, instruction formats refer to the binary format in which instructions
are encoded to represented in machine language. The bits of the instructions are divided into
groups called fields. The most common fields in instruction format are:

1. Opcode(Operation Code): An opcode field (in binary) specifies the operation to be per-
formed such as add, subtract, multiply, shift, complement etc.

2. Address: An address field specifies a memory address or processor register, where operand
is stored.

3. Mode: A mode field specifies the way the operand or the effective address of the operand
is determined (or located).

Figure 1: Instruction format (with mode field)

• Computers may have instructions of several different lengths containing varying number
of addresses (address field may be 3,2,1 or 0).

• The number of address field in the instruction format of a computer depends on the
internal organization of its registers.

There are several types of instruction formats, including zero, one, two, and three-address
instructions.
Each type of instruction format has its own advantages and disadvantages in terms of code size,
execution time, and flexibility. Modern computer architectures typically use a combination of
these formats to provide a balance between simplicity and power.

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3 Classification of instruction based on CPU organiza-
tion
1. Single Accumulator organization

• All operations are performed on an implied accumulator register

• With one operand implicitly in the Accumulator register minimizes the complexity
of machine & allow for short instruction
• The instruction format uses only one address field (i.e. one address instruction
format)

This organization was used in 1st generation computers due to the high cost of registers.
Examples are, Intel 8008, Intel 4004, intel 8085, IBM 701, ENIAC, 8051 microcontroller.

2. General register organization

• It uses set of general purpose registers (R0,R1,R2)

• It is most widely used organization
• It specifies all operands explicitly
• Instruction format needs two or three address fields according to operation (i.e. two
or three address instruction format)

3. Stack organization

• The operands are put into stack and operations are caried out on top of stack (ToS).
The operands are implicitly specified on ToS.
• It does not use and address field for the instructions like ADD, MUL, etc (i.e Zero
address instruction format)
• PUSH and POP instructions are used to communicate with stack which require an
address field

4 Types of Instructions
Based on the number of addresses present in the instruction, instructions are classified as:

4.1 Zero address instruction

These instructions do not specify any operands or addresses. Instead, they operate on data
stored in registers or memory locations implicitly defined by the instruction. For example, a
zero-address instruction might simply add the contents of two registers together without spec-
ifying the register names. Example of zero address instruction:

PUSH A
PUSH B
ADD
POP C

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4.2 One Address Instructions
These instructions specify one operand or address, which typically refers to a memory location
or register. The instruction operates on the contents of that operand, and the result may be
stored in the same or a different location. For example, a one-address instruction might load
the contents of a memory location into a register.
This uses an implied ACCUMULATOR register for data manipulation. One operand is in
the accumulator and the other is in the register or memory location. Implied means that the
CPU already knows that one operand is in the accumulator so there is no need to specify it.
Example of One address instruction:

LOAD X ; AC← M[X]

ADD X ; AC ← AC+M[X]
STORE Y ; M[Y]←AC

4.3 Two address Instructions

These instructions specify two operands or addresses, which may be memory locations or regis-
ters. The instruction operates on the contents of both operands, and the result may be stored in
the same or a different location. For example, a two-address instruction might add the contents
of two registers together and store the result in one of the registers.
This is common in commercial computers. Here two addresses can be specified in the in-
struction. Unlike earlier in one address instruction, the result was stored in the accumulator,
here the result can be stored at different locations rather than just accumulators, but require
more number of bit to represent the address. Two address example is given as follows:

ADD R1,R2; R1 ← R1+R2

4.4 Three address Instructions

These instructions specify three operands or addresses, which may be memory locations or
registers. The instruction operates on the contents of all three operands, and the result may
be stored in the same or a different location. For example, a three-address instruction might
multiply the contents of two registers together and add the contents of a third register, storing
the result in a fourth register.
This has three address fields to specify a register or a memory location. Programs created
are much short in size but number of bits per instruction increases. These instructions make
the creation of the program much easier but it does not mean that program will run much faster
because now instructions only contain more information but each micro-operation (changing
the content of the register, loading address in the address bus etc.) will be performed in one
cycle only. For example,

ADD R1,R2,R3 ; R1←R2+R3

5 Advantages of Zero-Address, One-Address, Two-Address

and Three-Address Instructions
5.1 Advantages of Zero address instruction
1. Stack-based Operations: In stack-based architectures, where operations implicitly employ
the top items of the stack, zero-address instructions are commonly used.

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 2. Reduced Instruction Set: It reduces the complexity of the CPU design by streamlining
the instruction set, which may boost reliability.

3. Less Decoding Complexity: Especially helpful for recursive or nested processes, which are
frequently used in function calls and mathematical computations.

4. Efficient in Nested Operations: Less bits are required to specify operands, which simplifies
the logic involved in decoding instructions.

5. Compiler Optimization: Because stacks are based on stacks, several algorithms can take
use of this to improve the order of operations.

5.2 Advantages of One address instruction

1. Intermediate Complexity: Strikes a balance between versatility and simplicity, making
it more adaptable than zero-address instructions yet simpler to implement than multi-
address instructions.

2. Reduced Operand Handling: Compared to multi-address instructions, operand fetching

is made simpler by just needing to handle a single explicit operand.

3. Implicit Accumulator: O ften makes use of an implicit accumulator register, which can
expedite up some operations’ execution and simplify designs in other situations.

4. Code Density: S maller code in comparison to two- and three-address instructions, which
may result in more efficient use of memory and the instruction cache.

5. Efficient Use of Addressing Modes: Can make use of different addressing modes (such
indexed, direct, and indirect) to improve flexibility without adding a lot of complexity.

5.3 Advantages of Two address instruction

1. Improved Efficiency: Allows for the execution of operations directly on memory or regis-
ters, which reduces the amount of instructions required for certain activities.

2. Flexible Operand Use: Increases programming variety by offering more options for operand
selection and addressing modes.

3. Intermediate Data Storage: May directly store interim results, increasing some algo-
rithms’ and calculations’ efficiency.

4. Enhanced Code Readability: Produces code that is frequently easier to read and compre-
hend than one-address instructions, which is beneficial for maintenance and troubleshoot-
ing.

5. Better Performance: Better overall performance can result from these instructions because
they minimize the amount of memory accesses required for certain processes.

5.4 Advantages of Three address instruction

1. Direct Representation of Expressions: Reduces the need for temporary variables and extra
instructions by enabling the direct representation of complicated expressions.

2. Parallelism: Allows for the simultaneous fetching and processing of several operands,
which facilitates parallelism in CPU architecture.

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 3. Compiler Optimization: Makes it possible for more complex compiler optimizations to be
implemented, which improve execution efficiency by scheduling and reordering instruc-
tions.

4. Reduced Instruction Count: May increase execution performance even with bigger in-
struction sizes by perhaps lowering the overall number of instructions required for com-
plicated processes.

5. Improved Pipeline Utilization: More information in each instruction allows CPU pipelines
to be used more efficiently, increasing throughput overall.

6. Better Register Allocation: Permits direct manipulation of several registers inside a single
instruction, enabling more effective usage of registers.

6 Disadvantages of Zero-Address, One-Address, Two-

Address and Three-Address Instructions
6.1 Disadvantages of zero address instruction
1. Stack Dependency: In contrast to register-based architectures, zero-address instructions
might result in inefficiencies when it comes to operand access because of their heavy
reliance on the stack.

2. Overhead of Stack Operations: Performance might be negatively impacted by the frequent

push and pop actions needed to maintain the stack.

3. Limited Addressing Capability: The processing of intricate data structures may become
more difficult since they do not directly support accessing memory regions or registers.

4. Difficult to Optimize: Because operand access is implied in stack-based designs, code

optimization might be more difficult.

5. Harder to Debug: When compared to register-based operations, stack-based operations

might be less obvious and more difficult to debug.

6.2 Disadvantages of one address instruction

1. Accumulator Bottleneck: Often uses an accumulator, which can act as a bottleneck and
reduce efficiency and parallelism.

2. Increased Instruction Count: Multiple instructions may be needed for complex processes,
which would increase the overall number of instructions and code size.

3. Less Efficient Operand Access: There is just one operand that is specifically addressed,
which might result in inefficient access patterns and extra data management instructions.

4. Complex Addressing Modes: The instruction set and decoding procedure get more com-
plicated when several addressing modes are supported.

5. Data Movement Overhead: Moving data between memory and the accumulator could
need more instructions, which would increase overhead.

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6.3 Disadvantages of two address instruction
1. Operand Overwriting: Usually, the result overwrites one of the source operands, which
might lead to an increase in the number of instructions needed to maintain data.

2. Larger Instruction Size: Because two-address instructions are bigger than zero- and one-
address instructions, the memory footprint may be increased.

3. Intermediate Results Handling: It is frequently necessary to handle intermediate outcomes

carefully, which can make programming more difficult and result in inefficiencies.

4. Decoding Complexity: The design and performance of the CPU may be impacted by the
greater complexity involved in decoding two addresses.

5. Inefficient for Some Operations: The two-address style could still be inefficient for some
tasks, needing more instructions to get the desired outcome.

6.4 Disadvantages of Three address instruction

1. Largest Instruction Size: Has the highest memory requirements per instruction, which
can put strain on the instruction cache and increase code size.

2. Complex Instruction Decoding: Three addresses to decode adds complexity to the CPU
architecture, which might affect power consumption and performance.

3. Increased Operand Fetch Time: Each instruction may execute more slowly if obtaining
three operands takes a long period.

4. Higher Hardware Requirements: Has the potential to raise cost and power consumption
since it requires more advanced hardware to handle the higher operand handling and
addressing capabilities.

5. Power Consumption: Higher power consumption is a crucial factor for devices that run on
batteries since it can be caused by more complicated instructions and increased memory
utilization.

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 Question and Answers

Q: Illustrate the following expressing using zero address instruction

X=(A+B)*(C+D)
A: First we need to perform the Reverse Polish Notation for the expression, which is given by:
X=AB+CD+*
Instruction:

PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
MUL
POP X

Q: Illustrate the following expressing using one address instruction

X=(A+B)*(C+D)
A: Instructions:

LOAD A ; AC ← m[A]
ADD B ; AC ← AC+M[B]
STORE T ; M[T] ← AC
LOAD C ; AC ← M[C]
ADD D ; AC ← AC + M[D]
MUL T ; AC ← AC + M[T]
STORE X ; M[X]←AC