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instruction format

The document discusses various aspects of computer architecture, including stack operations, instruction formats, addressing modes, and data transfer and manipulation instructions. It provides examples of arithmetic expressions in reverse Polish notation, different types of CPU organizations, and the impact of addressing modes on instruction execution. Additionally, it covers program control instructions and conditional branch instructions, detailing how they operate within a CPU.

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0% found this document useful (0 votes)
4 views26 pages

instruction format

The document discusses various aspects of computer architecture, including stack operations, instruction formats, addressing modes, and data transfer and manipulation instructions. It provides examples of arithmetic expressions in reverse Polish notation, different types of CPU organizations, and the impact of addressing modes on instruction execution. Additionally, it covers program control instructions and conditional branch instructions, detailing how they operate within a CPU.

Uploaded by

tisap41181
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Let SP = 000000 in the stack 64 of registers .

How many items are there in


the stack if:
a.) FULL = 1 and EMTY = 0?

b.) FULL = 0 and EMTY = 1?


• Convert the following numerical arithmetic expression into reverse
Polish notation and show the stack operations for evaluating the
numerical result.

• (3 + 4)[10(2 + 6) + 8]
• 34 + 2 6 + 10 * 8 + *
• 3 4 + 2 6 + 10 * 8 + *

6 10 8
4 2 2 8 8 80 80 88
3 3 7 7 7 7 7 7 7 7 616
Instruction Format

INSTRUCTION FORMAT

• Reference manuals / Datasheets


– Specifications of the processor.
– The physical and logical structure of computers
– the internal construction of the CPU
– processor registers
– Addressing modes

• A computer have a variety of instruction code formats.


• Function of the control unit within the CPU
– to interpret each instruction code
– provide the necessary control functions needed to process the instruction
Instruction Format

INSTRUCTION FORMAT
Instruction Fields

OP-code field - specifies the operation to be performed


Address field - designates memory address(es) or a processor register(s)
Mode field - specifies the way the operand or the effective address is determined

• The number of address fields in the instruction format depends


on the internal organization of CPU

• Operations specified by computer instructions are executed on


some data stored in memory or processor registers

• Operands residing in memory are specified by their memory address.


• Operands residing in processor registers are specified with a register
address.
Three types of CPU organizations
• Single accumulator organization.
– All operations are performed with an implied accumulator register.
– The instruction format in this type of computer uses one address field
– Example ADD X /* AC ← AC + M[X] */
• General register organization.
– The instruction format in this type of computer needs three register address fields.
» ADD R1, R2, R3
– can be reduced from three to two if the destination register is the same as one of the source
registers
» ADD R1, R2
» MOV R1, R2 /* R1 ← R2 */
» ADD R1, X /* R1 ← R1 + M[X] */

• Stack organization.
– PUSH and POP instructions which require an address field
» PUSH X /* TOS ← M[X] */
– Operation-type instructions do not need an address
» ADD
Influence of the number of addresses on computer
instruction
- X = (A + B) * (C + D) :

- 4 arithmetic operations : ADD, SUB, MUL, DIV


- 1 transfer operation to and from memory and general
register : MOV
- 2 transfer operation to and from memory and AC register :
STORE, LOAD
- Operand memory addresses : A, B, C, D
- Result memory address : X
Instruction Format

THREE ADDRESS INSTRUCTIONS

Three-Address Instructions
Program to evaluate X = (A + B) * (C + D) :

ADD R1, A, B /* R1 ← M[A] + M[B] */


ADD R2, C, D /* R2 ← M[C] + M[D] */
MUL X, R1, R2 /* M[X] ← R1 * R2 */

- Results in short programs


- Instruction becomes long (many bits)
Instruction Format

TWO-ADDRESS INSTRUCTIONS
Two-Address Instructions
Program to evaluate X = (A + B) * (C + D) :

MOV R1, A /* R1 ← M[A] */


ADD R1, B /* R1 ← R1 + M[A] */
MOV R2, C /* R2 ← M[C] */
ADD R2, D /* R2 ← R2 + M[D] */
MUL R1, R2 /* R1 ← R1 * R2 */
MOV X, R1 /* M[X] ← R1 */
Instruction Format

ONE ADDRESS INSTRUCTIONS


One-Address Instructions
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :

LOAD A /* AC ← M[A] */
ADD B /* AC ← AC + M[B] */
STORE T /* M[T] ← AC */
LOAD C /* AC ← M[C] */
ADD D /* AC ← AC + M[D] */
MUL T /* AC ← AC * M[T] */
STORE X /* M[X] ← AC */
Instruction Format

ZERO-ADDRESS INSTRUCTIONS
Zero-Address Instructions

- Can be found in a stack-organized computer


- Program to evaluate X = (A + B) * (C + D) :

PUSHA /* TOS ← A */
PUSHB /* TOS ← B */
ADD /* TOS ← (A + B)*/
PUSHC /* TOS ← C */
PUSHD /* TOS ← D */
ADD /* TOS ← (C + D)*/
MUL /* TOS ← (C + D) * (A + B) */
POP X /* M[X] ← TOS */
A computer has 32-bit instructions and 12-bit addresses.
If there are 250 two-address instructions, how many one-
address instructions can be formulated?

8 12 12 32 bits

Opcode Address Address Two Address Instructions

28 = 256 combinations.
256 – 250 = 6 combinations can be used for one address
6 x 212 12 32 bits

Opcode Address
One Address Instructions

Maximum number of one address instruction:


= 6 x 212 = 24,576
Write a program to evaluate the arithmetic statement:

X= A-B+C*(D*E-F)
G+H*K
a. Using a general register computer with three address
instructions.
b. Using a general register computer with two address
instructions.
c. Using an accumulator type computer with one address
instructions.
d. Using a stack organized computer with zero-address
operation instructions.
Addressing Modes

ADDRESSING MODES

Addressing Modes

* Specifies a rule for interpreting or modifying the address field of the instruction (before the
operand is actually referenced)

* Variety of addressing modes


- to give programming flexibility to the user
- to use the bits in the address field of the instruction efficiently
Addressing Modes

TYPES OF ADDRESSING MODES


Implied Mode
Address of the operands are specified implicitly in the definition of the instruction
- No need to specify address in the instruction
- EA = AC, or EA = Stack[SP]

Immediate Mode
Instead of specifying the address of the operand, operand itself is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand

Register Mode
Address specified in the instruction is the register address
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory addressing
- EA = IR(R) (IR(R): Register field of IR)
Addressing Modes

TYPES OF ADDRESSING MODES


Register Indirect Mode
Instruction specifies a register which contains the memory address of the operand
- Saving instruction bits since register address is shorter than the memory address
- Slower to acquire an operand than both the register addressing or memory
addressing
- EA = [IR(R)] ([x]: Content of x)

Register used in Register Indirect Mode may have


Autoincrement or Autodecrement features
- When the address in the register is used to access memory, the value in the
register is incremented or decremented by 1 automatically

Direct Address Mode


Instruction specifies the memory address which can be used directly to the physical
memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address for a large physical memory
space
- EA = IR(addr) (IR(addr): address field of IR)
Addressing Modes
TYPES OF ADDRESSING MODES
Indirect Addressing Mode
The address field of an instruction specifies the address of a memory location that
contains the address of the operand
- When the abbreviated address is used large physical memory can be addressed
with a relatively small number of bits
- Slow to acquire an operand because of an additional memory access
- EA = M[IR(address)]
Relative Addressing Modes
The Address fields of an instruction specifies the part of the address
(abbreviated address) which can be used along with a designated register to
calculate the address of the operand
- Address field of the instruction is short
- Large physical memory can be accessed with a small number of
address bits
- EA = f(IR(address), R), R is sometimes implied
3 different Relative Addressing Modes depending on R;
* PC Relative Addressing Mode(R = PC)
- EA = PC + IR(address)
* Indexed Addressing Mode(R = IX, where IX: Index Register)
- EA = IX + IR(address)
* Base Register Addressing Mode(R = BAR, where BAR: Base Address Register)
- EA = BAR + IR(address)
Addressing Modes

ADDRESSING MODES - EXAMPLES -


Address Memory
200 Load to AC Mode
PC = 200 201 Address = 500
202 Next instruction
R1 = 400

399 450
XR = 100
400 700

AC
500 800

600 900

Addressing Effective Content 702 325


Mode Address of AC
Direct address 500 /* AC ← (500) */ 800
Immediate operand - /* AC ← 500 */ 500 800 300
Indirect address 800 /* AC ← ((500)) */ 300
Relative address 702 /* AC ← (PC+500) */ 325
Indexed address 600 /* AC ← (RX+500) */ 900
Register - /* AC ← R1 */ 400
Register indirect 400 /* AC ← (R1) */ 700
Autoincrement 400 /* AC ← (R1)+ */ 700
Autodecrement 399 /* AC ← -(R) */ 450
A two-word instruction is stored in memory at an address designated by the symbol W. The
address field of the instruction (stored at W + 1) is designated by the symbol Y. The operand
used during the execution of the instruction is stored at an address symbolized by Z. An index
register contains the value X. State how Z is calculated from the other addresses if the
addressing mode of the instruction is : a. direct b. indirect c. relative d. indexed

a. direct
Z=Y
a. indirect
Z =M[Y]
a. relative
Z= Y+W+2
a. indexed
Z = Y +W
Data Transfer and Manipulation

DATA TRANSFER INSTRUCTIONS


Typical Data Transfer Instructions
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

Data Transfer Instructions with Different Addressing Modes


Assembly
Mode Convention Register Transfer
Direct address LD ADR AC ← M[ADR]
Indirect address LD @ADR AC ← M[M[ADR]]
Relative address LD $ADR AC ← M[PC + ADR]
Immediate operand LD #NBR AC ← NBR
Index addressing LD ADR(X) AC ← M[ADR + XR]
Register LD R1 AC ← R1
Register indirect LD (R1) AC ← M[R1]
Autoincrement LD (R1)+ AC ← M[R1], R1 ← R1 + 1
Autodecrement LD -(R1) R1 ← R1 - 1, AC ← M[R1]
Data Transfer and Manipulation

DATA MANIPULATION INSTRUCTIONS


Three Basic Types: Arithmetic instructions
Logical and bit manipulation instructions
Shift instructions
Arithmetic Instructions
Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with Carry ADDC
Subtract with Borrow SUBB
Negate(2’s Complement) NEG

Logical and Bit Manipulation Instructions Shift Instructions


Name Mnemonic Name Mnemonic
Clear CLR Logical shift right SHR
Complement COM Logical shift left SHL
AND AND Arithmetic shift right SHRA
OR OR Arithmetic shift left SHLA
Exclusive-OR XOR Rotate right ROR
Clear carry CLRC Rotate left ROL
Set carry SETC Rotate right thru carry RORC
Complement carry COMC Rotate left thru carry ROLC
Enable interrupt EI
Disable interrupt DI
Program Control

PROGRAM CONTROL INSTRUCTIONS


+1
In-Line Sequencing
(Next instruction is fetched from the next adjacent location in the
PC memory)

Address from other source; Current Instruction, Stack, etc


Branch, Conditional Branch, Subroutine, etc
Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL * CMP and TST instructions do not retain their
Return RTN results of operations(- and AND, respectively).
Compare(by - ) CMP They only set or clear certain Flags.
Test(by AND) TST

Status Flag Circuit A B


8 8
c7
c8 8-bit ALU
F7 - F0 Let A = 11110000 B = 00010100
V Z S C
F7
A-B produces C =1, S=1, V= 0, Z=0
Check for 8
zero output
F
Program Control

CONDITIONAL BRANCH INSTRUCTIONS

Mnemonic Branch condition Tested condition


BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0
BP Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
BNV Branch if no overflow V=0
Unsigned compare conditions (A - B)
BHI Branch if higher A>B
BHE Branch if higher or equal A≥B
BLO Branch if lower A<B
BLOE Branch if lower or equal A≤B
BE Branch if equal A=B
BNE Branch if not equal A≠B
Signed compare conditions (A - B)
BGT Branch if greater than A>B
BGE Branch if greater or equal A≥B
BLT Branch if less than A<B
BLE Branch if less or equal A≤B
BE Branch if equal A=B
BNE Branch if not equal A≠B
Program Control

SUBROUTINE CALL AND RETURN


SUBROUTINE CALL Call subroutine
Jump to subroutine
Branch to subroutine
Branch and save return address
Two Most Important Operations are Implied;

* Branch to the beginning of the Subroutine


- Same as the Branch or Conditional Branch

* Save the Return Address to get the address of the location in the Calling Program
upon exit from the Subroutine

- Locations for storing Return Address


• Fixed Location in the subroutine(Memory) CALL
• Fixed Location in memory SP ← SP - 1
• In a processor Register M[SP] ← PC
• In a memory stack PC ← EA
- most efficient way
RTN
PC ← M[SP]
SP ← SP + 1
Program Control

INTERRUPT PROCEDURE
Interrupt Procedure and Subroutine Call
- The interrupt is usually initiated by an internal or
an external signal rather than from the execution of
an instruction (except for the software interrupt)

- The address of the interrupt service program is


determined by the hardware rather than from the
address field of an instruction

- An interrupt procedure usually stores all the


information necessary to define the state of CPU
rather than storing only the PC.

The state of the CPU is determined from;


Content of the PC
Content of all processor registers
Content of status bits
Many ways of saving the CPU state
depending on the CPU architectures
Program Control

PROGRAM INTERRUPT
Types of Interrupts
External interrupts
External Interrupts initiated from the outside of CPU and Memory
- I/O Device -> Data transfer request or Data transfer complete
- Timing Device -> Timeout
- Power Failure
- Operator

Internal interrupts (traps)


Internal Interrupts are caused by the currently running program from illegal or erroneous
use of instruction.
- Register, Stack Overflow
- Divide by zero
- OP-code Violation
- Protection Violation

Software Interrupts
Both External and Internal Interrupts are initiated by the computer HW.
Software Interrupts are initiated by the executing an instruction.
- Supervisor Call -> Switching from a user mode to the supervisor mode
-> Allows to execute a certain class of operations
which are not allowed in the user mode

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