AUTOSAR CP EXP FunctionalSafetyMeasures
AUTOSAR CP EXP FunctionalSafetyMeasures
AUTOSAR
AUTOSAR CP R23-11
4
• New Chapter: Hardware Diagnostics
AUTOSAR covers Core Test and RAM Test.
2015-07-31 4.2.2 Release
Management • Minor corrections / clarifications /
editorial changes.
AUTOSAR
2014-10-31 4.2.1 Release • Initial Release
Management
Disclaimer
This work (specification and/or software implementation) and the material contained in
it, as released by AUTOSAR, is for the purpose of information only. AUTOSAR and the
companies that have contributed to it shall not be liable for any use of the work.
The material contained in this work is protected by copyright and other types of intel-
lectual property rights. The commercial exploitation of the material contained in this
work requires a license to such intellectual property rights.
This work may be utilized or reproduced without any modification, in any form or by
any means, for informational purposes only. For any other purpose, no part of the work
may be utilized or reproduced, in any form or by any means, without permission in
writing from the publisher.
The work has been developed for automotive applications only. It has neither been
developed, nor tested for non-automotive applications.
The word AUTOSAR and the AUTOSAR logo are registered trademarks.
Contents
1 Introduction 7
1.1 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Functional Safety Mechanisms 9
2.1 Memory Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2.1 Application Software . . . . . . . . . . . . . . . . . . . 11
2.1.2.2 OS Applications . . . . . . . . . . . . . . . . . . . . . . 12
2.1.2.3 Communication and Code Sharing . . . . . . . . . . . 13
2.1.2.4 Memory Partitioning within Application Software . . . . 14
2.1.2.5 Memory Partitioning within Software Components . . . 15
2.1.2.6 Implementation of Memory Partitioning . . . . . . . . . 17
2.1.3 Detection and Reaction . . . . . . . . . . . . . . . . . . . . . . 20
2.1.4 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1.5 References to AUTOSAR Documents . . . . . . . . . . . . . . 21
2.1.6 References to ISO26262 . . . . . . . . . . . . . . . . . . . . . 21
2.2 Timing Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.1 Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.2.1 Supervised Entities . . . . . . . . . . . . . . . . . . . . 23
2.2.2.2 Watchdog Manager . . . . . . . . . . . . . . . . . . . . 23
2.2.2.3 Timing Protection of the Operating System . . . . . . 25
2.2.3 Detection and Reaction . . . . . . . . . . . . . . . . . . . . . . 26
2.2.4 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2.5 References to AUTOSAR Documents . . . . . . . . . . . . . . 28
2.2.6 References to ISO26262 . . . . . . . . . . . . . . . . . . . . . 28
2.3 Logical Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.1 Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.3 Detection and Reaction . . . . . . . . . . . . . . . . . . . . . . 31
2.3.4 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3.5 References to AUTOSAR Documents . . . . . . . . . . . . . . 33
2.3.6 References to ISO26262 . . . . . . . . . . . . . . . . . . . . . 33
2.4 End-2-End Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.4.1 Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.4.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.4.2.1 End-2-End Profiles . . . . . . . . . . . . . . . . . . . . 36
2.4.2.2 End-2-End State Machine . . . . . . . . . . . . . . . . 40
2.4.2.3 Integration of the End-2-End Protection Library . . . . 41
2.4.2.4 End-2-End Protection Wrapper . . . . . . . . . . . . . 42
A Appendix 77
A.1 Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 77
B Related Documentation 78
1 Introduction
Functional safety is a system characteristic which is taken into account from the begin-
ning, as it may influence system design decisions. Therefore AUTOSAR specifications
include requirements related to functional safety.
Aspects such as complexity of the system design can be relevant for the achievement
of functional safety in the automotive field.
Software is one parameter that can influence complexity on system level. New tech-
niques and concepts for software development can be used in order to minimize com-
plexity and therefore can ease the achievement of functional safety.
AUTOSAR supports the development of safety-related systems by offering safety mea-
sures and mechanisms. However AUTOSAR is not a complete safe solution.
The use of AUTOSAR does not imply [1, ISO 26262] compliance. It is still possible to
build unsafe systems using the AUTOSAR safety measures and mechanisms.
1.1 Disclaimer
This explanatory document represents the functional safety measures and mecha-
nisms of the latest release of AUTOSAR. Some of the described mechanisms and
measures may be implemented differently or may not be available in previous releases.
The user of this document shall always consult the applicable referenced documents.
1.2 Scope
The content of this document is structured into separate chapters as follows:
Functional Safety Mechanisms: This chapter contains AUTOSAR functional safety
mechanisms related to freedom from interference between AUTOSAR SW-Cs.
• Memory: Partitioning mechanisms of AUTOSAR with the context of Application
Software development and deployment.
• Timing: Temporal Program Flow Monitoring mechanisms using the Watchdog
Manager and Timing Protection mechanisms using the Operating System.
• Execution: Logical Supervision mechanisms using the Watchdog Manager.
• Exchange of Information: Communication fault detection mechanisms using the
End-2-End Library and Extensions.
Functional Safety Measures: This chapter contains topics related to the development
of safety-relevant systems. The following items are covered:
1.3 Purpose
Information about AUTOSAR functional safety mechanisms and measures is cur-
rently distributed throughout the referenced documentation. Unless one knows how
functional safety mechanisms are supported and where the necessary information is
specifically located, it is difficult to evaluate how a safety-relevant system can be im-
plemented using AUTOSAR efficiently.
This explanatory document summarizes the key points related to functional safety in
AUTOSAR and explains how the functional safety mechanisms and measures can be
used.
Note: This document supersedes the AUTOSAR document "Technical Safety Concept
Status Report", ID: 233.
The features described in this chapter are part of the OS and the RTE functionality,
which are required to enable groups of SW-Cs to run in separate memory partitions, in
order to provide freedom from interference between software components.
According to ISO 262624 , the following memory-related effects of faults can be consid-
ered as a cause for interference between software components:
• Corruption of content.
• Read or write access to memory allocated to another software element.
• Inconsistent data (e.g. due to update during data fetch).
• Stack overflow or underflow.
The functional safety mechanism Memory Partitioning provides protection by means
of restricting access to memory and memory-mapped hardware. Memory partition-
ing means that OS-Applications reside in different memory areas (partitions) that are
protected from each other. In particular, code executing in one partition cannot modify
memory of a different partition. Moreover, memory partitioning enables to protect read-
only memory segments (e.g. code execution), as well as to protect memory-mapped
hardware.
The memory partitioning and user/supervisor-modes related features address the fol-
lowing goal: Supporting freedom from interference between software components by
means of memory partitioning (e.g. memory-related faults in SW-Cs do not propagate
to other software modules and SW-Cs executed in user-mode have restricted access
to CPU instructions like e.g. reconfiguration).
2.1.2 Description
Memory Partitioning is an extension of the RTE and the OS, which is described in
the AUTOSAR Specification as "One Partition will be implemented using one OS-
Application"5 and "SW-Cs grouped in separate user-mode memory partitions"6 .
During the course of this chapter, this extension will be described as the relationship
of Runnables, Tasks, Software Components and OS-Applications in the context of the
AUTOSAR Methodology.
4
[ISO 26262-6, Annex D] D.2.3 Memory
5
CP_TPS_ECUConfiguration[2], V3.5.0, R4.1 Rev 3, Page 154, ECUC_EcuC_00005
6
Requirements on AUTOSAR Features, V1.2.1, R4.1 Rev 2, Chapter 4.11 Safety
In the AUTOSAR Architecture, Application Software is located above the RTE and
consists of interconnected AUTOSAR Software Components, which atomically encap-
sulate parts of the Application Software functionality.
2.1.2.2 OS Applications
Figure 2.4 presents an interpretation of the relations from Figure 2.3. Runnables from
AUTOSAR Software Components are assigned to OS-Tasks according to this diagram.
According to Figure 2.4 and Figure 2.3, an OS-Application can contain multiple AU-
TOSAR Software Components and associated Runnables. Runnables are only al-
7
CP_SWS_OS[4], V5.3.0 R4.1 Rev 3, Chapter 7.6.1
lowed to directly access variables and to perform function calls within their respective
Software Component.
Internal Function Calls and Variables of a Software Component are not publically
known by other Software Components, as their definitions are not presented by the
header files of the external interface.
Therefore, a direct communication via variables and the execution of Code of other
Software Components is not intended.
In Figure 2.5, this is illustrated by the example of code-sharing, which is only allowed
within the Software Component and not between Software Components of one OS-
Application. Communication with other Software Components shall be performed via
the RTE. Runnable 4 may not execute functions belonging to SW-C 2.2.
8
[ISO 26262-6 7.4.8] Coexistence
Application Software can consist of Software Components with different ASIL ratings.
However, Software Components with different ASIL ratings should not be assigned to
the same OS-Application. Memory Partitioning does not provide freedom from interfer-
ence between Software Components which are assigned to the same OS-Application.
The Operating System only prevents other OS-Applications from performing improper
accesses. A faulty Software Component would not be prevented from modifying mem-
ory areas of other Software Components within the same OS-Application.
Note: Please consult the subsequent section for details on Task-level partitioning.
Memory Partitioning cannot be used to separate Runnables within the same SW-C.
If it is necessary to have a Software Component comprise Runnables with different
ASIL-ratings and an independent execution with freedom from interference is required
for those Runnables, then memory partitioning at OS-Application level is not sufficient,
memory partitioning has to be performed at Task-level. This approach is shown in
Figure 2.7.
A broad variety of technical safety concepts on the system- and software level can be
implemented using the mechanism Memory Partitioning.
Figure 2.8 shows a possible implementation whereas all Basic Software Modules
are executed in one trusted/supervisor-mode9 memory partition (highlighted in red in
Figure 2.8). Some SW-Cs are logically grouped and put in separate non- trusted/user-
mode memory partitions (highlighted in green). Selected SW-Cs belong to the same
trusted/supervisor-mode memory partition as the Basic Software Modules (see fourth
SW-C in Figure 2.8 highlighted in red). There may be several non-trusted/user-mode
10
partitions, each containing one or more SW-Cs.
9
Supervisor Mode, Privileged Mode and Elevated Mode are synonyms for the elevated CPU mode.
Trusted Mode is a mode of the Software, which is executed under the elevated CPU Mode.
10
User Mode and Non-Privileged Mode are synonyms for a non-elevated CPU mode. Non-Trusted
Mode is a mode of the Software, which is executed under the non-elevated CPU Mode.
Note: This table may be incomplete with respect to the features of the specific hardware
devices in use.
Address Space Rationale Read Write Execute
Flash Memory Read, Execute and Write accesses do not modify flash O O O
memory contents. Flash memory must be erased and
enabled for writing by a different mechanism first.
Note: The following implications arise from the Security
point of view: Reading and execution of foreign code
may be used to obtain information which is otherwise
not intended for the software.
RAM Write access to RAM may produce memory O X O
corruptions, thereby affecting the behavior of the
software.
Peripheral Side effects are possible even when reading from X X X
peripheral address space. E.g.: Acknowledgement of
an Interrupt is performed via a read access to the
Interrupt Controller, Read access to peripherals may
cause I/O errors.
Legend:
X - Protection is needed
O - Protection is optional
Note: Side effects from performance point of view may arise due to Bus Contention,
arbitration at interfaces, etc.
Use Case 1: Software Components in the same Partition.
• Software Components in the same partition have access to each other’s RAM
regions, and therefore can corrupt each other’s memory contents.
• Software components do not have access to peripheral devices by definition, as
they shall be not aware of the underlying microcontroller architecture. An unsafe
system can be created when a software component is given direct access to
peripheral devices.
Use Case 2: Software Components in different Partitions.
• Software Components in different partitions do not have access to each other’s
RAM regions, and therefore cannot corrupt each other’s memory contents.
• Software components do not have access to peripheral devices by definition, as
they shall be not aware of the underlying microcontroller architecture. A poten-
tially unsafe system can be created when a software component is given direct
access to peripheral devices.
Use Case 3: MCAL Drivers
• MCAL Drivers are a collection of functions, such as Read/Write/Initialize. They
must be executed by another entity, such as the BSW or a CDD. Please see
Figure 2.8 for details.
• MCAL Drivers need a Read/Write access to the peripheral space of the respective
peripheral hardware module. Depending on the hardware architecture, supervi-
sor mode of the processor may be additionally required.
2.1.4 Limitations
12
Specification of Operating System, V5.3.0 R4.1 Rev 3
13
CP_EXP_ApplicationLevelErrorHandling[5], R4.2 Rev 1, Chapter 8, Chapter 10
14
[ISO 26262-9 Clause 6]
tween Software Components of the same ASIL rating is not required by the stan-
dard.
OS-Applications which consist of a large number of Software Components are
allowed. In case a single Software Component causes a violation which results
in shutdown or restart of the entire memory partition, all other correctly working
SW-Cs of this memory partition are affected as well.
2. Memory Partitioning is not applicable for trusted OS-Applications.
The execution of trusted/supervisor-mode memory partitions is not controlled by
means of the Operating System and some MMU/MPU hardware implementa-
tions.
3. Memory Partitioning not supported on task-level.
The implementation of task-level partitioning is not mandatory for AUTOSAR OS
implementations. Freedom from Interference within the OS-Application may be
therefore not supported.
4. Performance penalty due to Memory Partitioning.
Depending on the architecture of the Application Software and the implemen-
tation of microcontroller hardware and the OS, there is a performance penalty
associated with the use of Memory Partitioning. This penalty increases with the
number of context switches which are performed per time unit.
5. No Basic Software Partitioning.
The current specification of the Basic Software does not specify memory parti-
tioning for Basic Software Components with different ASIL ratings from different
suppliers.
The following references to the ISO26262 standard are related to the aspects of free-
dom from interference for software components with different ASIL ratings.
According to ISO 2626215 , the following Timing- and Execution-related faults can be
considered as a cause for interference between software components:
• Blocking of execution
• Deadlocks
• Livelocks
• Incorrect allocation of execution time
• Incorrect synchronization between software elements
Timing protection and monitoring can be described as monitoring of the following prop-
erties: Monitoring that tasks are dispatched at the specified time, meet their execution
time budgets, and do not monopolize OS resources.
To guarantee that safety-related functions will respect their timing constraints, tasks
monopolizing the CPU (such as heavy CPU load, many interrupt requests) shall be
detected and handled.
15
[ISO 26262-6, Annex D] D.2.2 Timing and execution
2.2.2 Description
16
See CP_EXP_LayeredSoftwareArchitecture[3], V3.4.0, R4.1 Rev 3, Page 42, Page 82.
given limits. This means that Watchdog Manager checks if a Supervised Entity is run
not too frequently or not too rarely.
Alive Supervision is performed using a single Checkpoint without transitions. The su-
pervised Entity must cyclically call the Checkpoint to signal its timely operation. The
Watchdog Manager is executed periodically by the Operating System to verify the
Checkpoint parameters.
A Supervised Entity can also be monitored by multiple instances of Alive Supervision,
therefore containing an independent checkpoint per Alive Supervision. Please see
Figure 2.9.
If the second Checkpoint is never reached, then Deadline Supervision will fail to de-
tect this issue. This issue appears because the timing checks are performed by the
Watchdog Manager after the second Checkpoint is called.
17
Specification of Operating System, V5.3.0 R4.1 Rev 3, Chapter 7.7.2
For safe and accurate timing protection it is necessary for the operating system to con-
trol these factors at runtime to ensure that Tasks/Interrupts can meet their respective
deadlines. The AUTOSAR OS provides the following timing protection mechanisms:
1. Execution Time Protection. An upper bound for execution time of Tasks or Cat218
Interrupts, the so called Execution Budget, is monitored via the OS to prevent
timing errors.
2. Locking Time Protection. An upper bound for blocking of resources, locking and
suspending of interrupts, the so called Lock Budget, is monitored by the OS.
3. Inter-Arrival Time Protection. A lower bound between tasks being activated or Cat
2 Interrupts arriving, a so called Time Frame, is monitored via the OS to prevent
timing errors.
Note: Execution time enforcement requires hardware support, e.g. a timing enforce-
ment interrupt. If an interrupt is used to implement the time enforcement, the priority of
this interrupt shall be high enough to "interrupt" the supervised tasks or interrupts.
The Watchdog Manager provides three mechanisms for Temporal and Logical Program
Flow Monitoring: Deadline Supervision, Alive Supervision and Logical Supervision.
The supervision mechanisms are configured statically. For the monitoring of a Super-
vised Entity, more than one supervision mechanism can be employed.
Based on the results from each of enabled mechanisms, the status of the Supervised
Entity (called Local Status) is computed. When the status of each Supervised Entity
is determined, then based on each Local Supervision Status, the status of the whole
MCU is determined (called Global Supervision Status).
Depending on the Local Supervision Status of each Supervised Entity and on the
Global Supervision Status, the Watchdog Manager initiates a number of mechanisms
to recover from supervision failures. These range from local error recovery within the
Supervised Entity to a global reset of the ECU.
The following error recovery mechanisms can be employed by the Watchdog Manager:
1. Error Handling in the Supervised Entity
In case the Supervised Entity is an SW-C or a CDD, then the Watchdog Manager
may inform the Supervised Entity about supervision failures via the RTE Mode
mechanism. The Supervised Entity may then take its actions to recover from that
failure.
18
Category 2 Interrupts are managed by the Operating System. Category 1 Interrupts are executed
outside of the Operating System and therefore cannot be monitored.
The Watchdog Manager may register an entry with the Diagnostic Event Man-
ager (DEM) when it detects a supervision failure. A Supervised Entity may take
recovery actions based on that error entry.
2. Partition Shutdown
If the Watchdog Manager module detects a supervision failure in a Supervised
Entity which is located in a non-trusted partition, the Watchdog Manager module
may request a partition shutdown by calling the BswM.
3. Reset by Hardware Watchdog
The Watchdog Manager indicates to the Watchdog Interface when Watchdog
Interface shall no longer trigger the hardware watchdog. After the timeout of the
hardware watchdog, the hardware watchdog resets the ECU or the MCU. This
leads to a re-initialization of the ECU and/or MCU hardware and the complete
re-initialization of software.
4. Immediate MCU Reset
In case an immediate, global reaction to the supervision failure is necessary, the
Watchdog Manager may directly cause an MCU reset. This will lead to a re-
initialization of the MCU hardware and the complete software. Usually, a MCU
reset will not re-initialize the rest of the ECU hardware.
Note: The AUTOSAR Document "Explanation of Error Handling on Application Level"19
provides additional information on error handling. Within the document it is explained
how error handling can be performed and where the required data (e.g. substitute val-
ues) can be obtained from. Furthermore the document provides a detailed explanation
(user’s manual) on how OS-Application/Partition termination and restart in AUTOSAR
is performed.
2.2.4 Limitations
19
CP_EXP_ApplicationLevelErrorHandling[5], R4.2 Rev 1, Chapter 8, Chapter 10
3. The nesting of Deadline Supervision (i.e. start 1, start 2, end 2, end 1) is not
supported.
4. The Alive Supervision function with more than one checkpoint per Supervised
Entity is not consistently specified within the Specification of Watchdog Manager
document. For now it is recommended to support only one alive supervision
checkpoint per Supervision Entity.
5. In order to shutdown or restart (as error reaction) a partition containing Super-
vised Entities, the integrator code (OS Application’s restart task) must deactivate
(or deactivate + activate) all Supervised Entities of the involved partition, by call-
ing available functions of Watchdog Manager. This is a bit complex, in future
releases of the Specification of Watchdog Manager document it is considered to
add a new function of Watchdog Manager for this.
6. Libraries cannot call BSWs, so libraries cannot be supervised by Watchdog Man-
ager. Deadline Supervision could be used however by placing checkpoints before
and after a library call in the module’s code to supervise libraries.
7. It is not standardized how BSW modules are identified with Supervised Entity
IDs.
The following references to the ISO26262 standard are related to the aspects of free-
dom from interference for software components with different ASIL ratings. Concepts
related to timing supervision are covered.
ID ISO26262 Reference
03 Part 6: [D.2.1]
08 Part 6: [D.2.2]
09 Part 6: [7.4.12] NOTE 2, Monitoring of program execution by an external element
According to ISO 2626220 , the following Timing- and Execution-related faults can be
considered as a cause for interference between software components:
• Blocking of execution
• Deadlocks
• Livelocks
• Incorrect allocation of execution time
• Incorrect synchronization between software elements
Logical and temporal monitoring of program sequences is used in the automotive in-
dustry and mentioned e.g. in ISO 26262 as a measure to detect failures of the pro-
cessing units (i.e. CPU, microcontroller) and as measure for the detection of failures of
the HW clock.
Faults in execution of program sequences (i.e. invalid execution of program sequences)
can lead to data corruption, process crashes, or fail-silence violations.
Logical monitoring of program sequences is required/recommended/proposed by ISO
26262, IEC 61508, MISRA.
2.3.2 Description
no fixed relationship between Supervised Entities and the architectural building blocks
in AUTOSAR. Typically a Supervised Entity may represent one SW-Cs or a Runnable
within an SW-C, a BSW module or CDD depending on the choice of the developer.
Places relevant for logical supervision in a Supervised Entity are defined as Check-
points. The code of Supervised Entities is interlaced with function calls of the Watchdog
Manager. Those calls are used to report to the Watchdog Manager that a Checkpoint
is reached.
Each Supervised Entity has one or more Checkpoints. The Checkpoints and Transi-
tions between the Checkpoints of a Supervised Entity form a Graph.
A Graph may have one or more21 initial Checkpoints and one or more final Check-
points. Any sequence of starting with any initial checkpoint and finishing with any final
checkpoint is correct, assuming that the checkpoints belong to the same Graph.
A graph within a Supervised Entity is called an Internal Graph. Checkpoints from differ-
ent Supervised Entities can be connected by External Transitions, forming an External
Graph.
Figure 2.11 shows a Graph representation of a While-Loop, which consists of Check-
points and Transitions.
21
Internal graphs can have only one initial Checkpoint. External graphs can have multiple initial Check-
points.
At runtime, the Watchdog Manager verifies if the supervised Entities are executed ac-
cording to the configured Graphs. This is called Logical Supervision.
Also, the Watchdog Manager can verify the timing of Checkpoints and Transitions within
a Graph.
The timing of Transitions between Checkpoints can be verified via Deadline Supervi-
sion, whereas Logical Monitoring verifies the correct order of the Checkpoints. The
details of Timing Monitoring mechanisms are described in Chapter 2.2.
During design phase the valid program sequences are identified and modeled. During
runtime the Watchdog Manager uses this model to supervise or monitor the proper
execution of program sequences.
The Watchdog Manager provides three mechanisms for Temporal and Logical Program
Flow Monitoring: Deadline Supervision, Alive Supervision and Logical Supervision.
The supervision mechanisms are configured statically. For the monitoring of a Super-
vised Entity, more than one supervision mechanism can be employed.
Based on the results from each of enabled mechanisms, the status of the Supervised
Entity (called Local Status) is computed. When the status of each Supervised Entity
is determined, then based on each Local Supervision Status, the status of the whole
MCU is determined (called Global Supervision Status).
Depending on the Local Supervision Status of each Supervised Entity and on the
Global Supervision Status, the Watchdog Manager initiates a number of mechanisms
to recover from supervision failures. These range from local error recovery within the
Supervised Entity to a global reset of the ECU.
The following error recovery mechanisms can be employed:
1. Error Handling in the Supervised Entity:
In case the Supervised Entity is an SW-C or a CDD, then the Watchdog Manager
may inform the Supervised Entity about supervision failures via the RTE Mode
mechanism. The Supervised Entity may then take its actions to recover from that
failure.
The Watchdog Manager may register an entry with the Diagnostic Event Man-
ager (DEM) when it detects a supervision failure. A Supervised Entity may take
recovery actions based on that error entry.
2. Partition Shutdown
If the Watchdog Manager module detects a supervision failure in a Supervised
Entity which is located in a non-trusted partition, the Watchdog Manager module
may request a partition shutdown by calling the BswM.
3. Reset by Hardware Watchdog
The Watchdog Manager indicates to the Watchdog Interface when Watchdog
Interface shall no longer trigger the hardware watchdog. After the timeout of the
hardware watchdog, the hardware watchdog resets the ECU or the MCU. This
leads to a re-initialization of the ECU and/or MCU hardware and the complete
re-initialization of software.
4. Immediate MCU Reset
In case an immediate, global reaction to the supervision failure is necessary,
the Watchdog Manager may directly cause an MCU reset. This will lead to a
re-initialization of the MCU hardware and the complete software.
Note: The AUTOSAR Document "Explanation of Error Handling on Application Level"22
provides additional information on error handling. Within the document it is explained
how error handling can be performed and where the required data (e.g. substitute val-
ues) can be obtained from. Furthermore the document provides a detailed explanation
22
CP_EXP_ApplicationLevelErrorHandling[5], R4.2 Rev 1, Chapter 8, Chapter 10
2.3.4 Limitations
1. For Logical Supervision, Watchdog manager does not support any overlapping
graphs - a checkpoint shall belong to maximum one Graph. This is required to be
able to allocate a received Checkpoint notification to a Graph.
2. Watchdog Manager does not support Logical Supervision of concurrently exe-
cuted Supervised Entities, because it follows only one instance of a Graph at a
time.
3. In order to shutdown or restart (as error reaction) a partition containing Super-
vised Entities, the integrator code (OS Application’s restart task) must deactivate
(or deactivate + activate) all Supervised Entities of the involved partition, by call-
ing available functions of Watchdog Manager.
The following references to the ISO26262 standard are related to the aspects of free-
dom from interference for software components with different ASIL ratings. Concepts
related to logical supervision are covered.
ID ISO26262 Reference
03 Part 6: [D.2.1]
08 Part 6: [D.2.2]
09 Part 6: [7.4.12] NOTE 2, Monitoring of program execution by an external element and Temporal monitoring of
program execution
Therefore, such data shall be transmitted using mechanisms to protect it against the
effects of faults within the communication link.
23
[ISO 26262-6, Annex D] D.2.4 Exchange of Information
The concept of End-2-End protection assumes that safety-related data exchange shall
be protected at runtime against the effects of faults within the communication link (see
Figure 2.12). Examples for such faults are random HW faults (e.g. corrupt registers
of a CAN transceiver), interference (e.g. due to EMC), systematic faults within the
software implementing the VFB communication (e.g. RTE, IOC, COM and network
stacks) inside the ECU and outside, such as on Gateways.
The following faults related to message exchange via communication network have
been considered in the End-2-End Library.
Fault Model Description
Repetition of A type of communication fault, were information is received more than once.
information
Loss of information A type of communication fault, were information or parts of information are removed from a
stream of transmitted information.
Delay of information A type of communication fault, were information is received later than expected.
Insertion of information A type of communication fault, were additional information is inserted into a stream of transmitted
information.
Masquerading A type of communication fault, were non-authentic information is accepted as authentic
information by a receiver.
Incorrect addressing A type of communication fault, were information is accepted from an incorrect sender or by an
incorrect receiver.
Incorrect sequence of A type of communication fault, which modifies the sequence of the information in a stream of
information transmitted information.
Corruption of A type of communication fault, which changes information.
information
Asymmetric information A type of communication fault, were receivers do receive different information from the same
sent from a sender to sender.
multiple receivers
Information from a A type of communication fault, were some receivers do not receive the information
sender received by only
a subset of the
receivers
Blocking access to a A type of communication fault, were the access to a communication channel is blocked.
communication channel
Table 2.7: Fault Models of a Communication Network
CP_SWS_E2ELibrary[7], V3.2.1, R4.1 Rev 3, Chapter 4.3.3
2.4.2 Description
From the perspective of Software Components, data transmission via the RTE behaves
like a simple point-to-point connection. However, the implementation of this abstraction
requires a highly complex infrastructure made up of software layers, communication
stacks, drivers and the underlying hardware. Along with the complexity, the number of
potential sources for failures also increases.
The use of the End-2-End protection mechanism assumes that the integrity of safety-
relevant data has to be maintained during communication, protecting the data against
the effects of faults within the communication link.
The most important aspects of the End-2-End protection are the standardization of the
protection capabilities and the flexible applicability of the mechanism. Mechanisms for
safe data communication within and between ECUs though the concept of End-2-End
protection will be described in this chapter.
The architecture of the End-2-End protection is implemented as follows: Data Ele-
ments consisting of Application Data are extended on the sender side with additional
control information, the End-2-End header. The control information usually contains a
Checksum, a Counter and other options. The extended data element is provided to the
RTE for transmission, as shown in Figure 2.13. It shows the principle of E2E, but not all
details required for implementation. Especially the usage of the RTE Data Transformer
to encode/decode complex data elements is omitted for simplicity.
Data Elements are verified at the receiver side by processing the contents of the End-2-
End header against the Application Data. After the received data element is processed
and accepted as correct, the control information is removed and Application Data is
provided to the target Software Component.
The error handling is performed at the receiver.
24
CP_SWS_E2ELibrary[7], V3.2.1, R4.1 Rev 3, SWS_E2E_00221
Figure 2.14 illustrates how the CRC calculation is performed in the End-2-End Profile 1.
The value of Data ID is calculated into the CRC value, so both communication partners
must use the same Data ID to correctly verify the CRC Checksum of a message.
Although the length of the Data ID is 16 bits, leading to a large number of individual
Data IDs, the length of the CRC checksum is only 8 bits. This means that different Data
IDs will produce the same CRC checksum, thus limiting the number of independent
Data IDs.
If a message is routed to the wrong destination, e.g. due to Bit-flips in a gateway, and
the Data IDs produce the same CRC checksum, then the receiver would accept the
misdirected message, assuming that the current counter value and the length of the
message are both correct. The extent of the underlying protection against Addressing
Faults is diminished. This fault model is called Masquerading.
It is possible to restrict the Data ID values so there is no overlap in the CRC Check-
sums. This however limits the number of independent Data IDs to 255.
The End-2-End Profile 2 takes a different approach in the use of the Data ID protection
mechanisms. Each sender-receiver port pair has a list of Data IDs. The current value
of the sequence counter determines which Data ID is used.
An appropriate selection of Data IDs is required to increase the number of messages
for which detection of masquerading is possible. However, there will be overlaps of the
8-Bit Data ID and Counter values, limiting the number of independent Data IDs and
Counter values to 256.
If a single erroneously received message does not violate the safety goal of the system,
then the End-2-End Profile 2 allows for protection against masquerading for a greater
number of messages.
Mechanism Description Fault Model
Sequence Number A 4Bit Counter is incremented with every Send-Request. This Value is Unintended message
(Counter) explicitly sent. repetition, message
loss, insertion of
messages,
re-sequencing
5
4
Message Key used for 8 bit (not explicitly sent) Insertion of messages,
CRC calculation (Data masquerading
The Data ID used for CRC calculation is an element of a pre-defined
ID)
list and depends on the current value of the Counter. The list of Data
IDs is unique for each Data Element and only known to the sender and
the receiver.
Safety Code (CRC) A CRC Checksum (8-Bit) calculation is performed over all data Message corruption,
elements, the Counter and the Data ID. This value is explicitly sent. insertion of messages
(masquerading)
Timeout (detection and Timeout detection must be implemented by the SW-C. Message loss,
handling implemented message delay
by SW-C)
AUTOSAR supports PDUs up to 4kB in size, either through the TCP/IP stack or through
TP services of FlexRay TP, CAN TP, etc. The End-2-End Profiles 1 and 2 support an
ASIL-D compliant transmission of up to 30 or 42 byte PDUs, due to the short 8-Bit CRC
checksum.
The AUTOSAR Release 4.2.1 introduces a new End-2-End Profile. The End-2-End
Profile 4 is specifically designed for ASIL-D compliant transmission of long data. This
is supported by the use of a special 32-Bit CRC polynomial. This polynomial is superior
to the widely used IEEE 802.3 CRC, as it provides a higher Hamming Distance for long
data.
Mechanism Description Fault Model
Counter A 16 Bit Counter is incremented with every Send-Request. This Value Unintended message
is explicitly sent. repetition, message
loss, insertion of
messages,
re-sequencing
CRC The 32 Bit CRC is calculated over the entire E2E header (excluding Message corruption,
the CRC bytes) and over the user data. This Value is explicitly sent. insertion of messages
(masquerading)
Note: This CRC polynomial is different from the CRC-polynomials
used by FlexRay, CAN, LIN and TCP/IP.
Data ID The 32 Bit Data ID shall be unique for a specific data element within Insertion of messages,
the network of ECUs. masquerading
This Value is explicitly sent.
Timeout (detection and The receiver reads the currently available data, i.e. checks if new data Message loss,
handling implemented is available. message delay
by SW-C)
Then, by means of the counter, the receiver can detect loss of
communication and timeouts.
Table 2.10: Mechanisms in End-2-End Profile 4
The End-2-End Profile 4 header provides the following control fields, which are trans-
mitted together with the protected data.
Contrary to E2E Profiles 1 and 2, there is an explicit transmission of the data length,
as data packets do not have a standard size. The 16 bits Length field is introduced
to support variable-size data, which can have a different length in each transmission
cycle. Also there is an explicit transmission of the Data ID.
Data Elements are verified at the receiver side by processing the contents of the End-2-
End header against the Application Data using the End-2-End Profile’s check-function.
It determines whether the received data of this cycle is correct and provides additional
information in case of detected faults.
The AUTOSAR Release 4.2.1 introduces a State Machine, which helps to determine
whether the received Application Data is acceptable with a greater level of detail. A
new level of abstraction is introduced, so applications receive an overall status of the
communication, instead of dealing with the status of every single message.
The new state machine supports configurable settings for the number of lost or re-
peated packets, recoverable and non-recoverable communication faults, as well as
initialization of communication. Figure 2.15 illustrates the design and features of the
state machine.
To enable the proper usage of the End-2-End Library, different solutions are possible.
They may depend on the integrity of RTE, COM or other basic software modules as
well as the usage of other SW/HW mechanisms (e.g. memory partitioning).
The End-2-End Library can be used to protect safety-related data elements exchanged
between SW-Cs by means of End-2-End Protection Wrapper.
Furthermore, the End-2-End Library can be used to protect safety-related I-PDUs by
means of COM Callouts.
It is also possible to have mixed scenarios, where some data elements are protected
at the SW-C level (e.g. with End-2-End protection Wrapper) and some with COM End-
2-End callouts.
Introduced in AUTOSAR Release 4.2.1, the RTE Data Transformer can also be used
to protect data exchange of complex data elements between ECUs at the RTE level.
The End-2-End Protection Library can be used to protect the data communication be-
tween SW-Cs at the RTE level. To accomplish this, the End-2-End Protection Wrap-
per functions as a wrapper over the Rte_Write and Rte_Read functions, which are
offered to SW-Cs. The End-2-End Protection Wrapper encapsulates the Rte_Read/
Write invocations of the Software Component and protects the data exchange using
the End-2-End Library.
In this approach, every safety-related SW-C has its own additional sub-layer (a .h/.c file
pair) called the End-2-End Protection Wrapper, which is responsible for marshalling of
complex data elements into the layout identical to the corresponding I-PDUs (for inter-
ECU communication), and for correct invocation of End-2-End Library and of RTE.
Please see Figure 2.17.
The usage of the End-2-End Protection Wrapper allows a use of VFB communication
between SW-Cs, without the need of further measures to ensure VFB’s integrity.
The communication between such SW-Cs can be within an ECU (which means on the
same or different cores or within the same or different memory partitions of a micro-
controller) or across ECUs (SW-Cs connected by a VFB also using a network).
The end-to-end protection is a systematic solution for protecting SW-C communica-
tion, regardless of the communication resources used (e.g. COM and network, OS/
IOC or internal communication within the RTE). Relocation of SW-Cs may only require
selection of other protection parameters, but no changes on SW-C application code.
Also, the use of the End-2-End protection wrapper supports safe communication
between software components despite a potentially unsafe communication software
stack.
Note: The End-2-End Protection Wrapper does not support multiple instantiation of the
SW-Cs. This means, if an SW-C is supposed to use End-2-End Protection Wrapper,
then this SW-C must be single-instantiated. This limitation is based on the fact that
multiple instances of a Software Component would have the same DataID, thus limiting
the capabilities of the underlying protection mechanisms.
In an ECU system where integrity of operation is not provided for COM and RTE, it is
possible to transmit safety-related data through the network.
On the sender ECU, there is a dedicated SW-C called the Transmission Manager,
containing End-2-End Protection Wrapper. The Transmission Manager collects safety-
related data from related SW-Cs, combines them and protects them using the End-
2-End Protection Wrapper. Finally, it provides the combined and protected Data as a
Data Element to the RTE. Please see Figure 2.18.
On the receiver ECU a Transmission Manager does the reverse steps for the reception
of such data.
The Transmission Manager replaces the duties of the RTE and COM, such as merging
of Data Elements into PDUs and ensuring the integrity of data.
Note: The Transmission Manager SW-C module is neither part of End-2-End Library
nor part of AUTOSAR. Also, the integrity of RTE communication between the SW-Cs
and the Transmission Manager shall be protected by other measures.
In this approach, the End-2-End Library is used to protect the data exchange between
COM modules. The End-2-End Library is invoked by COM, through COM End-2-End
callouts, to protect and check the I-PDUs. The callout invokes the End-2-End Library
with parameters appropriate for a given I-PDU. Please see Figure 2.19.
For each I-PDU to be protected and checked there is a separate callout function. Each
callout function "knows" how each I-PDU needs to be protected and checked. This
means that the callout invokes the End-2-End Library functions with settings and state
parameters that are appropriate for the given I-PDU.
This solution works with all communication models, multiplicities offered by RTE for
inter-ECU communication. In contrast to the Transmission Manager, this solution can
only be used in systems where the integrity of operation of COM and RTE is provided.
Introduced in AUTOSAR Release 4.2.1, the RTE Data Transformer can be used to
protect the exchange of complex data elements between ECUs.
The main difference between the previously described mechanisms for End-2-End Li-
brary invocation can be illustrated as follows:
The End-2-End protection wrapper extends the complex data element25 under protec-
tion by adding data elements of the End-2-End header. The additional data elements
can be seen by the SW-C but are ignored. The RTE Protection Wrapper, therefore,
does not support the protection of individual signals, unless they are embedded within
a complex data element.
COM maps the individual signals of a complex data element into PDUs. Using COM
Callouts, the contents of the entire PDU are protected. The maximum PDU size is
however limited by the physical properties of the interconnection bus.
Complex data elements can be prepared for transmission by being specifically ar-
ranged in a Byte-Array by a process called serialization. The serialized data array
can be then protected using the End-2-End Library as a single piece. Furthermore, the
serialized data array size can be dynamic on a transmission cycle basis.
25
A complex data element is an instance of a complex data type. Inside a complex data type, there
are one or more data types (primitive data types), like in a C struct.
As illustrated in Figure 2.20, the RTE Data Transformer accepts complex data (either
a Sender/Receiver data element or a Client/Server operation with its arguments) from
the RTE, performs a configurable chain of data transformations (such as Serialization,
End-2-End Protection, Cryptographic functions, Compression) and provides the result-
ing byte array, which is finally transmitted to the receiver by COM (or RTE during intra-
ECU communication). Data transformation for End-2-End Protection is implemented
by the End-2-End Transformer26 , which internally uses the End-2-End Library.
The complete configuration of the RTE Data Transformer is performed via AUTOSAR
System Template for Inter-ECU communication and Software-Component Template for
Intra-ECU communication. The resulting code is fully generated and executed via the
RTE. The Software Components do not have to be aware of the specific protection
mechanism used, unless detailed knowledge of the detected faults is required. The
RTE Data Transformer can only be used in systems, where the integrity of operation of
RTE is provided.
Note: The serialized data array size is not restricted by the PDU size of the inter-
connection network, as large data arrays can be transmitted using existing transport
protocols.
26
CP_SWS_E2ETransformer[8], V0.9.1, R4.2 Rev 1
Note: The individual data transformations are performed on data arrays and not com-
plex data elements, therefore serialization is the first and respectively last data trans-
formation performed by the RTE Data Transformer.
2.4.4 Limitations
1. The appropriate usage of the End-2-End Library alone is not sufficient to achieve
a safe End-2-End communication. Solely the user is responsible to demonstrate
that the selected profile provides sufficient error detection capabilities for the con-
sidered network (e.g. by evaluation hardware failure rates, bit error rates, number
of nodes in the network, repetition rate of messages and the usage of a gateway).
2. A communication between Software Components over the RTE is more than a
simple Point-to-Point connection. Further fault models have to be considered,
such as RTE errors in Data Conversion, Filtering, missing notifications, wrong
order of parameters in client-server communication and delays in transmission.
Those failure modes also have to be considered during the development of a
safety-relevant system.
Local RTE communication can be protected against some of the faults mentioned
above by other mechanisms, such as an RTE which employs internal partitioning
and other safety mechanisms and measures.
3. The use of the End-2-End protection for all Software Component communications
of an ECU may be prohibitive due to runtime-overheads. Also, the limitations
associated with the uniqueness of DataIDs may prevent this approach on Profile
1 and 2 due to masquerading.
27
CP_EXP_ApplicationLevelErrorHandling[5], R4.2 Rev 1, Chapter 8, Chapter 10
4. The End-2-End Protection does not guarantee data actuality, because the End-
2-End Profiles do not incorporate time stamps in the control data.
The following references to the ISO26262 standard are related to the aspects of free-
dom from interference for software components with different ASIL ratings. Concepts
related to exchange of information are covered.
ID ISO26262 Reference
03 Part 6: [D.2.1]
09 Part 6: [D.2.4]
10 Part 6: [7.4.12] NOTE 2, Detection of data errors
4
012 Interface test ISO 26262-6 Acceptance Test for the AUTOSAR Stack
Table 7, 1k
Table 10, 1b
013 Document ISO26262-8 Fulfilled by AUTOSAR Quality Management
Management
10.4.3-10.4.6
3.2 Traceability
Traceability is a prerequisite for the implementation of safety-relevant systems. AU-
TOSAR provides traceability from the AUTOSAR project objectives to the software
specifications of the AUTOSAR architecture.
1
In the context of this document, functional safety mechanisms are a concrete product part, such as
memory protection. They are considered as specialization of functional safety measures, which also
include process steps, like a review. This definition is in line with the definition given in ISO 26262 for
these terms.
Therefore the example can be adapted or changed in future to include new AUTOSAR
concepts or extend the complexity of the analyzed system.
Timing is an important property of embedded systems. Safe behavior requires that the
systems actions and reactions are performed within the right time.
The right time can be described in terms of a set of timing constraints that have to be
satisfied. However, an AUTOSAR software component cannot ensure proper timing by
itself. It depends on proper support by the AUTOSAR runtime environment and the
basic software. During integration the timing constraints of the software components
need to be ensured.
The timing-related features address the following aspects to enable proper software
component timing within the AUTOSAR framework:
• Provision of synchronized time-bases to provide a common notion of time across
a network of ECUs;
• Provision of means for synchronized execution of runnables within an AUTOSAR
ECU and across a network of AUTOSAR ECUs;
• Support by the AUTOSAR RTE, BSW and Methodology for deterministic timing
of software components;
• Support by the AUTOSAR RTE and BSW to detect and control timing violations
and prevent their propagation.
The synchronization will apply to the clock rate and optionally apply also to the clock
absolute value.
A synchronized time-base allows synchronized action of the processing entities. Syn-
chronized time-bases are often called "global time", as e.g. the so called "FlexRay
global time". We do not use the term "global time" here because a single ECU some-
times has to cope with several synchronized time-bases which may vary in terms of
rate and absolute value.
The synchronized time bases are established by the synchronized time-base manager
BSW module.
In the AUTOSAR ECU Architecture the "Synchronized Time-base Manager" BSW mod-
ule implements an AUTOSAR Service as indicated in Figure 3.1.
The application can access the AUTOSAR Service "Synchronized Time-Base Man-
ager" via service ports with standardized AUTOSAR Interfaces.
Figure 3.1: The Synchronized Time - Base Manager in the ECU architecture
CP_SWS_SynchronizedTimeBaseManager[9], V1.2.1, R4.2 Rev 2, Chapter 7.6.1 Architecture
Different types of customers will use the synchronized time-bases: triggered cus-
tomers, active customers and notification customers. Triggering customers (runnables)
is done via the OS.
The Synchronized Time-base Manager itself does not provide means like network time
protocols or time agreement protocols to synchronize its (local) time bases to time
bases on other nodes. It interacts with the <bus>TSyn modules of the BSW to achieve
such synchronization.
ID Description
RS_BRF_00127_CC01 There are means that customers can use the synchronized time base. The following types
of customers are to be considered: triggered customers, active customers and notification
customers.
Table 3.4: Coverage Criteria - Services for accessing to synchronized time-bases
3.7.1.1.3 Sync AUTOSAR OS with Global Time from providing bus system in a
well-defined way
The feature "Sync AUTOSAR OS with Global Time from existent bus system in a well-
defined way" is considered to be covered if
ID Description
RS_BRF_00278_CC01 There are means to provide the synchronized time base for FlexRay, CAN, Ethernet and
TTCAN clusters
RS_BRF_00278_CC02 Synchronization between the synchronized time-base and the time base used by the OS
for scheduling is provided.
Table 3.6: Coverage Criteria - Sync AUTOSAR OS with Global Time from providing bus
system in a well-defined way
Table 3.7: Coverage Justification - Sync AUTOSAR OS with Global Time from providing
bus system in a well-defined way
Constraints:
• The feature is restricted to RTE timing events only. The events are used to trigger
runnables.
• The synchronization of runnables that are controlled by different AUTOSAR OS
instances (e.g. if they are running on different ECUs or different µCs within one
ECU) is only possible if they are located on ECUs within the same FlexRay, CAN,
Ethernet or TTCAN network cluster.
The feature "Services for synchronization of SW-Cs" is considered to be covered if
ID Description
RS_BRF_00126_CC01 • There are technical means to trigger runnables in a synchronized way, i.e. with minimum
jitter and (in case of serialized processing) fixed execution order. The following cases
have to be distinguished here:
– The runnables which are triggered by the synchronized timing events are mapped to
the same operating system task.
– The runnables which are triggered by the synchronized timing events are mapped to
different operating system tasks within one OS application.
– The runnables which are triggered by the synchronized timing events are mapped to
different operating system tasks in different OS applications on the same
microcontroller core.
– The runnables which are triggered by the synchronized timing events are mapped to
different operating system tasks in different OS applications on different cores of the
same microcontroller.
– The runnables which are triggered by the synchronized timing events are mapped to
different operating system tasks in different OS applications on different
microcontrollers within one ECU.
The runnables which are triggered by the synchronized timing events are mapped to
different operating system tasks in different OS applications on different microcontrollers
within different ECUs.
4
RS_BRF_00126_CC02 The AUTOSAR methodology supports the specification of synchronization constraints for
RTE timing events.
virtual integration on VFB level, development of SW-Cs, and finally the integration of
SW-Cs into ECUs and of ECUs into a system of ECUs.
Furthermore, the runtime environment must provide suitable mechanisms to enforce
deterministic timing.
The following Figure illustrates a specification of VFB timing.
ID Description
RS_BRF_00122_CC01 • It is possible to specify the following timing constraints:
– a timing relation (min, max, nominal) between RTE events with a lower and upper
bounds
– the time relation between a physical sensor acquisition (or a physical actuator change)
and the availability of the corresponding data element on the port of a sensor SW-C (or
actuator SW-C)
– constraints on the execution time (min,max) of a runnable
– constraints on the triggering rate for a runnable
– the end-to-end timing related to external communication
– the end-to-end timing related to IO accesses
RS_BRF_00122_CC02 • The scheduling strategies allow to enforce these timing constraints by providing the
following mechanisms:
– specification of non-preemptive execution of a code segment
– static time-based scheduling for all tasks or for a subset of the tasks
– the possibility to replace ISRs with time-based polling routines
– fixed-priority based scheduling
– the possibility of preemption of lower-priority tasks by higher-priority tasks
4
4
– The AUTOSAR timing
extensions allow to
specify timing events
related to bus
communication and
timing constraints for
these.
– The AUTOSAR timing
extensions allow to
specify input/output
latency constraints.
RS_BRF_00122_CC02 CP_SRS_OS_008 SRS_Os_00097 • The OS and the RTE
provide the necessary
CP_SWS_OS_034 SWS_Os_00001
scheduling mechanisms
CP_SRS_OS_008 SRS_Os_00098 to enforce timing as
follows:
CP_SWS_OS_034 SWS_Os_00002, SWS_
Os_00007 – Non-preemptive
CP_SRS_OS_008
scheduling is supported
SRS_Os_00097
CP_SWS_OS_034 by OSEK OS.
SWS_Os_00001
– The Operating System
provides statically
configurable schedule
tables based on time
tables.
c.-e. These features are
available with OSEK OS.
Depending on the scalability class, the AUTOSAR OS can provide protection mecha-
nisms against timing violation. As the OS is only aware of tasks and not of runnables,
the OS provides protection mechanisms on task level with the fault containment region
being the OS application.
Timing protection of SW-Cs at runtime requires monitoring of runnables and preventing
the propagation of timing faults from one SW-C to another. If SW-Cs require protection
from each other, then their runnables have to be placed into different OS applications
which implies that they are placed into different task bodies.
Note: Please see the subsubsection 2.2.2.3 "Timing Protection of the Operating Sys-
tem".
This feature is considered fulfilled as the functionality can be realized within the soft-
ware component. There is no need for specific mechanisms in AUTOSAR.
The E-Gas Monitoring Concept is a safety concept applicable e.g. for diesel and gaso-
line engine management. It is standardized by the AKEGAS working group and not
part of the AUTOSAR standard.
The possible realizations of the e-Gas monitoring concept in the context of AUTOSAR
software architecture have been investigated. The features of this section ensure that a
design approach as shown in the following figure can be used with AUTOSAR Release
4.0.
In the design approach shown below, the monitoring related software is located in a
Complex Driver (CDD). A CDD allows a direct access to the related inputs and outputs.
ID Description
RS_BRF_00243_CC01 the loss and corruption of data is detected if it happens on the way from the emitter node to
the BSW driver of the receiver node
RS_BRF_00243_CC02 the loss and corruption of data is detected if it happens on the way from the Bus Specific
interface to the Complex Driver
Table 3.16: Coverage Criteria - Communication protections against corruption and loss
of data
4
RS_BRF_00243_CC02 CP_SRS_Libraries_314 SRS_LIBS_08535, the detection of loss and
E2E0026, E2E0030 corruption of data between
CP_SWS_E2ELibrary_428
the Bus Specific Interface
and the Complex Driver is
ensured by the access of
the Complex Driver to the
frame payload dedicated to
Safety and the application
dependent end-to-end
protection.
ID Description
RS_BRF_00248_CC01 The Monitoring SW placed in the Complex Drivers SW can perform test of the related A/
D-Converter without disturbing a data acquisition related to normal operation.
RS_BRF_00248_CC02 The Monitoring SW placed in the Complex Drivers can directly perform tests of the
safety-related actuators (throttle, injectors) of the shut-off path.
Table 3.20: Coverage Criteria - Testing and monitoring of I/O data and I/O HW
Table 3.21: Coverage Justification - Testing and monitoring of I/O data and I/O HW
4 Hardware Diagnostics
Modern microcontrollers for safety-relevant applications are highly complex devices.
To ensure that the desired level of integrity is achieved by the microcontroller as part
of a safety-relevant system, integration and use of functional safety mechanisms and
measures in hardware and software is required.
Microcontrollers must support the premise of the safety-relevant system, that the pro-
vided functionality can be trusted. Execution of Hardware Diagnostic mechanisms can
support this premise. This chapter provides an overview of how hardware diagnostics
are supported using AUTOSAR.
According to ISO 262621 , detection of failures in the following parts of the processing
units are typically considered for the derivation of diagnostic coverage. The following
table provides a preliminary mapping between ISO26262 and Core Test requirements
[10] [11].
ID Processing unit parts Core Test SRS Requirements
001 ALU Data Path Core ALU Test
002 Registers (general purpose registers bank, Core Register Test
DMA transfer registers etc.), internal RAM
003 Address calculation (Load/Store Unit, DMA Core Address Generator
addressing logic, memory and bus interfaces)
Core Memory Interfaces
Memory Management/Protection Unit (MMU/MPU)
Cache Controller
004 Interrupt Handling Core Interrupt and Exception Detection
005 Control Logic (Sequencer, coding and -
execution logic including flag registers and
stack control)
006 Configuration Registers -
007 Other sub-elements not belonging to previous -
classes
Table 4.1: Mapping between Processing Unit parts and Core Test requirements
1
[ISO 26262-5, Annex D] Table D.1 Volatile Memory
4.1.2 Description
The Core Test Driver is an AUTOSAR Basic Software Module which accesses the
microcontroller core directly without intermediate software layers. It is located in the
Abstraction Layer (MCAL).
The Core Test Driver provides several tests to verify dedicated core functionality like
e.g. general purpose registers or Arithmetical and Logical Unit (ALU). Furthermore, the
Core Test Driver provides services for configuring, starting, polling, terminating and
notifying applications about Core Test results. It also provides services for returning
test results in a predefined way.
The Core Test Driver can be used during ECU power-up and during application runtime.
However it is assumed that each hardware functional block of the core under test can
be accessed by the Core Test Driver exclusively.
If the execution of the Core Test Driver is to be embedded into a system safety archi-
tecture concept, then it is up to the user of the Core Test Driver to choose a suitable
test combination and scheduled execution order to fulfill the safety requirements of the
system.
Core Test reports errors in dedicated memory and bus interfaces (e.g. Tightly Coupled
Memories, caches, systems bus) and dedicated supporting functionality (e.g. interrupt
controller) to the diagnostic event manager (DEM) as production errors.
Errors inside the CPU (e.g. ALU, Prefetch queue, registers) cannot be reliably reported
to DEM, as these faults affect the correct operation of the Core itself.
4.1.4 Limitations
MCAL drivers intentionally miss the ability of accessing test results being exe-
cuted on other cores. Currently, there is no test managing entity in AUTOSAR
upper layers to handle test result processing.
4. Core Test cannot report detected faults reliably.
Faults within the CPU itself (e.g. ALU, MAC, Registers) cannot be reliably re-
ported to DEM, as they are being processed by the same faulty CPU.
The following references to the ISO26262 standard are related to the aspects of test
by software for Processing Units.
ID ISO26262 Reference
010 Part 5: [D.2.3.1] Self Test by software
011 Part 11: [Table 34] Combinatorial and sequential logic
012 Part 5: [Table D.4] Processing Units
013 Part 5: [Table D.1] Analysed failure modes
According to ISO 262622 , detection of the following failures in the volatile memory
is typically considered for the derivation of diagnostic coverage. The following table
provides a preliminary mapping between ISO26262 and RAM Test requirements [12]
[13].
ID Failure Modes of Volatile Memory RAM Test SRS Requirements
001 Low Coverage (60%): A Test algorithm with low coverage shall be available
Stuck-at for data, addresses and control
interface, lines and logic.
002 Medium Coverage (90%): A Test algorithm with medium coverage shall be available
d.c. fault model for data, addresses (includes
address lines within same block and inability to
write to cell) and control interface, lines and
logic
003 Medium Coverage (90%): -
Soft error model for bit cells
004 High Coverage (99%): A Test algorithm with high coverage shall be available
d.c. fault model for data, addresses (includes
address lines within same block and inability to
write to cell) and control interface, lines and
logic
005 High Coverage (99%):
Soft error model for bit cells
Table 4.3: Mapping between Volatile Memory Failure Modes and RAM Test requirements
4.2.2 Description
The RAM Test Driver is an AUTOSAR Basic Software Module which accesses the
microcontroller RAM directly without intermediate software layers. It is located in the
Abstraction Layer (MCAL).
The RAM Test driver performs a test of the physical health of the RAM cells, it is not
intended to test the contents of the RAM. Furthermore, RAM used for registers is also
tested.
Different algorithms exist to test RAM. They target different sets of fault models,
achieve different coverages, result in different runtimes and are either destructive or
non-destructive. Coverage also depends on the underlying physical RAM architecture.
An ECU safety analysis must be performed to determine which RAM Test diagnostic
coverage rate (Low, Medium or High) is required. Appropriate RAM Test algorithms
and further configuration parameters are then selected at compile time. At run time,
the application software may choose between the compiled algorithms (and between
further parameters).
2
[ISO 26262-5, Annex D] Table D.1 Volatile Memory
The RAM Test driver supports synchronous test methods called "foreground test" and
asynchronous tests called "background test". During the execution of a RAM test algo-
rithm, no other software shall be allowed to modify the RAM area under test.
During the execution of non-destructive tests, the RAM Test module saves the contents
of the RAM area under test and restores the original contents thereafter.
RAM Test reports errors to the diagnostic event manager (DEM) as production errors.
4.2.4 Limitations
The following references to the ISO26262 standard are related to the aspects of RAM
Test.
ID ISO26262 Reference
015 Part 11: [5.1.13.5] RAM Pattern test
016 Part 11: [5.1.13.7] RAM March test
012 Part 11: [Table 33] Volatile Memory
013 Part 5: [Table D.1] General semiconductor elements - Volatile Memory
A Appendix
Table A.1: Acronyms and abbreviations used in the scope of this Document
B Related Documentation