ESE5720 final project

Wideband Trans-impedance Amplifier design

Name: Chengjun Li
ID: 47636985
1. Introduction and literature search
In this project, the main job will focus on the operation amplifier building. The aim of this project was designing a
wideband Trans-Impedance Amplifier to transform the 10uA current signal to a 1.5V differential swing voltage
signal. Other requirements refer following table.
No. Parameter Value
1 Technology node (minimum channel length) 600nm (CMOS)
2 Vdd 3V
3 Cp 100fF
4 Load resistance 600Ω (differential)
5 Input current amplitude 10μA
6 Required output peak-to peak voltage swing >1.5V (differential)
7 Trans-impedance gain >150kΩ
8 -3dB bandwidth (BW -3dB) >150Mhz
9 The -3dB low corner frequency <10MHz
10 Total input referred current noise <100nA
11 Largest capacitor available 50pF
12 Smallest capacitor available 10fF
13 Largest resistor available 250kΩ
14 Smallest resistor available 1Ω
15 Total power consumption <25mW

Before start design the circuit structure, the characteristic of the transistor parameter should be studied and explore
the associative relationship between each parameter. The bias current will depend on the bias voltage and the size
of the transistor. When the transistor work in saturation and triode, they individually obey following equation.
2
𝑊 𝑉𝐷𝑆
𝑡𝑟𝑖𝑜𝑑𝑒: 𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 ( ) [(𝑉𝐺𝑆 − 𝑉𝑇 )𝑉𝐷𝑆 − ]
𝐿 2
1 𝑊
𝑠𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛(𝑤𝑖𝑡ℎ 𝑐ℎ𝑎𝑛𝑛𝑒𝑙 𝑒𝑓𝑓𝑒𝑐𝑡): 𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 ( ) (𝑉𝐺𝑆 − 𝑉𝑇 )2 [1 + 𝜆(𝑉𝐷𝑆 − 𝑉𝐺𝑆 + 𝑉𝑡ℎ )]
2 𝐿
The main parameter of the transistor contains Threshold voltage 𝑉𝑡ℎ , transconductance gain 𝑔𝑚 and gate to source
& gate to drain capacitor 𝐶𝑔𝑠 & 𝐶𝑔𝑑 . All of these parameters were effect by the bias station and size of the
transistor. Most of them have regular correlation with the transistor size and bias current. Their expression can
write as following equation.

𝑊
𝑔𝑚 = √2𝜇𝐶𝑜𝑥 ( ) 𝐼𝐷
𝐿

2
𝐶𝑔𝑠 = 3 𝑊𝐿𝐶𝑜𝑥 + 𝑊𝐿𝑜𝑣 𝐶𝑜𝑥 and 𝐶𝑔𝑑 = 𝐶𝑜𝑥 𝑊𝐿𝑜𝑣

𝑞𝑁 𝛿 𝜉 2 )]
∆𝑉𝑇 = [(𝑥𝑛 − 𝑥𝑛0 ) + ( − ) (𝑥𝑛2 − 𝑥𝑛0 [1]
𝐶𝑜𝑥 𝑊 𝐿
According to the requirement, firstly the structure of the amplifier should be considered. There are three main
amplifier types to construct the TIA. They are common gate amplifier, common drain amplifier and differential
amplifier. Where common gate amplifier has low input impedance, it was used to amplify the input current to
voltage. The common drain amplifier has low output resistance and high input impedance which suit to be used as
the buffer between different circuit structures. And differential amplifier can cancel the common mode noise to get
a low noise output. [2] Their work function and input & output resistance will be shown detail in the design
strategy part. Use cascade amplifier structure will help the TIA get a better performance. [3]

For frequency response of the TIA, due to it use the cascade design. The bandwidth of whole circuit always
depends on the bottle neck of all amplifiers. Therefore, in this design, following approximation can be applied.
Use the highest low pass 𝑊3𝑑𝐵 point among all amplifiers as the low pass point as whole circuit low pass point
and lowest high pass 𝑊3𝑑𝐵 point as the whole circuit high pass 𝑊3𝑑𝐵 point. [4]
2. Process characterization
(1) 𝐼𝐷 𝑣𝑠 𝑉𝐷𝑆
𝐼𝐷 𝑣𝑠 𝑉𝐷𝑆 for 0 < 𝑉𝐷𝑆 < 3𝑉, where 𝐿 = 600𝑛𝑚, 𝑎𝑛𝑑 𝑊 = 5𝜇𝑚, 𝑊 = 10𝜇𝑚, 𝑊 = 20𝜇𝑚, 𝑊 = 40𝜇𝑚, 𝑊 = 80𝜇𝑚
In order to get a valid result, the 𝑉𝐺𝑆 was set as 3V.
Test circuit for the NMOS and its simulation parameter (upward parameter was the MOS parameter swing)

The simulation result of NMOS

𝐼𝐷 𝑣𝑠 𝑉𝐷𝑆 for 0 < 𝑉𝑆𝐷 < 3𝑉, where 𝐿 = 600𝑛𝑚, 𝑎𝑛𝑑 𝑊 = 5𝜇𝑚, 𝑊 = 10𝜇𝑚, 𝑊 = 20𝜇𝑚, 𝑊 = 40𝜇𝑚, 𝑊 = 80𝜇𝑚
In order to get a valid result, the 𝑉𝑆𝐺 was set as 3V.
Test circuit for the PMOS and its simulation parameter
The simulation result of PMOS

For this test result, we only analyze the transistor work in saturation region and triode region as approximation.
According to the ESE5720 course material, when the transistor work in the triode region, the relationship between 𝐼𝐷𝑆
2
𝑊 𝑉𝐷𝑆
and bias voltage obey following equation 𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 ( 𝐿 ) [(𝑉𝐺𝑆 − 𝑉𝑇 )𝑉𝐷𝑆 − 2
] and when the transistor work in the

1 𝑊
saturation region the relationship obeys following question 𝐼𝐷 = 2 𝜇𝑛 𝐶𝑜𝑥 ( 𝐿 ) (𝑉𝐺𝑆 − 𝑉𝑇 )2 [1 + 𝜆(𝑉𝐷𝑆 − 𝑉𝐺𝑆 + 𝑉𝑡ℎ )].

From the simulation parameter, we know when 𝑉𝐷𝑆 < 3 − 𝑉𝑡ℎ the transistor work in triode region and when 𝑉𝐷𝑆 >
3 − 𝑉𝑡ℎ the transistor work in saturation. Base on the equation, we know the 𝐼𝐷𝑆 will increase by the 𝑉𝐷𝑆 increasing
where triode region has larger slope than saturation region. Form the equation we know, the 𝐼𝐷 also will increase by
channel width 𝑊 increasing. All of these characteristics were shown in the diagram.
(2) 𝑉𝑡ℎ 𝑣𝑠 𝐼𝐷
𝑉𝑡ℎ 𝑣𝑠 𝐼𝐷 for 0 < 𝐼𝐷𝑆 < 20𝑚𝐴 , where 𝐿 = 600𝑛𝑚, 𝑎𝑛𝑑 𝑊 = 5𝜇𝑚, 𝑊 = 10𝜇𝑚, 𝑊 = 20𝜇𝑚, 𝑊 = 40𝜇𝑚, 𝑊 =
80𝜇𝑚. Connect the transistor in diode connection to get a valid value.
Test circuit for the NMOS and its simulation parameter

The simulation result of NMOS

𝑉𝑡ℎ 𝑣𝑠 𝐼𝐷 for 0 < 𝐼𝑆𝐷 < 20𝑚𝐴 , where 𝐿 = 600𝑛𝑚, 𝑎𝑛𝑑 𝑊 = 5𝜇𝑚, 𝑊 = 10𝜇𝑚, 𝑊 = 20𝜇𝑚, 𝑊 = 40𝜇𝑚, 𝑊 =
80𝜇𝑚. Connect the transistor in diode connection to get a valid value.
Test circuit for the PMOS and its simulation parameter
The simulation result of PMOS

Due to the drain-induced barrier lowering, the 𝑉𝑡ℎ will decrease by the current increasing. The equation of influence of
𝑞𝑁 𝛿 𝜉 2 )].
the channel width on the tendency of threshold voltage ∆𝑉𝑇 = 𝐶 [(𝑥𝑛 − 𝑥𝑛0 ) + (𝑊 − 𝐿) (𝑥𝑛2 − 𝑥𝑛0 By the channel
𝑜𝑥

width increasing the, the capacitance increasing tendency will slow down.
(3) 𝑔𝑚 𝑣𝑠 𝐼𝐷
𝑔𝑚 𝑣𝑠 𝐼𝐷 for 0 < 𝐼𝐷𝑆 < 20𝑚𝐴 , where 𝐿 = 600𝑛𝑚, 𝑎𝑛𝑑 𝑊 = 5𝜇𝑚, 𝑊 = 10𝜇𝑚, 𝑊 = 20𝜇𝑚, 𝑊 = 40𝜇𝑚, 𝑊 =
80𝜇𝑚. Connect the transistor in diode connection to get a valid value.
Test circuit for the NMOS and its simulation parameter

The simulation result of NMOS

𝑔𝑚 𝑣𝑠 𝐼𝐷 for 0 < 𝐼𝑆𝐷 < 20𝑚𝐴 , where 𝐿 = 600𝑛𝑚, 𝑎𝑛𝑑 𝑊 = 5𝜇𝑚, 𝑊 = 10𝜇𝑚, 𝑊 = 20𝜇𝑚, 𝑊 = 40𝜇𝑚, 𝑊 =
80𝜇𝑚. Connect the transistor in diode connection to get a valid value.
Test circuit for the PMOS and its simulation parameter
The simulation result of PMOS

In these testing circuit, all of these transistors were connected in diode connection. Therefore, both of the PMOS and
𝑊
NMOS work in saturation region. We know the expression of the transconductance 𝑔𝑚 = √2𝜇𝐶𝑜𝑥 ( 𝐿 ) 𝐼𝐷 . By

observing the simulation result, we can find 𝑔𝑚 was increase by 𝐼𝐷 increasing and the tendency gradually become
slow down which fit the characteristic of radical function. And the 𝐼𝐷 also increase by the width of the transistor
increasing.
(4) 𝐶𝑔𝑠 𝑣𝑠 𝑊
𝐶𝑔𝑠 𝑎𝑛𝑑 𝐶𝑔𝑑 𝑣𝑠 𝑊 for 4𝜇𝑚 < 𝑊 < 400𝜇𝑚
Test circuit for the NMOS 𝐶𝑔𝑠 𝑎𝑛𝑑 𝐶𝑔𝑑 and its simulation parameter

The 𝐶𝑔𝑠 𝑎𝑛𝑑 𝐶𝑔𝑑 simulation result of NMOS

𝐶𝑔𝑠 𝑎𝑛𝑑 𝐶𝑔𝑑 𝑣𝑠 𝑊 for 4𝜇𝑚 < 𝑊 < 400𝜇𝑚

Test circuit for the PMOS 𝐶𝑔𝑠 𝑎𝑛𝑑 𝐶𝑔𝑑 and its simulation parameter
 The 𝐶𝑔𝑠 𝑎𝑛𝑑 𝐶𝑔𝑑 simulation result of PMOS

2
For the 𝐶𝑔𝑠 𝑎𝑛𝑑 𝐶𝑔𝑑 of the transistor, the expression equation can write as 𝐶𝑔𝑠 = 3 𝑊𝐿𝐶𝑜𝑥 + 𝑊𝐿𝑜𝑣 𝐶𝑜𝑥 and 𝐶𝑔𝑑 =

𝐶𝑜𝑥 𝑊𝐿𝑜𝑣 . Therefore, when we increasing the width of the transistor, the value of 𝐶𝑔𝑠 𝑎𝑛𝑑 𝐶𝑔𝑑 proportional
growth.

(5) 𝑓𝑡 processing with drain current

For the unity frequency, the expression of the 𝑓𝑡 can be written as
1 𝑔𝑚
𝑓𝑡 ≈ = (𝑎𝑠𝑠𝑢𝑚𝑒 𝑡ℎ𝑒 𝑒𝑞𝑢𝑎𝑣𝑖𝑙𝑒𝑛𝑡 𝑟𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 𝑜𝑓 𝑡𝑟𝑎𝑛𝑠𝑖𝑠𝑡𝑜𝑟 𝑤𝑎𝑠 1/𝑔𝑚)
2𝜋(1/𝑔𝑚) 𝐶𝐿 2𝜋𝐶𝐿
Due to 𝐼𝐷 increasing will cause 𝑔𝑚 increasing, therefore, the 𝑓𝑡 also will increase by current increasing.
3. Design strategy
For 150kΩ trans-impedance gain, it was hard to realize by a simple amplifier. Therefore, hierarchical design was
necessary for this design. We analyze the advantage and characteristic of each amplifier in the literature review.
Combine the advantage of each kind of amplifier, this design will arrange the amplifier stages in following
structure.

For first stage, we should transform the 10uA input current to a stable and usable voltage signal. Therefore, this
design chose using the common gate amplifier as the first stage, because it was the only normal amplifier
(common gate & common drain & common source) allow stable current signal input. Compare with two other
amplifiers, the common gate amplifier uses the drain terminal receive the input signal, but other two amplifier use
the gate terminal receive the signal which cause a large variable resistance with frequency. And the input
resistance can write as following equation.
𝑟02 𝑟03
𝑅𝑖𝑛 = ( ) ∗ (1 + )
1 + 𝑔𝑚1 ∗ 𝑟02 𝑟01
In order to get a higher transconductance, this design also should do some modification on the circuit structure.
There are two main modifications on the structure. First, use a transistor (M2) working as the constant current
source to supply the current to whole amplifier structure. Second, use a diode connection transistor (M3) replace
resistance 𝑅𝐷 structure which can give larger output resistance which can help amplifier get a larger gain. Final,
output resistance and transconductance can write as following equation.

𝑟03 ∗ (𝑟01 + 𝑟02 + 𝑔𝑚1 ∗ 𝑟01 ∗ 𝑟02 )

𝑅𝑜𝑢𝑡 =
𝑟03 + 𝑟01 + 𝑟02 + 𝑔𝑚1 ∗ 𝑟01 ∗ 𝑟02
𝑟02 ∗ 𝑔𝑚1
𝐴𝑖 = 𝑅𝑜𝑢𝑡 ∗
1 + 𝑟02 ∗ 𝑔𝑚1
Due to first stage common gate amplifier with a high output resistance, directly connecting first stage to the
voltage amplifier will cause a gain dilution. Therefore, a buffer was necessary between first stage and following
voltage amplifier. Common drain amplifier has high dynamic input impedance and a high output resistance which
was suitable buffer to drive following voltage amplifier. In order to minimize the voltage loss, use the active
resistance (M2) as the 𝑅𝑆 . The output resistance and voltage gain of the buffer can write as following equation.
𝑟02 1
𝑅𝑜𝑢𝑡 = ≈
1 + 𝑟02 ∗ 𝑔𝑚1 𝑔𝑚
𝐴𝐶𝐷 = 𝑔𝑚1 ∗ (𝑟01 ||𝑟02 ||𝑟𝑠1 ||𝑟𝑠𝑏 ) ≈ 1
For the third stage, the design should consider the voltage amplifying in this part. The noise also will be amplified
in this stage. Therefore, in order to reduce the effect of the noise signal, the design use differential amplifier as the
circuit structure to solve this problem. In order to get higher voltage swing region all of these differential
amplifiers use resistance drain load. Consider the bandwidth limitation, in this design, large output resistance will
be the main reason to limit the band width. Therefore, by trade-off many factors, I think use cascade structure will
be more feasible. In this design, four stages differential amplifier were used to get a full voltage gain of the swing
region with a fair frequency response. Due to the gain four stage cascaded differential amplifier was large enough,
the bottle neck will move to the swing range. The gain of four stage differential amplifier can be summarized as
following equation, and we should associate the input signal comparing with the output swing range. (M1 and M2
was the differential pair transistor of this amplifier)

𝑅𝐷 𝑔𝑚1 + 𝑔𝑚2 + 4 ∗ 𝑔𝑚1 ∗ 𝑔𝑚2 ∗ 𝑅𝑆𝑆

𝐴𝐷𝑀2 = ( )∗
2 1 + (𝑔𝑚1 + 𝑔𝑚2 ) ∗ 𝑅𝑆𝑆
𝐴𝑠𝑢𝑚 = 𝐴𝐷𝑀1 ∗ 𝐴𝐷𝑀2 ∗ 𝐴𝐷𝑀3 ∗ 𝐴𝐷𝑀4
𝑠𝑤𝑖𝑛𝑔 𝑟𝑎𝑛𝑔𝑒 = 𝐼𝑆𝑆 ∗ 𝑅𝐷
If 𝐴𝑠𝑢𝑚 ∗ 𝑖𝑛𝑝𝑢𝑡 𝑠𝑖𝑔𝑛𝑎𝑙 > 𝑠𝑤𝑖𝑛𝑔 𝑟𝑎𝑛𝑔𝑒, the final output signal amplitude will be limited to swing range. For last
stage, a buffer was also necessary to drive the 300Ω load. Due to target load with a small resistance, this design
directly uses the load as source resistor 𝑅𝑆 will be more efficiency by less gain loss. If above assumption make
sense, the final output result can write in following format
𝑔𝑚 ∗ 𝑅𝑆
𝐴𝐶𝐷 =
1 + (𝑔𝑚 + 𝑔𝑚𝑏 ) ∗ 𝑅𝑆
𝑜𝑢𝑡𝑝𝑢𝑡 𝑠𝑖𝑔𝑎𝑛𝑙 𝑎𝑚𝑝𝑙𝑖𝑡𝑢𝑑𝑒 = 𝐴𝐶𝐷 ∗ 𝑠𝑤𝑖𝑛𝑔 𝑟𝑎𝑛𝑔𝑒
Additional details, all of active load in each amplifier circuit were biased by the current mirror. Where whole
circuit only have one voltage source 3V which was convenient to organize the power supply net. For the first
differential stage, due to the buffer only be able to generate a single output, a voltage bridge was used to generate
the DC bias and a high pass capacitor structure connect to the ground to simulate the differential input.
4. Hand calculation
For this part all unit were use the metric unit
Parameter name Unit
Resistance 𝑅 Ω
Capacitor 𝐶 F
Transconductance 𝑔𝑚 A/V
Transimpedance 𝐴𝑖 Ω
Voltage gain 𝐴 V/V
Bandwidth 𝑊 Rad/sec

First stage: Common gate amplifier

𝑔𝑚1 = 185.7𝑒 − 6, 𝑟01 = 21.42𝑒3, 𝑟02 = 31.89𝑒3, 𝑟03 = 52.48𝑒3
𝐶𝐿 = 297𝑒 − 18 + 1.847𝑒 − 15 + 4.876𝑒 − 15
𝑟02 𝑟03
𝑅𝑖𝑛 = ( ) ∗ (1 + ) = 1.589𝑒 + 04
1 + 𝑔𝑚1 ∗ 𝑟02 𝑟01
𝑟03 ∗ (𝑟01 + 𝑟02 + 𝑔𝑚1 ∗ 𝑟01 ∗ 𝑟02 )
𝑅𝑜𝑢𝑡 = = 4.064𝑒 + 04
𝑟03 + 𝑟01 + 𝑟02 + 𝑔𝑚1 ∗ 𝑟01 ∗ 𝑟02
𝑟02
𝐴𝑖 = 𝑅𝑜𝑢𝑡 ∗ = 2.7123𝑒 + 04
𝑅𝑖𝑛 + 𝑟02
1
𝑊𝐶𝐺3𝑑𝐵 = = 5.581𝑒 + 08
2 ∗ 𝑝𝑖 ∗ 𝑅𝑜𝑢𝑡 ∗ 𝐶𝐿
Second stage: Common drain amplifier with active load.
𝑔𝑚1 = 384.3𝑒 − 6, 𝑔𝑚𝑏1 = 90.06𝑒 − 6, 𝑟01 = 48.09𝑒3, 𝑟02 = 15.05𝑒3
1 1
𝑟𝑠1 = , 𝑟𝑠𝑏 =
𝑔𝑚1 𝑔𝑚𝑏1
𝐶𝐿 = 𝐶𝑔𝑑 + 𝐶𝑑𝑏 + 𝐶𝑔𝑠−𝑛𝑒𝑥𝑡𝑠𝑡𝑎𝑔𝑒 + 𝐶𝑔𝑏−𝑛𝑒𝑥𝑡𝑠𝑡𝑎𝑔𝑒 + 𝐶𝑔𝑑−𝑛𝑒𝑥𝑡𝑠𝑡𝑎𝑔𝑒
𝑟02
𝑅𝑜𝑢𝑡 = = 2.218𝑒 + 03
1 + 𝑟02 ∗ 𝑔𝑚1
𝐴𝐶𝐷 = 𝑔𝑚1 ∗ (𝑟01 ||𝑟02 ||𝑟𝑠1 ||𝑟𝑠𝑏 ) = 0.683
1
𝑊𝐶𝐷3𝑑𝐵 = = 2.609𝑒 + 09
2 ∗ 𝑝𝑖 ∗ 𝑅𝑜𝑢𝑡 ∗ 𝐶𝐿
Third stage: 4 stages amplifier
𝑅𝐷 ∗ 𝑟01
𝑅𝑜𝑢𝑡 =
𝑅𝐷 + 𝑟01
𝑅𝐷 𝑔𝑚1 + 𝑔𝑚2 + 4 ∗ 𝑔𝑚1 ∗ 𝑔𝑚2 ∗ 𝑅𝑆𝑆
𝐴𝐷𝑀 = ( ) ∗
2 1 + (𝑔𝑚1 + 𝑔𝑚2 ) ∗ 𝑅𝑆𝑆
𝐴𝐷𝑀1 = 5.086, 𝑊𝐷𝑀1,3𝑑𝐵 = 1.125𝑒 + 09
𝐴𝐷𝑀2 = 4.394, 𝑊𝐷𝑀2,3𝑑𝐵 = 1.692𝑒 + 09
𝐴𝐷𝑀3 = 3.179, 𝑊𝐷𝑀3,3𝑑𝐵 = 2.528𝑒 + 09
𝐴𝐷𝑀4 = 2.692, 𝑊𝐷𝑀4,3𝑑𝐵 = 1.375𝑒 + 09
𝐴𝑠𝑢𝑚 = 𝐴𝐷𝑀1 ∗ 𝐴𝐷𝑀2 ∗ 𝐴𝐷𝑀3 ∗ 𝐴𝐷𝑀4 = 191.248
1 1
𝑊𝐷𝑀3𝑑𝐵 = ≈
2 ∗ 𝑝𝑖 ∗ 𝑅𝑜𝑢𝑡 ∗ 𝐶𝐿 2 ∗ 𝑝𝑖 ∗ 𝑅𝐷 ∗ 𝐶𝐿
𝑊𝐷𝑀3𝑑𝐵 point Frequency
W_D1_3dB 8.004169853720680e+08
W_D2_3dB 3.479056735617660e+09
W_D3_3dB 3.560942856663867e+09
W_D4_3dB 8.412082199637016e+08
Stage 4 DC bias
𝑅_𝐷 = 4𝑒3
 𝐼_𝑆𝑆 = 428.8𝑒 − 6
𝑠𝑤𝑖𝑛𝑔𝑟𝑎𝑛𝑔𝑒 = 𝐼𝑆𝑆 ∗ 𝑅𝐷 = 1.7152
Fourth stage: common source amplifier
𝑔𝑚 = 2.698𝑒 − 3, 𝑔𝑚𝑏 = 558.6𝑒 − 6
𝑅𝑆 = 600, 𝐶𝐿 = 12.02𝑒 − 15
𝑔𝑚 ∗ 𝑅𝑆
𝐴𝐶𝐷𝑒𝑛𝑑 = = 0.6181
1 + (𝑔𝑚 + 𝑔𝑚𝑏 ) ∗ 𝑅𝑆
1
𝑊𝐶𝐷𝑒𝑛𝑑3𝑑𝐵 = = 3.587𝑒 + 09
2 ∗ 𝑝𝑖 ∗ 𝑅𝑜𝑢𝑡 ∗ 𝐶𝐿

Assume the input signal was a constant input signal 10𝜇𝐴

Amplifier name Voltage and transimpedance gain Output signal (V) or (A)
Input circuit structure 1 10uA
First stage common gate amplifier 2.7123𝑒 + 04Ω 0.27123V
Second stage common drain amplifier 0.683 0.18525V
Third stage 1st differential amplifier 5.086 0.92625V
Third stage 2nd differential amplifier 4.394 3.7V
Third stage 3rd differential amplifier 3.179 11.74V
Third stage 4th differential amplifier 2.692 23.49V
Last stage output common drain amplifier 0.6181 14.519V

The output voltage of last differential stage ≫ swing range. Therefore, we can think the final differential output
depend on the swing range and output buffer gain.

Amplifier name Voltage and transimpedance gain Output signal (V) or (A)
Swing range 1.7152V
Last stage output common drain amplifier 0.6181 1.06V (*2 for differential)

Due to this circuit don’ have high pass RC circuit structure, the lower conner 3dB point was 1Hz. When we
calculate the 3dB point, we choose bottle neck (lowest one) as the bandwidth 3dB point
3dB point Frequency (Hz)
W_CD3dB 2.608936415660623e+09
W_CDe_3dB 1.019565045395114e+11
W_CG3dB 5.581310212896597e+08
W_D1_3dB 8.004169853720680e+08
W_D2_3dB 3.479056735617660e+09
W_D3_3dB 3.560942856663867e+09
W_D4_3dB 8.412082199637016e+08

𝑊3𝑑𝐵 ≈ 5.581e + 08Hz

5. Cadence simulation result
(1) DC operating point summary table
First stage common gate amplifier & Second stage common drain amplifier

Third stage differential amplifier 1st & 2nd

Third stage differential amplifier 3rd & 4th

Input & output circuit structure

 Input & output bias
Amplifier name Input dc bias (V) Output dc bias (V)
Input circuit structure 0.9043
First stage common gate amplifier 0.9043 1.512
Second stage common drain amplifier 1.512 0.7151
Third stage 1st differential amplifier 0.7151 2.599
Third stage 2nd differential amplifier 2.599 1.864
Third stage 3rd differential amplifier 1.864 1.961
Third stage 4th differential amplifier 1.961 2.142
Last stage output common drain amplifier 2.142 0.5632
Active load bias
Amplifier name Bias 1 Bias 2
First stage common gate amplifier 2.005 0.9164
Second stage common drain amplifier 1.013
Third stage 1st differential amplifier 1.532
Third stage 2nd differential amplifier 1.532
Third stage 3rd differential amplifier 1.532
Third stage 4th differential amplifier 1.532

(2) AC simulation of TIA transfer function

Simulation parameter and plot function
 Simulation result
Where trans-impedance gain 𝐴(𝑑𝐵) ≈ 109.987 ≈ 300𝑘Ω and 3dB point 𝑊3𝑑𝑏 ≈ 159.1𝑀𝐻𝑧

(3) Transient simulation output waveform

Simulation setting

Swing simulation result

Where the differential swing range ≈ 2 ∗ (950.881𝑚𝑉 − 186.7519𝑚𝑉) = 1.528𝑉 𝐴𝑖 = 152.8𝑘Ω

(4) Noise simulation

(5) Evidence of stable operation

Stability simulation parameter
 Stability testing current source setting

Stability testing result show the circuit was stable enough

(6) Power consumption = 3𝑉 ∗ 6.705𝑚𝐴 = 20.115𝑚𝑊

 (7) Table of summarizes achieved performance
No. Parameter Value
1 Technology node (minimum channel length) 600nm (CMOS)
2 Vdd 3V
3 Cp 100fF
4 Load resistance 600Ω (differential)
5 Input current amplitude 10μA
6 Required output peak-to peak voltage swing 1.528𝑉
7 Trans-impedance gain 152.8kΩ
8 -3dB bandwidth (BW -3dB) 159.1Mhz
9 The -3dB low corner frequency 1Hz
10 Total input referred current noise 35.4969nA
11 Largest capacitor available 50pF
12 Smallest capacitor available 100fF
13 Largest resistor available 35K
14 Smallest resistor available 300Ω
15 Total power consumption 20.115𝑚𝑊

6. Comparison of hand calculation and simulation

Tran impedance gain Swing output 3dB point
Simulation ≈300 𝑘Ω 1.528𝑉 (152.8𝑘Ω) 159.1MHz
Hand ≈ 140 𝑘Ω 2.16V (216 𝑘Ω) 558MHz
Due to the signal was get the limitation of swing range in 2nd and 3rd differential stage, the trans impedance gain
will have a larger distinct. (This was only a approximation result, final output gain will depend on the swing range
of last different stage and output buffer). The bandwidth 3dB point and final trans impedance gain were very close
to the simulation result. Therefore, the design of this TIA can be seen as reasonable. Hand calculation and
simulation result were able to verify each other.

7. Conclusion
In this project, all of the simulation and hand calculation result were shown the report. The relationship between
drain to source current and bias situation was analyzed by plot their trend. The associative parameter of the
transistor also be shown a regular relationship about the dc bias situation. For TIA design, a four stages (four
differential amplifiers seem as one stage) structure was applied in this design to get trade-off result between
transimpedance gain and the band width. Finally, the transimpedance gain get 109.987dB≈ 315.936kΩ. The low
pass 3dB point was 1Hz and the high pass point was 159MHz. The bandwidth of whole amplifier was about
159MHz. The noise and stability were also meet the requirement. The hand calculation results were shown in the
report which approach to the simulation result. Therefore, it can be seen as a verification of the design TIA circuit.

8. Reference

[1] Paul R. Gray; Paul J. Hurst; Stephen H. Lewis; Robert G. Meyer (2001). Analysis and Design of Analog
Integrated Circuits (4th ed.). New York: Wiley. pp. 186–191. ISBN 0-471-32168-0.
[2] “Cascade Amplifier Working and Its Applications” URL: https://www.elprocus.com/cascade-amplifier-
working-applications/
[3] Dennis L. Feucht (1990). Handbook of Analog Circuit Design. Elsevier Science. p. 192. ISBN 978-1-4832-5938-3
[4] D. A. BELL, R. LAXTON “Influence of the Channel Width on the Threshold Voltage Modulation” ELECTRONICS
LETTERS, 10th July 1975, vol 11, No. 14

9. Appendix (matlab hand calculation code)

%%
pi=3.14;
%common gate
g_m1=185.7e-6;
r_01=21.42e3;
r_02=31.89e3;
r_03=52.48e3;
C_L=297e-18+1.847e-15+4.876e-15;

R_in=(r_02/(1+g_m1*r_02))*(1+r_03/r_01);

R_out=(r_03*(r_01+r_02+g_m1*r_01*r_02))/(r_03+r_01+r_02+g_m1*r_01*r_02);
A_CG=R_out/R_in;
A_i=R_out*(r_02)/(R_in+r_02);
W_CG3dB=1/(2*pi*R_out*C_L);

%%
%common drain
g_m1=384.3e-6;
g_mb1=90.06e-6;
r_01=48.09e3;
r_02=15.05e3;
r_s1=1/g_m1;
r_sb=1/g_mb1;
C_L=2.042e-15+829.1e-18+24.64e-15;

R_out=(r_02)/(1+r_02*g_m1);

A_CD=g_m1*(r_01*r_02*r_s1*r_sb)/(r_01*r_02*r_s1+r_01*r_02*r_sb+r_02*r_s1*r_sb+r_01*r_s1*r_sb);
W_CD3dB=1/(2*pi*R_out*C_L);

%%
%differential amplifier 1
R_D=8e3;
R_SS=528;
g_m1=635.9e-6;
g_m2=635.7e-6;
r_01=50.81e3;
C_L=10.45e-15+11.19e-15+1.923e-15+2.643e-15+2.577e-15;

R_out=(R_D*r_01)/(R_D+r_01);

A_DM1=(R_D/2)*(g_m1+g_m2+4*g_m1*g_m2*R_SS)/(1+(g_m1+g_m2)*R_SS);
W_D1_3dB=1/(2*pi*R_out*C_L);

%%
%differential amplifier 2
R_D=8e3;
R_SS=4.753e3;
g_m1=549.2e-6;
g_m2=549.2e-6;
r_01=3.614e3;
C_L=2.643e-15+0.3478e-15+9.964e-15+2.606e-15+2.825e-15;

R_out=(R_D*r_01)/(R_D+r_01);

A_DM2=(R_D/2)*(g_m1+g_m2+4*g_m1*g_m2*R_SS)/(1+(g_m1+g_m2)*R_SS);
W_D2_3dB=1/(2*pi*R_out*C_L);

%%
%differential amplifier 3
R_D=5e3;
R_SS=1.516e3;
g_m1=635.9e-6;
g_m2=635.7e-6;
r_01=6.4e3;
C_L=2.606e-15+0.5145e-15+9.985e-15+2.799e-15+2.603e-17;

R_out=(R_D*r_01)/(R_D+r_01);

A_DM3=(R_D/2)*(g_m1+g_m2+4*g_m1*g_m2*R_SS)/(1+(g_m1+g_m2)*R_SS);
W_D3_3dB=1/(2*pi*R_out*C_L);

%%
%differential amplifier 4
R_D=4e3;
R_SS=1.654e3;
g_m1=673e-6;
g_m2=673e-6;
r_01=6.656e3;
C_L=2.606e-15+0.5145e-15+27.47e-15+9.21e-15+7.523e-15;

R_out=(R_D*r_01)/(R_D+r_01);

A_DM4=(R_D/2)*(g_m1+g_m2+4*g_m1*g_m2*R_SS)/(1+(g_m1+g_m2)*R_SS);
W_D4_3dB=1/(2*pi*R_D*C_L);

%%
%differential dc bias

A_sum=A_DM1*A_DM2*A_DM3*A_DM4;

R_D=4e3;
I_SS=428.8e-6;

swing_range=I_SS*R_D;

%%
%common drain

g_m=2.698e-3;
g_mb=558.6e-6;
R_S=600;
C_L=2.603e-15;

A_CD_end=(g_m*R_S)/(1+(g_m)*R_S);
W_CDe_3dB=1/(2*pi*R_S*C_L);