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Dldlab Report 8

The document outlines a lab experiment focused on designing and implementing an n-bit adder/subtractor circuit. It details the functionality of half adders, full adders, and half subtractors, and explains how to integrate these components to perform binary addition and subtraction. The conclusion highlights the successful verification of the circuit's functionality and its significance in digital computation.

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emanfatima2t8
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2 views10 pages

Dldlab Report 8

The document outlines a lab experiment focused on designing and implementing an n-bit adder/subtractor circuit. It details the functionality of half adders, full adders, and half subtractors, and explains how to integrate these components to perform binary addition and subtraction. The conclusion highlights the successful verification of the circuit's functionality and its significance in digital computation.

Uploaded by

emanfatima2t8
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EEE240 Fundamental of Digital Logic Design

Lab # 08: Design and Implementation of n-bit


Adder/Subtractor

Safia Mahnoor
Name Eman Fatima
SP24-BAI-046
Registration No. SP24-BAI-015
BSAI-2
Class
Dr. Muhammad Rizwan Azam
Instructor’s Name

Lab Assessment
Post Lab Total
In-Lab
Data Presentation Data Analysis Writing Style

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Pre-Lab:
• Objectives:
The objective of this experiment is to study the functionality of
binary addition and subtraction using an n-bit adder/subtractor circuit. It involves
designing a combinational circuit capable of performing both operations on n-bit
binary numbers and implementing it using hardware or simulation tools.

• Introduction:
1) Half Adder:
A half adder is a basic combinational circuit used to perform the
addition of two single-bit binary numbers. It produces two outputs:
1. Sum (S): The XOR of the two input bits.
2. Carry (C): The AND of the two input bits.
2) Full Adder:
A full adder is an extended version of the half adder that can add
three bits: two input bits and a carry bit from the previous stage. It also produces two
outputs:
1. Sum (S): The XOR of all three inputs.
2. Carry (C): The OR of the AND combinations of the inputs.
The full adder is essential for multi-bit addition, as it can handle the carry
propagation between successive stages.
3) Half Subtractor:
A half subtractor is a combinational circuit that performs the
subtraction of two single-bit binary numbers. It provides two outputs:
1. Difference (D): The XOR of the two input bits.
2. Borrow (B): The AND of the complement of the minuend and the subtrahend.
The half subtractor cannot process borrow inputs, limiting its use to the least
significant bit in subtraction.

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4) N-bit Adder/Subtractor:
An n-bit adder/subtractor is a combinational
circuit that can perform addition or subtraction on two binary numbers of n-bits.
To perform both operations within a single circuit:
➢ A control signal, often labeled M, determines the operation mode:
o M = 0: Perform addition.
o M = 1: Perform subtraction.
➢ XOR gates are used to toggle the subtrahend bits based on the control signal.
➢ A full adder is used to process the bits, incorporating the carry or borrow logic.

In-Lab:
1) Half Adder:
• Proteus Implementation:

• Gate-Level Model:

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• Stimulus:

• Simulation:

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2) Full Adder:
• Proteus Implementation:

• Gate-Level Model:

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• Stimulus:

• Simulation:

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3) 4-bit Adder:
• Gate-Level Model:

• Stimulus:

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• Simulation:

Post-Lab:
4) 4-bit Adder/Subtractor:

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• Gate-Level Model:

• Stimulus:

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• Simulation:

Conclusion:
Through this experiment, we successfully developed a circuit capable
of performing both addition and subtraction by integrating full adders and XOR
gates for mode selection. The implementation verified the circuit's functionality,
accuracy, and efficiency across various test cases. Overall, it demonstrates how basic
building blocks, like half and full adders, contribute to the foundation of modern
digital computation.

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