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Lec2 Sequential Logic Circuits Latches - 241213 - 161211

The document provides an overview of latches, which are binary storage elements used in digital circuits. It details the SR latch and D latch types, their construction using NOR and NAND gates, and their operational characteristics. Additionally, it explains the controlled SR latch with an enable input and the functionality of the D latch in capturing data during clock pulses.
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0% found this document useful (0 votes)
14 views13 pages

Lec2 Sequential Logic Circuits Latches - 241213 - 161211

The document provides an overview of latches, which are binary storage elements used in digital circuits. It details the SR latch and D latch types, their construction using NOR and NAND gates, and their operational characteristics. Additionally, it explains the controlled SR latch with an enable input and the functionality of the D latch in capturing data during clock pulses.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Benha University

Shoubra Faculty of Engineering


Communication and Computer Program

Logic Circuits
CCE 301

Sequential Logic Circuits


Lec. 2 Latches

Presented By

Dr. Maher Abdelrasoul


Latches
o A latch is binary storage element which can
store a 0 or 1 (the most basic memory).
o A latch is a bistable device, with inputs, that
remains in a given state as long as power is
applied and until input signals are applied to
cause its output to change.
o A bistable device is a circuit having two stable
conditions (states).
o Easy to build with gates (NORs, NANDs, NOT)
o It has two types
1. SR-Latch
2. D-Latch
2
SR Latch
o The S-R (Set-Reset) latch is the most basic type. It can be
constructed from NOR gates or NAND gates.
o With NOR gates, the latch responds to active-HIGH inputs;
o With NAND gates, it responds to active-LOW inputs.

S R Q S’ R’ Q
0 0 Q0 No change 0 0 Q=Q’=1 Invalid
0 1 0 Reset 0 1 1 Set
1 0 1 Set 1 0 0 Reset
1 1 Q=Q’=0 Invalid 1 1 Q0 No change

o Never apply an active set and reset at the same time (invalid). 3
Graphic Symbols for Latches

o A latch is designated by a rectangular block with


inputs on the left and outputs on the right.

o One output represents the normal output, the other


(with the bubble) represents the complement.

o For S’R’ (SR built with NANDs), bubbles added to


the input.
4
SR Latch

Show the Q output with relation to the input signals applied to


the latch shown in Fig. Assume Q = 0 initially.

Set Reset Reset Set

No change No change

5
SR Latch

Show the Q output with relation to the input signals applied to


the latch shown in Fig. Assume Q = 0 initially.

Set Reset Reset Set

No change No change

5
SR Latch

Determine the Q output with relation to the input signals.


Assume Q = 0 initially.

Reset Set Set Reset


No change No change No change

6
SR Latch

Determine the Q output with relation to the input signals.


Assume Q = 0 initially.

Reset Set Set Reset


No change No change No change

6
Controlled SR Latch
o SR Latch with Control Input (Gated SR latch)
o The gated latch has an additional input, called enable (EN) that must
be HIGH in order for the latch to respond to the S and R inputs.

C S R Q
0 x x Q0 No change
1 0 0 Q0 No change S
1 0 1 0 Reset R
1 1 0 1 EN
Set
Q
1 1 1 Q=Q’ Invalid
9
Controlled SR Latch
o SR Latch with Control Input (Gated SR latch)
o The gated latch has an additional input, called enable (EN) that must
be HIGH in order for the latch to respond to the S and R inputs.

C S R Q
0 x x Q0 No change
1 0 0 Q0 No change S
1 0 1 0 Reset R
1 1 0 1 EN
Set
Q
1 1 1 Q=Q’ Invalid
10
D-Latch (Data Latch)
⚫ The D latch (D for "data") or transparent latch
is a simple extension of the gated SR latch that
removes the possibility of invalid input states.
⚫ The D latch is used to capture, or 'latch' the logic
level which is present on the Data line when the
clock input is high.
⚫ If the data on the D line changes state while the clock pulse
is high, then the output, Q, follows the input, D.
⚫ When the CLK input falls to logic 0, the last state of the D
input is trapped and held in the latch.

C D Q
0 x Q0 No change
1 0 0 Reset
1 1 1 Set
11
D-Latch (Data Latch)
⚫ The D latch (D for "data") or transparent latch
is a simple extension of the gated SR latch that
removes the possibility of invalid input states.
⚫ The D latch is used to capture, or 'latch' the logic
level which is present on the Data line when the
clock input is high.
⚫ If the data on the D line changes state while the clock pulse
is high, then the output, Q, follows the input, D.
⚫ When the CLK input falls to logic 0, the last state of the D
input is trapped and held in the latch.

C D Q
0 x Q0 No change
1 0 0 Reset
1 1 1 Set
12
13

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