Lec2 Sequential Logic Circuits Latches - 241213 - 161211
Lec2 Sequential Logic Circuits Latches - 241213 - 161211
Logic Circuits
CCE 301
Presented By
S R Q S’ R’ Q
0 0 Q0 No change 0 0 Q=Q’=1 Invalid
0 1 0 Reset 0 1 1 Set
1 0 1 Set 1 0 0 Reset
1 1 Q=Q’=0 Invalid 1 1 Q0 No change
o Never apply an active set and reset at the same time (invalid). 3
Graphic Symbols for Latches
No change No change
5
SR Latch
No change No change
5
SR Latch
6
SR Latch
6
Controlled SR Latch
o SR Latch with Control Input (Gated SR latch)
o The gated latch has an additional input, called enable (EN) that must
be HIGH in order for the latch to respond to the S and R inputs.
C S R Q
0 x x Q0 No change
1 0 0 Q0 No change S
1 0 1 0 Reset R
1 1 0 1 EN
Set
Q
1 1 1 Q=Q’ Invalid
9
Controlled SR Latch
o SR Latch with Control Input (Gated SR latch)
o The gated latch has an additional input, called enable (EN) that must
be HIGH in order for the latch to respond to the S and R inputs.
C S R Q
0 x x Q0 No change
1 0 0 Q0 No change S
1 0 1 0 Reset R
1 1 0 1 EN
Set
Q
1 1 1 Q=Q’ Invalid
10
D-Latch (Data Latch)
⚫ The D latch (D for "data") or transparent latch
is a simple extension of the gated SR latch that
removes the possibility of invalid input states.
⚫ The D latch is used to capture, or 'latch' the logic
level which is present on the Data line when the
clock input is high.
⚫ If the data on the D line changes state while the clock pulse
is high, then the output, Q, follows the input, D.
⚫ When the CLK input falls to logic 0, the last state of the D
input is trapped and held in the latch.
C D Q
0 x Q0 No change
1 0 0 Reset
1 1 1 Set
11
D-Latch (Data Latch)
⚫ The D latch (D for "data") or transparent latch
is a simple extension of the gated SR latch that
removes the possibility of invalid input states.
⚫ The D latch is used to capture, or 'latch' the logic
level which is present on the Data line when the
clock input is high.
⚫ If the data on the D line changes state while the clock pulse
is high, then the output, Q, follows the input, D.
⚫ When the CLK input falls to logic 0, the last state of the D
input is trapped and held in the latch.
C D Q
0 x Q0 No change
1 0 0 Reset
1 1 1 Set
12
13