+

William Stallings
Computer Organization
and Architecture
10th Edition
© 2016 Pearson Education, Inc., Hoboken,
NJ. All rights reserved.
+ Chapter 3
A Top-Level View of Computer
Function and Interconnection
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Computer Components
 Contemporary computer designs are
based on concepts developed by John von
Neumann at the Institute for Advanced
Studies, Princeton;
 Referred to as the von Neumann architecture
and is based on three key concepts:
 Data and instructions are stored in a single read-
write memory
 The contents of this memory are addressable by
location, without regard to the type of data
contained there.
 Execution occurs in a sequential fashion (unless
explicitly modified) from one instruction to the next.
+
Computer Components
 Thesummary of the concepts was discussed
in Chapter 2:
 There is a small set of basic logic components that can
be combined in various ways to store binary data and
perform arithmetic and logical operations on that data;
 There
are tow ways to combined the basic logic
components:
 Programming in hardware:
 to construct a special-purpose configuration,
 The resulting “program” is in the form of hardware
and is termed a hardwired program.
 Programming in software:
 to construct a general-purpose configuration,
 The method of programming, a sequence of codes or
instructions is called software.
+ Data
Data
Sequence of
arithmetic
Sequence
and
of
logic
arithmetic
functions
and logic
Results
Results
functions
(a) Programming in hardware

Hardware (a) Programming in hardware

and Software Instruction Instruction

Approaches
codes
Instruction interpreter
Instruction
codes interpreter
Control
signals
Control
signals
General-purpose
Data arithmetic
General-purpose Results
and logic
arithmetic
Data functions Results
and logic
functions
(b) Programming in software
(b) Programming in software

Figure 3.1 Hardware and Software Approaches

Figure 3.1 Hardware and Software Approaches
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Software
• A sequence of codes or instructions
• Part of the hardware interprets each instruction and
Software
generates control signals
• Provide a new sequence of codes for each new
program instead of rewiring the hardware.

Major Components:
• CPU
•Instruction interpreter I/O
•Module of general-purpose arithmetic and logic functions Components
• I/O Components
• Input module
• Contains basic components for accepting data and
instructions and converting them into an internal
+ form of signals usable by the system
• Output module: Means of reporting results
• Memory, or Main Memory
• operations on data may require access to more than
just one element at a time in a predetermined sequence.
• there must be a place to temporarily store both
instructions and data.
Data Exchange Between CPU & Memory
and CPU & I/O
Memory address Memory buffer MEMORY
register (MAR) register (MBR)
• Specifies the • Contains the data
address in to be written into
memory for the memory or
next read or write receives the data
read from
memory
MAR

I/O address I/O buffer

register (I/OAR) register (I/OBR)
+ • Specifies a • Used for the
particular I/O exchange of data
device between an I/O
module and the MBR
CPU

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The basic function
performed by a CPU Main Memory
0
computer is System 1
2
PC MAR Bus
execution of a Instruction
Instruction
program; IR MBR
Instruction

• Program is consists of
a set of instructions I/O AR
Data
Execution
stored in memory. unit Data
I/O BR
• An instruction Data
Data
processing consists of
two steps: I/O Module n–2
 The processor reads n–1

(fetches) instructions
from memory one at a
time,
PC = Program counter
 Then executes each Buffers IR = Instruction register
MAR = Memory address register
instruction. MBR = Memory buffer register
I/O AR = Input/output address register
Figure 3.2 illustrates the top-level I/O BR = Input/output buffer register
components and suggests the
interactions among them. Figure 3.2 Computer Components: Top-Level View
Instruction Fetch and Execute

Fetch Cycle Execute Cycle

Fetch Next Execute

START HALT
Instruction Instruction

Figure 3.3 Basic Instruction Cycle

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+
Instruction Fetch and Execute

At the beginning of each instruction cycle:

 Instruction Fetch:
 the processor fetches an instruction from memory;
 The program counter (PC) holds the address of the
instruction to be fetched next;
 The processor increments the PC after each instruction
fetch so that it will fetch the next instruction in
sequence;
 The fetched instruction is loaded into the instruction
buffer register (IBR), then instruction register (IR);
 Instruction Execution:
 The processor interprets the instruction and performs
the required action: CPU-MM, CPU-I/O, Data
Processing, or Control; for example:
 Loaded AC from M, MAR=PC, fetch M(MAR),
PC=PC+1, AC=AC ± M(MAR), ..etc.
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When processor interprets the instruction, then performs
the required action, the required action categories to:
• Data transferred to
• Data transferred or from a peripheral
from processor to device by
memory or from transferring
memory to between the
processor processor and an
Processor- Processor- I/O module
memory I/O

Data
Control
processing

• An instruction may • The processor may

specify that the perform some
sequence of arithmetic or logic
execution be operation on data
altered
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0 3 4 15
Opcode Address

(a) Instruction format

0 1 15
S Magnitude

(b) Integer format

Program Counter (PC) = Address of instruction

Instruction Register (IR) = Instruction being executed
Accumulator (AC) = Temporary storage

(c) Internal CPU registers

0001 = Load AC from Memory

0010 = Store AC to Memory
0101 = Add to AC from Memory

(d) Partial list of opcodes

Figure 3.4 Characteristics of a Hypothetical Machine

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 Memory CPU Registers Memory CPU Registers
Example: 300 1 9 4 0
301 5 9 4 1
3 0 0 PC 300 1 9 4 0
AC 301 5 9 4 1
3 0 1 PC
0 0 0 3 AC
302 2 9 4 1 1 9 4 0 IR 302 2 9 4 1 1 9 4 0 IR
The program •
•
•
•
940 0 0 0 3 940 0 0 0 3
fragment shown adds 941 0 0 0 2 941 0 0 0 2
the contents of the Step 1 Step 2
memory word at Memory CPU Registers Memory CPU Registers
address 940 to the 300 1 9 4 0 3 0 1 PC 300 1 9 4 0 3 0 2 PC
301 5 9 4 1 0 0 0 3 AC 301 5 9 4 1 0 0 0 5 AC
contents of the 302 2 9 4 1 5 9 4 1 IR 302 2 9 4 1 5 9 4 1 IR
• •
memory word at •
940 0 0 0 3
•
940 0 0 0 3 3+2=5
address 941 and 941 0 0 0 2 941 0 0 0 2

stores the result in Step 3 Step 4

the address 941. Memory CPU Registers Memory CPU Registers

300 1 9 4 0 3 0 2 PC 300 1 9 4 0 3 0 3 PC
301 5 9 4 1 0 0 0 5 AC 301 5 9 4 1 0 0 0 5 AC
Partial list of opcodes 302 2 9 4 1 2 9 4 1 IR 302 2 9 4 1 2 9 4 1 IR
• •

• 0001 = Load AC •
940 0 0 0 3
941 0 0 0 2
•
940 0 0 0 3
941 0 0 0 5
from memory
• 0010 = Store AC to Step 5 Step 6

memory
• 0101 = Add to AC
from memory
Figure 3.5 Example of Program Execution
(contents of memory and registers in hexadecimal)
 Instruction Operand Operand
fetch fetch store

Multiple Multiple
operands results

Instruction Instruction Operand Operand

Data
address operation address address
Operation
calculation decoding calculation calculation

Return for string

Instruction complete, or vector data
fetch next instruction

Figure 3.6 Instruction Cycle State Diagram

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 Interrupt
Table 3.1 Classes of Interrupts
Interrupt
Description
Class
Generated by some condition that occurs as a result of
an instruction execution, such as arithmetic overflow,
Program division by zero, attempt to execute an illegal machine
instruction, or reference outside a user’s allowed
memory space.
Generated by a timer within the processor.
Timer This allows the operating system to perform certain
functions on a regular basis.
Generated by an I/O controller, to signal normal
I/O completion of an operation, request service from the
processor, or to signal a variety of error conditions.
Hardware Generated by a failure such as power failure or memory
Failure parity error.
 User I/O User I/O User I/O
Program Program Program Program Program Program

1 4 1 4 1 4

I/O I/O I/O

Command Command Command
WRITE WRITE WRITE
5
2a
END
2 2

Interrupt Interrupt
2b Handler Handler

WRITE WRITE 5 WRITE 5

END END
3a

3 3

3b

WRITE WRITE WRITE

(a) No interrupts (b) Interrupts; short I/O wait (c) Interrupts; long I/O wait

= interrupt occurs during course of execution of user program

Figure 3.7 Program Flow of Control Without and With Interrupts

 User Program Interrupt Handler

i
Interrupt
occurs here i+1

Figure 3.8 Transfer of Control via Interrupts

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 Fetch Cycle Execute Cycle Interrupt Cycle

Interrupts
Disabled
Check for
Fetch Next Execute
START Interrupt;
Instruction Instruction Interrupts Process Interrupt
Enabled

HALT

Figure 3.9 Instruction Cycle with Interrupts

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 Time

1 1

4 4
I/O operation
I/O operation;
processor waits 2a concurrent with
processor executing

5 5

2b
2
4
I/O operation
4 3a concurrent with
processor executing
I/O operation;
processor waits 5

5 3b

(b) With interrupts

3

(a) Without interrupts

Figure 3.10 Program Timing: Short I/O Wait

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 Time

1 1

4 4

I/O operation; 2 I/O operation

processor waits concurrent with
processor executing;
then processor
waits
5

5
2
4
4
3 I/O operation
concurrent with
I/O operation; processor executing;
processor waits then processor
waits

5
5

3 (b) With interrupts

(a) Without interrupts

Figure 3.11 Program Timing: Long I/O Wait

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Instruction Operand Operand
fetch fetch store

Multiple Multiple
operands results

Instruction Instruction Operand Operand

Data Interrupt
address operation address address Interrupt
Operation check
calculation decoding calculation calculation

No
Instruction complete, Return for string interrupt
fetch next instruction or vector data

Figure 3.12 Instruction Cycle State Diagram, With Interrupts

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 Interrupt
User program handler X
Interrupt
User program handler X

Dealing With
Multiple Interrupts Interrupt
handler Y
Interrupt
handler Y

(a) Sequential interrupt processing

(a) Sequential interrupt processing
Interrupt
User program handler X
Interrupt
User program handler X

Interrupt
handler Y
Interrupt
handler Y

(b) Nested interrupt processing

(b) Nested interrupt processing
Figure 3.13 Transfer of Control with Multiple Interrupts
Figure 3.13 Transfer of Control with Multiple Interrupts
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 Printer Communication
User program
interrupt service routine interrupt service routine
t=0

15
0 t=
t =1

t = 25

t= t = 25 Disk
40 interrupt service routine

t=
35

Figure 3.14 Example Time Sequence of Multiple Interrupts

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+ I/O Function
 I/O module (e.g., a disk controller) can exchange
data directly with the processor;
 Processor can read data from or write data to an I/O
module:
 Processor identifies a specific device that is controlled by a
particular I/O module,
 I/O instructions rather than memory referencing instructions.
 In some cases it is desirable to allow I/O exchanges to
occur directly with memory:
 The processor grants to an I/O module the authority to read
from or write to memory,
 so that the I/O memory transfer can occur without tying up the
processor.
 The I/O module issues read or write commands to memory
relieving the processor of responsibility for the exchange,
 This operation is known as direct memory access (DMA).
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 Read Memory
Write
N Words

Interconnection
Address 0 Data

Data

Structures
N–1

Read I/O Module Internal

Write Data

External
Address M Ports Data

Internal
Data Interrupt
Signals
External
Data

Instructions Address

Control
Data CPU Signals

Interrupt Data
Signals

Figure 3.15 Computer Modules

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 The interconnection structure must support
the following types of transfers:
Memory Processor I/O to or
I/O to Processor
to to from
processor to I/O
processor memory memory

An I/O
module is
allowed to
Processor Processor exchange
Processor data
reads an reads data Processor
writes a directly
instruction from an sends data
unit of with
or a unit of I/O device to the I/O memory
data to
data from via an I/O device without
memory
memory module going
through the
processor
using DMA

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A bus is a communication Signals transmitted by any one
pathway connecting two or device are available for reception
more devices: by all other devices attached to the
bus;
• Key characteristic is that
it is a shared • If two devices transmit during the
transmission medium same time period their signals
will overlap and become garbled
Bus
Interco-
Typically consists of nnection
multiple communication Computer systems contain
lines: a number of different buses
that provide pathways
• Each line is capable of between components at
transmitting signals various levels of the
representing binary 1 computer system hierarchy
and binary 0

System bus: The most common

• A bus that connects computer
major computer interconnection
components structures are based on
(processor, memory, the use of one or more
I/O) system buses

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 Data Bus
 Data lines that provide a path for moving data
among system modules;
 These lines, collectively, are called the data bus.
 May consist of 32, 64, 128, or more separate lines;
 The number of lines is referred to as the width of
the data bus;
 The number of lines determines how many bits
can be transferred at a time;
 The width of the data bus
is a key factor in
determining overall
system performance;

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+ Address Bus Control Bus

 Used to designate the source or  Used to control the access and the use
destination of the data on the data of the data and address lines;
bus;
 If the processor wishes to read
 Because the data and address lines are
a word of data from memory it shared by all components there must
puts the address of the desired be a means of controlling their use;
word on the address lines.  Control signals transmit both
 Width determines the maximum command and timing information
possible memory capacity of the among system modules;
system  Timing signals indicate the validity of
 Also used to address I/O ports data and address information.
 The higher order bits are used  Command signals specify operations
to select a particular module to be performed.
on the bus, and
 Typical control lines include:
 the lower order bits select a
memory location or I/O port  Memory Write & Read, I/O write &
within the module Read, Transfer ACK, Bus Request &
Grant, Interrupt request & ACK,
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. Clock, and Reset.
 CPU Memory Memory I/O I/O

Control lines

Address lines Bus

Data lines

Figure 3.16 Bus Interconnection Scheme

 How dos an operation of the bus:

 If one module wishes to send data to another?
 If one module wishes to request data from another module?

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+
Point-to-Point Interconnect
Principal reason for At higher and higher data
change was the rates it becomes
electrical constraints increasingly difficult to
encountered with perform the
increasing the synchronization and
frequency of wide arbitration functions in a
synchronous buses timely fashion

A conventional shared bus on

point-to-point
the same chip magnified the
interconnection has
difficulties of increasing bus
lower latency, higher
data rate and reducing bus
data rate, and better
latency to keep up with the
scalability
processors
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 +Quick Path Interconnect
QPI
 Introduced in 2008;
 Multiple direct connections;
 Direct pairwise connections to other compo-
nents eliminating the need for arbitration
found in shared transmission systems.
 Layered protocol architecture;
 These processor-level interconnects use a
layered protocol architecture rather than the
simple use of control signals found in shared
bus arrangements.
 Packetized data transfer
 Data are sent as a sequence of packets each
of which includes control headers and error
control codes.
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 I/O device

I/O device
I/O Hub

DRAM

DRAM
Core Core
A B

DRAM

DRAM
Core Core
C D
I/O device

I/O device
I/O Hub

QPI PCI Express Memory bus

Figure 3.17 Multicore Configuration Using QPI

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  The high-level set of rules
Packets for exchanging packets of
Protocol Protocol data between devices.
 A packet is included of an
integral number of Flits.

Routing Routing
Provides the framework for
directing packets through
Flits the fabric.
Link Link

Responsible for;
Physical Phits Physical  reliable transmission and
flow control.
 unit of transfer is an 80-
bit Flit (flow control unit).

Figure 3.18 QPI Layers Consists of the;

 actual wires carrying the signals,
 circuitry and logic to support ancillary
features required in the transmission and
receipt of the 1s & 0s.
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 unit of transfer is an 20-bit Phit.
 COMPONENT A
Intel QuickPath Interconnect Port

Fwd Clk

Rcv Clk
Transmission Lanes Reception Lanes

Fwd Clk
Rcv Clk

Reception Lanes Transmission Lanes

Intel QuickPath Interconnect Port

COMPONENT B

Figure 3.19 Physical Interface of the Intel QPI Interconnect

• Speeds of the link 6.4 GT/s (transfers per second);

 At 20 bits per transfer, that adds up to 16 GB/s
 #2n+1 #n+1 #1 QPI
lane 0

bit stream of flits #2n+2 #n+2 #2 QPI

lane 1

#2n+1 #2n #n+2 #n+1 #n #2 #1

#3n #2n #n QPI

lane 19

Figure 3.20 QPI Multilane Distribution

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+
QPI Link Layer
 Performs two key  Flow control function:
functions: flow  Needed to ensure that a
control and error sending QPI entity does not
control; overwhelm a receiving QPI
 Operate on the level of entity by sending data faster
the flit (flow control than the receiver can process
unit)
the data and clear buffers for
 Each flit consists of: more incoming data.
 a 72-bit message
payload and
 Error control function:
 an 8-bit error
 Detects and recovers
control code called
from bit errors, and
a cyclic redundancy
check (CRC)  so isolates higher layers
from experiencing bit
errors.
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+ QPI Routing and Protocol Layers

Routing Layer Protocol Layer

 Used to determine the  Packet is defined as the unit
course that a packet of transfer;
will traverse across the  One key function performed
available system at this level is a cache
interconnects; coherency protocol;
 Routing tables are  which deals with making sure
defined by firmware that main memory values
and describe the held in multiple caches are
possible paths that a consistent.
packet can follow; A typical data packet payload
is a block of data being sent
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to or from a cache;
+ Peripheral Component
Interconnect (PCI)
 A popular high-bandwidth;
 processor independent bus that can function as a mezzanine or
peripheral bus.
 Delivers better system performance for high speed I/O
subsystems;
 e.g., graphic display adapters, network interface controllers, and disk
controllers.
 PCI Special Interest Group (SIG);
 Created to develop further and maintain the compatibility of the PCI
specifications.
 PCI Express (PCIe);
 Is a Point-to-point interconnect scheme intended to replace bus-based
schemes such as PCI,
 Key requirement is high capacity to support the needs of higher data
rate I/O devices, such as Gigabit Ethernet,
 Another requirement deals with the need to support time dependent
data streams.
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 Core Core

Gigabit PCIe
Memory
Ethernet
Chipset
PCIe–PCI PCIe
Memory
Bridge

PCIe

PCIe PCIe
Switch

PCIe PCIe

Legacy PCIe PCIe PCIe

endpoint endpoint endpoint endpoint

Figure 3.21 Typical Configuration Using PCIe

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 Transaction layer
packets (TLP)
Transaction Transaction

Data link layer

packets (DLLP)
Data Link Data Link

Physical Physical

Figure 3.22 PCIe Protocol Layers

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 B4 B0 128b/ PCIe
130b lane 0
byte stream

B5 B1 128b/ PCIe
130b lane 1
B7 B6 B5 B4 B3 B2 B1 B0

B6 B2 128b/ PCIe
130b lane 2

B7 B3 128b/ PCIe
130b lane 3

Figure 3.23 PCIe Multilane Distribution

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 D+ D–
8b

Differential
Scrambler Receiver

8b 1b Clock recovery
circuit

Data recovery
128b/130b Encoding circuit

130b 1b

Parallel to serial Serial to parallel

1b 130b

Transmitter Differential
128b/130b Decoding
Driver

128b

D+ D–
Descrambler
(a) Transmitter
8b

(b) Receiver

Figure 3.24 PCIe Transmit and Receive Block Diagrams

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 Receives read and write requests from
+ 
the software above the TL and creates
request packets for transmission to a
destination via the link layer;

PCIe  Most transactions use a split transaction

technique;
Transaction Layer (TL)  A request packet is sent out by a
source PCIe device which then waits
for a response called a completion
packet.
 TL messages and some write
transactions are posted transactions
(meaning that no response is
expected);

 TL packet format supports 32-bit

memory addressing and extended
64-bit memory addressing;

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+
The transaction layer (TL) supports
four address spaces:
 Memory  I/O
 The memory space includes  This address space is used
system main memory and
for legacy PCI devices,
PCIe I/O devices
with reserved address
 Certain ranges of memory
ranges used to address
addresses map into I/O
devices. legacy I/O devices

 Configuration  Message
 This address space  This address space is for
enables the TL to control signals related to
read/write configuration interrupts, error handling,
registers associated with and power management
I/O devices

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 Table 3.2
PCIe TLP Transaction Types
Address Space TLP Type Purpose
Memory Read Request
Transfer data to or from a location in the
Memory Memory Read Lock Request system memory map.
Memory Write Request
I/O Read Request Transfer data to or from a location in the
I/O
I/O Write Request system memory map for legacy devices.
Config Type 0 Read Request
Config Type 0 Write Request Transfer data to or from a location in the
Configuration
Config Type 1 Read Request configuration space of a PCIe device.
Config Type 1 Write Request
Message Request Provides in-band messaging and event
Message reporting.
Message Request with Data
Completion
Memory, I/O, Completion with Data
Returned for certain requests.
Configuration Completion Locked
Completion Locked with Data
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 Number
of octets
1 STP framing 1 Start

Appended by PL
2 Sequence number
DLLP

Created
by DLL
4

2 CRC

12 or 16 Header 1 End

Created by Transaction Layer

Appended by Data Link Layer

Appended by Physical Layer

0 to 4096 Data

0 or 4 ECRC

4 LCRC

1 STP framing

(a) Transaction Layer Packet (b) Data Link Layer Packet

Figure 3.25 PCIe Protocol Data Unit Format

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+ Summary A Top-Level View of
Computer Function
and Interconnection
Chapter 3
 Point-to-point interconnect
 QPI physical layer
 Computer components
 QPI link layer
 Computer function
 QPI routing layer
 Instruction fetch and
execute  QPI protocol layer
 Interrupts  PCI express
 I/O function  PCI physical and logical
 Interconnection structures architecture
 Bus interconnection  PCIe physical layer
 PCIe transaction layer
 PCIe data link layer
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