ECEN689: Special Topics in High-Speed

Links Circuits and Systems

Lecture 18: RX FIR & CTLE Equalization

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements
• HW5 now due Friday (in class)
• Any issues?

• Reading
• Hanumolu equalization overview paper

2
Agenda
• RX FIR Equalization

• RX CTLE Equalization

3
 Link with Equalization

TX FIR RX CTLE + DFE

Deserializer
Channel
Serializer

Σ
DTX[N:0] DRX[N:0]

TX Clk f RX Clk
Generation Recovery
(PLL) (CDR/Fwd Clk)

4
 TX FIR Equalization
• TX FIR filter pre-distorts transmitted pulse in order to invert channel
distortion at the cost of attenuated transmit signal (de-emphasis)
w-1

TX
z-1 w0
data

z-1 w1

z-1 w2

z-1 wn

5
RX FIR Equalization
• Delay analog input signal and
multiply by equalization
coefficients
• Pros
• With sufficient dynamic range, can
amplify high frequency content
(rather than attenuate low
frequencies)
• Can cancel ISI in pre-cursor and
beyond filter span
• Filter tap coefficients can be
adaptively tuned without any
back-channel
• Cons [Hall]
• Amplifies noise/crosstalk
• Implementation of analog delays
• Tap precision
6
RX Equalization Noise Enhancement
• Linear RX equalizers don’t discriminate between
signal, noise, and cross-talk
• While signal-to-distortion (ISI) ratio is improved, SNR
remains unchanged

[Hall]

7
Analog RX FIR Equalization Example
• 5-tap equalizer with tap spacing of Tb/2
3rd-order delay cell

1Gb/s experimental results

D. Hernandez-Garduno and J. Silva-Martinez, “A CMOS 1Gb/s 5-Tap Transversal Equalizer based on 3rd-Order Delay Cells,"
ISSCC, 2007. 8
Digital RX FIR Equalization
• Digitize the input signal with high-speed low/medium
resolution ADC and perform equalization in digital domain
• Digital delays, multipliers, adders
• Limited to ADC resolution
• Power can be high due to very fast ADC

[Hanumolu]

9
Digital RX FIR Equalization Example

• 12.5GS/s 4.5-bit Flash ADC in 65nm CMOS [Harwood ISSCC 2007]

• Cancel both precursor and long-tail

• Can be purely passive or combined

Passive CTLE Active CTLE

Vo+ Vo-

Din- Din+
[Hanumolu]

11
Passive CTLE
• Passive structures offer excellent linearity,
but no gain at Nyquist frequency

1 + R1C1s
H (s ) =
R2
R1 + R2 1 + R1 R2 (C + C )s
R1 + R2
1 2

1 1
ωz = , ωp =
R1C1 R1 R2
(C1 + C2 )
R1 + R2
R2 C1
[Hanumolu] DC gain = , HF gain =
R1 + R2 C1 + C2
HF gain ω p R1 + R2 C1
Peaking = = =
DC gain ω z R2 C1 + C2

12
Active CTLE
• Input amplifier with RC [Gondi JSSC 2007]
degeneration can provide
frequency peaking with gain
at Nyquist frequency
• Potentially limited by gain-
bandwidth of amplifier
1
s+
• Amplifier must be designed H (s ) = m
g RS CS
for input linear range C p  1 + g m RS 2 
 s +  s +
1 
 RS CS  RD C p 
• Often TX eq. provides some
1 + g m RS 2
low frequency attenuation ωz =
1
, ωp1 = , ωp2 =
1
RS CS RS CS RD C p
• Sensitive to PVT variations g m RD
DC gain = , Ideal peak gain = g m RD
and can be hard to tune 1 + g m RS 2
Ideal peak gain ω p1
• Generally limited to 1st-order Ideal Peaking =
DC gain
=
ωz
= 1 + g m RS 2

compensation 13
Active CTLE Example

Vo+ Vo-

Din- Din+

14
Active CTLE Tuning
• Tune degeneration resistor and capacitor
to adjust zero frequency and 1st pole which
sets peaking and DC gain
CS

1 1 + g m RS 2
ωz = , ωp1 =
RS CS RS CS

RS

15
Next Time
• RX DFE
• Alternate/Future Approaches

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