DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

ANALOG AND DIGITAL ELECTRONICS LABORATORY

18CSL37

Prepared by
Prof. SURESH P, Asst. Prof, Dept. of CSE
Prof. VENKATAGIRI J, Asst. Prof, Dept. of CSE
Prof. DIVYARAJ G N, Asst. Prof, Dept. of CSE
Department vision:
To be a school of Excellence in Computing for Holistic Education and Research

Department Mission:
Mission1:
Strive for academic excellence in Computer Science and Engineering through student centric innovative
teaching learning process, competent faculty members, efficient assessment and effective use of ICT.
Mission 2:
Establish Centre for Excellence in various vertical of Computer Science and Engineering to promote
collaborative research and Industry Institute Interaction.
Mission 3:
Transform the engineering aspirants to socially responsible, ethical, technically competent and value added
professional or entrepreneur.

Program Educational Objectives

Knowledge

Computer Science and Engineering Graduates will have professional technical career in inter disciplinary
domains providing innovative and sustainable solutions using modern tools.

Skills

Computer Science and Engineering Graduates will have effective communication, leadership, team building,
problem solving, decision making and creative skills.

Attitude

Computer Science and Engineering Graduates will practice ethical responsibilities towards their peers,
employers and society.

Program Specific Outcomes

PSO 1
Ability to adopt quickly for any domain, interact with diverse group of individuals and be an entrepreneur in
a societal and global setting.

PSO 2
Ability to visualize the operations of existing and future software Applications.
Program Outcomes:

1. Engineering Knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and
an engineering specialization to the solution of complex engineering problems.

2. Problem Analysis: Identify, formulate, research literature, and analyze complex engineering problems
reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering
sciences

3. Design/development of Solutions: Design solutions for complex engineering problems and design system
components or processes that meet t h e specified needs with appropriate consideration for the public health
and safety, and the cultural, societal, and environmental considerations.

4. Conduct Investigations of Complex Problems: Use research-based knowledge and research methods
including design of experiments, analysis and interpretation of data, and synthesis of the information to
provide valid conclusions.

5. Modern Tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering
and IT tools including prediction and modeling to complex engineering activities with an understanding of
the limitations.

6. The Engineer and Society: Apply reasoning informed by the contextual knowledge to assess societal,
health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional
engineering practice.

7. Environment and Sustainability: Understand the impact of the professional engineering solutions in
societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable
development.

8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
engineering practice.

9. Individual and Team Work: Function effectively as an individual, and as a member or leader in diverse
teams, and in multidisciplinary settings.

10. Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear instructions.

11. Project Management and Finance: Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one’s own work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.

12. Life-long Learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
 List of Experiments
Hours/Week: 03 Exam Hours: 03
CIE Marks: 40 Total Hours: 36
Semester: 3 SEE Marks: 100

Sl. No. PART A (Analog Electronic Circuits) Page No.

Design an astable multivibrator circuit for three cases of duty cycle 1
1. (50%, <50% and >50%) using NE 555 timer IC. Simulate the same for
any one duty cycle.
2. Using ua 741 Opamp, design a 1 kHz relaxation oscillator with 50% 5
duty cycle. And simulate the same.
3. Using ua 741 Opamp, design window comparator for any given UTP 8
and LTP. And simulate the same.
PART B (Digital Electronic Circuits)
4. Design and implement Half adder, Full Adder, Half Subtractor, Full 10
Subtractor using basic gates. And implement the same in HDL.
5. Given any 4-variable logic expression, simplify it using appropriate 16
technique and realize the simplified logic expression using 8:1
multiplexer IC. And implement the same in HDL.
6. Realize a J-K Master/Slave Flip-Flop using NAND gates and verify 19
its truth table. And implement the same in HDL.
7. Design and implement code converter I) Binary to Gray (II) Gray to 22
Binary Code using basic gates.
8. Design and implement a mod-n (n<8) synchronous up counter using 28
J-K Flip-Flop ICs & demonstrate its working.
9. Design and implement an asynchronous counter using decade counter 32
IC to count up from 0 to n (n<=9) and demonstrate on 7 segment
display (using IC 7447).

Conduct of Practical Examination:

Experiment distribution
 For laboratories having only one part: Students are allowed to pick one
experiment from the lot with equal opportunity.
 For laboratories having PART A and PART B: Students are allowed to pick
one experiment from PART A and one experiment from PART B, with equal
opportunity.
 Change of experiment is allowed only once and marks allotted for procedure
to be made zero of the changed part only.
 Marks Distribution (Subjected to change in accordance with university
regulations)
a) For laboratories having only one part – Procedure + Execution +
Viva-Voce: 15+70+15 = 100 Marks
b) For laboratories having PART A and PART B
i. Part A – Procedure + Execution + Viva = 6 + 28 + 6 = 40
Marks
ii. Part B – Procedure + Execution + Viva = 9 + 42 + 9 = 60
Mark
Resistor value finder
 Cathode Ray Oscilloscope
An oscilloscope is a test instrument which allows us to look at the 'shape' of electrical signals
by displaying a graph of voltage against time on its screen. It is like a voltmeter with the
valuable extra function of showing how the voltage varies with time. A graticule with a 1cm
grid enables us to take measurements of voltage and time from the screen.

The graph, usually called the trace, is drawn by a beam of electrons striking the phosphor
coating of the screen making it emit light, usually green or blue. This is similar to the way a
television picture is produced.

Oscilloscopes contain a vacuum tube with a cathode (negative electrode) at one end to emit
electrons and an anode (positive electrode) to accelerate them so they move rapidly down the
tube to the screen. This arrangement is called an electron gun. The tube also contains
electrodes to deflect the electron beam up/down and left/right.

The electrons are called cathode rays because they are emitted by the cathode and this gives
the oscilloscope its full name of cathode ray oscilloscope or CRO. A dual trace oscilloscope
can display two traces on the screen, allowing us to easily compare the input and output of an
amplifier for example. It is well worth paying the modest extra cost to have this facility.

Setting up an oscilloscope:

Oscilloscopes are complex instruments with many controls and they require some care to set
up and use successfully. It is quite easy to 'lose' the trace off the screen if controls are set
wrongly.

There is some variation in the arrangement and labeling of the many controls. So, the
following instructions may be adapted for this instrument.

1. Switch on the oscilloscope to warm up (it takes a minute or two).

2. Do not connect the input lead at this stage.
3. Set the AC/GND/DC switch (by the Y INPUT) to DC.
4. Set the SWP/X-Y switch to SWP (sweep).
5. Set Trigger Level to AUTO.
6. Set Trigger Source to INT (internal, the y input).
7. Set the Y AMPLIFIER to 5V/cm (a moderate value).
8. Set the TIMEBASE to 10ms/cm (a moderate speed).
9. Turn the time base VARIABLE control to 1 or CAL.
10. Adjust Y SHIFT (up/down) and X SHIFT (left/right) to give a trace across the middle
of the screen, like the picture.
11. Adjust INTENSITY (brightness) and FOCUS to give a bright, sharp trace.

Connecting an oscilloscope:
The Y INPUT lead to an oscilloscope should be a co-axial lead and the figure 4 shows its
construction. The central wire carries the signal and the screen is connected to earth (0V)to
shield the signal from electrical interference (usually called noise).

Most oscilloscopes have a BNC socket for the y input and the lead is connected with a push
and twist action, to disconnect we need to twist and pull. Professionals use a specially
designed lead and probes kit for best results with high frequency signals and when testing
high resistance circuits, but this is not essential for simpler work at audio frequencies (up to
20 kHz).

Obtaining a clear and stable trace:

Once if we connect the oscilloscope to the circuit, it is necessary to adjust the controls to
obtain a clear and stable trace on the screen in order to test it.

 The Y AMPLIFIER (VOLTS/CM)

control determines the height of the trace.
Choose a setting so the trace occupies at least
half the screen height, but does not disappear
off the screen.
 The TIMEBASE (TIME/CM) control
determines the rate at which the dot sweeps
across the screen. Choose a setting so the
trace shows at least one cycle of the signal across the screen. Steady DC input signal gives a horizontal
line trace for which the time base setting is not critical.
 The TRIGGER control is usually best left set to AUTO.
 The trace of an AC signal with the oscilloscope controls correctly set is as shown in
Figure

Measuring voltage and time period:

The trace on an oscilloscope screen is a
graph of voltage against time. The shape of
this graph is determined by the nature of the
input signal. In addition to the properties
labeled on the graph, there is frequency
which is the number of cycles per second.
The diagram shows a sine wave but these
properties apply to any signal with a
constant shape.
 Amplitude is the maximum voltage reached by the signal. It is measured in volts.
 Peak voltage is another name for amplitude.
 Peak-peak voltage is twice the peak voltage (amplitude). When reading an
oscilloscope trace it is usual to measure peak-peak voltage.
 Time period is the time taken for the signal to complete one cycle. It is measured in
seconds (s), but time periods tend to be short so milliseconds (ms) and microseconds (μs) are
often used. 1ms = 0.001s and 1μs = 0.000001s. Time period = 1/ Frequency
 Frequency is the number of cycles per second. It is measured in hertz (Hz), but
frequencies tend to be high so kilohertz (kHz) and megahertz (MHz) are often used. 1kHz =
1000Hz and 1MHz = 1000000Hz. Frequency = 1 / Time period

Measuring Voltage: Voltage is shown on the vertical y-axis and the scale is determined by
the Y AMPLIFIER (VOLTS/CM) control. Usually peak-peak voltage is measured because it
can be read correctly even if the position of 0V is not known. The amplitude is half the peak-
peak voltage. Voltage = distance in cm × volts/cm

Measuring Time period: Time is shown on the horizontal x-axis and the scale is determined
by
the TIMEBASE (TIME/CM) control. The time period (often just called period) is the time for
one cycle of the signal. The frequency is the number of cycles per second, frequency = 1/time
period.
Time = distance in cm × time/cm
 Function Generator
A function generator is a device that can produce various patterns of voltage at a variety of
frequencies and amplitudes. It is used to test the response of circuits to common input signals.
The electrical leads from the device are attached to the ground and signal input terminals of
the device under test.

General function
generators can be used to
generate the following
waveforms:
- Sinusoidal
-Square
- Triangular
- Pulse

Setting the values on the function generator:

 Double click on the function generator to open the function generator panel.
 Select the waveform of your choice by clicking on the waveform selector buttons.
 Select the property associated with the waveform such as frequency, amplitude or offset
etc. by clicking on the waveform property selector button.
 Use the arrow keys to move the cursor to the desired position
 Use the number pad to change the value or alternatively you can use the knob
 After changing one property, move on to the next property

Note:
After changing properties of a waveform (e.g. frequency, amplitude of Sine), if you wish to
select other waveform (e.g. Square), will set all the properties of Sine to their default values.
Generating Sine wave:
 Click the sine button.
 Click and select frequency, change it to the desired value
 Similarly, change amplitude, offset and phase
Generating Square wave:
 Click the square button.
 Click and select frequency, change the value to the desired value
 Similarly, change amplitude, duty cycle and phase

Generating a pulse train:

 Click the pulse button
 Click and select amplitude, change the value to the desired value
 Similarly, change other parameters as well.
The amplitude control on a function generator varies the voltage difference between the high
and low voltage of the output signal. The direct current (DC) offset control on a function
generator varies the average voltage of a signal relative to the ground.

The frequency control of a function generator controls the rate at which output signal
oscillates. On some function generators, the frequency control is a combination of different
controls. One set of controls chooses the broad frequency range (order of magnitude) and the
other selects the precise frequency. This allows the function generator to handle the enormous
variation in frequency scale needed for signals.
 Breadboards
A breadboard is a solder less device for temporary prototype with electronics and test circuit
designs. Most electronic components in electronic circuits can be interconnected by inserting
their leads or terminals into the holes and then making connections through wires where
appropriate. The breadboard has strips of metal underneath the board and connect the holes
on the top of the board. The metal strips are laid out as shown below. Note that the top and
bottom rows of holes are connected horizontally and split in the middle while the remaining
holes are connected vertically.

Note how all holes in the selected row are connected together, so the holes in the selected
column. The set of connected holes can be called a node:

To interconnect the selected row (node A) and column (node B) a cable going from any hole
in the row to any hole in the column is needed:
Now the selected column (node B) and row (node A) are interconnected:
 PSpice simulator tool

In order to ensure a successful circuit design and mitigate costly and potentially dangerous
design flaws, careful planning and evaluation must occur at every stage of the circuit design
process. Circuit simulation provides a cost-effective and efficient method for identifying
faults before moving to the more expensive and time-consuming prototyping stage. Including
simulation in the design process reduces design errors and speeds the design cycle by allowing
you to predict and better understand circuit behavior. The main purpose of simulation is to
predict and understand the behavior of electronic circuits. PSpice is a program that simulates
electronic circuits on your PC.

Limitations of simulation:
While a prototype helps you to verify and validate your design in the real world, simulation
helps you catch design errors before spending money and time on prototyping.

Orcad 9.2 Lite Edition Installation:

1. Insert Cadence CD into CD-ROM drive
2. Select Products to install
 Capture – Schematic entry application – it must be installed
 Capture CIS – Should be grayed out.
 PSpice – For conducting mixed-signal analog and digital simulations
 Layout– For creating PC Board layouts from schematics
Then follow the instructions as it appears on the monitor and complete the installation
The steps to simulation:
1. Create a simulation project
2. Draw schematic to simulate
3. Establish a simulation profile
4. Set up simulation type
5. Simulate circuit
6. Analyze results in Probe
General procedure for all experiments:
1. Select the required components from the menu.
2. Place all the required components in the schematic.
3. Simulate the circuit using RUN option from the menu.
4. Observe the waveforms form the output

To start a simulation session:

1. On the start menu select ORCAD
FAMILY RELEASE 9.2 LITE
EDITION - CAPTURE LITE
EDITION
2. Once the capture window appears,
select FILE - NEW – PROJECT. The
following window appears:

3. Give the project a descriptive name

(spaces can be included).
4. Select ANALOG OR MIXED-
SIGNAL CIRCUIT WIZARD.
5. Specify a location where the project is to be stored
6. Click OK.
The following window appears:

7. Select Create a blank project and click OK. The following window appears:

8. To place parts, click PLACE PART (Shift+P). Then

the following window appears:
If Libraries are not appearing in the window then click
Add Library. The library files will generally be
available in the following path by default.
C:\Program Files\Orcad_Demo \Capture \
Library\Pspice. Select all Library files by pressing
Ctrl A and then press Open. All the
Library files will appear in the window.
9. Select the part you wish to place in the schematic. Insert as many as needed

10. Right Click and select END MODE to stop inserting parts

11. To wire parts together, click Place Wire Icon from the Right hand side vertical Icons list
(Shift+W). Place cursor over boxes at ends of parts and draw wires connecting parts. When
done, right click and select End Wire.

12. To insert a ground node, click Place – Ground Icon. Window appears with caption
Place Ground with only ground nodes available for selection.
Always select 0/SOURCE for the ground node of an analog circuit – every analog circuit
must contain at least one 0 ground. This is not a requirement for digital circuits.
13. To change component values that are displayed. Double click the displayed value·
Change the desired value in the dialog box that appears.

To set up a simulation profile:

1. Select PSPICE ---NEW SIMULATION PROFILE from the menu.
2. Give a descriptive name to the type of simulation.
3. Select the desired parameters for the particular circuit and then click OK.
4. Place voltage, current, and power markers from the PSPICE --- MARKERS menu
where needed.

5. Click PSPICE -- RUN.

 VHDL

VHDL stands for Very High Speed Integrated Circuit Hardware Description
Language. It describes the behavior of an electronic circuit or system, from which the
physical circuit or system can then be implemented.
VHDL was originally intended to serve 2 main purposes-
1. It was used as a documentation language for describing the structure of
complex digital circuits.
2. VHDL provides features for modeling the behavior of a digital circuit.

General Features of VHDL:

1. The language can be used as an exchange medium between chip vendors
and CAD tool user and can be used as communication medium between
CAD and CAE tools.
2. It supports hierarchy.
3. It is not a case sensitive language.
4. It is strongly type checked language.
5. It provides design portability and flexible design methodologies: top down,
bottom up or mixed
6. It supports both synchronous and asynchronous timing models.
7. Nominal Propagation delays, min-max delays, setup and hold timing
constraint and spike detection can be described in this language.

Usage of the Tool:

It is one of most popular software tool used to synthesize VHDL code. This tool includes
many steps. To make user feel comfortable with the tool the steps are given below:-
1. Select NEW PROJECT in FILE MENU.
a. Enter following details as per your convenience
b. Project name : sample (should be same as the entity name in
a. your VHDL code
c. Project location : C:\example( As per convenience use default
d. Top level module : HDL
2. In NEW PROJECT dropdown Dialog box, Choose your appropriate device
specification. Example is given below:
a. Device family : cyclone
b. Device : EP1C6Q240
c. Package : PQFP
d. Pincount :240
e. Speed grade 8
3. On File Drop down menu choose new Vhdl file. Type the Vhdl code Under
the Processing Drop down menu
4. Choose Start compilation
5. If there are errors go back to the VHDL code and correct it. Once the
compilation is successful
6. Under the processing drop down box select simulator tool select the
simulator mode to functional and click on generate functional simulation
netlist. we Get the success message.
 7. Under simulator tool click on open. In the empty location right click . Click
on insert on NODE or BUS. Then click on NODE finder. In the window
opened select pins to unassigned. Click on List . IT will list all the Net list
seloct all and click ok.
8. The input and output appears give appropriate input.
9. On the simulator tool click on start simulation. Simulation success message
will be prompted.
10. On simulator tool click on report to see the output.

Note:
Create a new project for every new VHDL code.
The primary data type std_logic (standard unresolved logic) consists of nine character literals in the
following order:
'U' - uninitialized
'X' - strong drive, unknown logic value
'0' - strong drive, logic zero
'1' - strong drive, logic one
'Z' - high impedance
'W' - weak drive, unknown logic value
'L' - weak drive, logic zero
'H' - weak drive, logic one
'-' - don't care
 Analog & Digital Electronics Laboratory (18CSL37) AY 2021-22

PART - A (Analog Electronic Circuits)

Experiment No.1: Design an astable multivibrator circuit for three cases of duty cycle
(50%, <50% and >50%) using NE 555 timer IC. Simulate the same for any one duty
cycle.

Description:
Multivibrator is a form of oscillator, which has a non-sinusoidal output. The output
waveform is rectangular. The multivibrators are classified as
i) Astable or free running multivibrator
It alternates automatically between two states (low and high for a rectangular
output) and remains in each state for a time dependent upon the circuit constants.
It is just an oscillator as it requires no external pulse for its operation.
ii) Monostable or one shot multivibrators:
It has one stable state and one quasi stable. The application of an input pulse
triggers the circuit time constants and the output goes to the quazi stable state,
after a period of time determined by the time constant, the circuit returns to its
initial stable state. The process is repeated upon the application of each trigger
pulse.
iii) Bistable Multivibrators:
It has both stable states. It requires the application of an external triggering pulse
to change the output from one state to other. After the output has changed its
state, it remains in that state until the application of next trigger pulse. Flip flop
is an example.

Equipment / Components Required:

1. 555 Timer IC – 1
2. Resistors - As required according to the Design
3. 0.1µF Capacitor - 1
4. 0.01µF Capacitor - 1
5. DC Regulated Power Supply – 1
6. Signal generator – 1
7. CRO – 1
8. CRO Probes – 2
9. Wires – As required

Procedure:

1. Before making the connections, check the components using multimeter.

2. Make the connections as shown in the above circuit diagrams and switch on the
power supply.
3. Observe the capacitor voltage waveform at 6th pin of 555 timer on CRO.
4. Observe the output waveform at 3rd pin of 555 timer on CRO.
5. Note down the amplitude levels, time period and hence calculate duty cycle.
6. Connect the pin 2 or Pin 6 to the CRO to get the capacitor waveform check the
amplitude from the waveform to get the UTP and LTP values.

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7. Connect pin 3 to CRO to get the output. Find out the TH and TL values.

555 Timer Pin Diagram:-

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Design 1: For 50% Duty Cycle

TH = 0.693 (RA+RB) C ------------ 1

TL=0.693RBC ------------- 2

Let Frequency =1kHz, T=1ms, C=0.1 μF

Duty Cycle = TH/T
0.5 = TH/T
TH = 0.5 * T =0.5*1*10-3
TH=0.5ms
T = TL + TH
1ms = TL + 0.5ms
TL = 0.5ms
TH = TL=0.5ms

For RA, In Equation 1, Substitute

0.5ms= 0.693 * RA *0.1 *10-6
RA =7.2 kΩ

For RB, In Equation 2,

Substitute
RB = TL/(0.693*C)
= (0.5*10-3)/(0.693*0.1*10-6)
RB = 7.2KΩ

Circuit Diagram for Astable Multivibrator:

Figure 1.1: astable mutivibrator

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Design 2: For 60% Duty Cycle

Let Frequency =2kHz, T=0.5ms

Duty Cycle = TH/T
0.6 = TH/T
TH = 0.6 * T =0.6*0.5*10-3
TH=0.3ms
T = TL + TH
0.5*10-3 = TL + 0.3*10-3
TL=0.2ms

Let C=0.1 μF
TH = 0.693 (RA+RB) C ------------ 1
TL=0.693RBC ------------- 2

For RB, In Equation 2,

Substitute
RB = TL/(0.693*C)
= (0.2*10-3)/(0.693*0.1*10-6)
RB = 2.9KΩ

For RA, In Equation 1, Substitute

TH = 0.693 (RA+RB) C
0.3*10-3 = 0.693 ( RA+ 2.9 * 103 ) 0.1*10-6
RA=1.4KΩ

Circuit Diagram for Astable Multivibrator:

Figure 1.2: astable mutivibrator

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Design 3: For 90% Duty Cycle

Let Frequency =500Hz, T=0.002s

Duty Cycle = TH/T
0.9 = TH/T
TH = 0.9 * T =0.9*0.002
TH=0.0018s
T = TL + TH
0.002 = TL + 0.0018
TL=0.0002s

Let C=0.1 μF

TH = 0.693 (RA+RB) C ------------ 1

TL=0.693RBC ------------- 2

For RB, In Equation 2,

Substitute
RB = TL/(0.693*C)
= (0.0002)/(0.693*0.1*10-6)
RB = 2.9KΩ

For RA, In Equation 1, Substitute

TH = 0.693 (RA+RB) C
0.0018 = 0.693 ( RA+ 2.9 * 103 ) 0.1*10-6
RA=23.1KΩ

Circuit Diagram for Astable Multivibrator:

Figure 1.3: astable mutivibrator

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Design 4: For 25% Duty Cycle

Let Frequency =1kHz, T=1ms, C=0.1 μF

TH = 0.25ms TL= 0.75ms

For RA, 0.25ms= 0.693 * RA *0.1 *10-6
RA =3.6 kΩ

For RB, 0.75ms= 0.693 * RA *0.1 *10-6

RB =10 kΩ

Circuit Diagram for Astable Multivibrator:

Figure 1.4: astable mutivibrator

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Output waveforms:
For design1:

Figure 1.5: astable multivibrator output waveforms

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Result:

Note:

Each division in oscilloscope is 0.2 Time=no of div in x-axis x time base Amplitude= no
of div in y-axis x volt/div Duty cycle= (TH/TH +TL) *100

Duty cycle Duty cycle Frequency TL TH

Theoretical 50% 1kHZ 0.5ms 0.5ms
60% 2kHZ 0.2ms 0.3ms
90% 500HZ 0.0002ms 0.0018ms
25% 1kHZ 0.25ms 0.75ms
Practical 50%
60%
90%
25%

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Simulation: Circuit diagram: Astable Multivibrator for duty cycle >50%

1. Start Orcad and Create new project by clicking File  New  Project  Enter
the Project Name and Select Analog or Mixed A/D
2. By clicking Place  Part, select the following Components

Part Library Quantity

555 D Eval 1
Resistors Analog 3
Capacitor Analog 2
VDC Source 1
0/CAPSYM Place Ground 3

3. Connect all the components using Wires.

4. Set the values of the component.
5. Place the probes at the input and output terminal of the circuit.
6. Then click on Save
7. Create a new simulation profile with Analysis type: Time domain (Transient), Run
to Time: 10ms
8. Save and Run the simulation.
9. Observe the waveform and note down.

Figure 1.6: astable multivibrator

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Output waveform:

RESULT & CONCLUSION:

1) An astable multivibrator of given duty cycle and frequency is designed and

implemented.
2) An astable multivibrator of given duty cycle and frequency is simulated using PSpice.

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 Analog & Digital Electronics Laboratory (18CSL37) AY 2021-22

Experiment No.2: Using µa 741 Opamp, design a 1 kHz relaxation oscillator with
50% duty cycle. And simulate the same.

Description:

Op-Amp Relaxation Oscillator is a simple Square wave generator which is also called as a
Free running oscillator or Astable multivibrator or Relaxation oscillator. In this figure the
op-amp operates in the saturation region. Here, a fraction (R1/ (R1+R2)) of output is fed
back to the non-inverting input terminal. Thus reference voltage is (R1/ (R1+R2)) Vo. And
may take values as + (R1/ (R1+R2)) Vsat or - (R1/ (R1+R2)) Vsat. The output is also fed
back to the inverting input terminal after integrating by means of a low-pass RC
combination. Thus whenever the voltage at inverting input terminal just exceeds reference
voltage, switching takes place resulting in a square wave output.

Equipment / Components Required:

1. µA741 OPAMP – 1
2. Resistors - As required according to the Design
3. 0.1µF Capacitor - 1
4. 0.01µF Capacitor - 1
5. DC Regulated Power Supply – 1
6. Signal generator – 1
7. Potentiometer - 1
8. CRO – 1
9. CRO Probes – 2
10. Wires – As required
Procedure:
1. Before making the connections check all the components using multimeter.
2. Make the connections as shown in the figure and switch on the power
supply.
3. Place the CRO probe Clips at the input and output terminals of the circuit.
2. Observe the voltage waveform across the capacitor on CRO.
3. Also observe the output waveform on CRO. Measure its amplitude and
frequency.

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µa741 OPAMP PIN Diagram:

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Design 1: For Frequency = 1kHZ, Duty Cycle = 50%

The period of the output rectangular wave is given as T =2RC ln (1+β/1- β )-------- 1
Where,
β =R1/R1+ R2 is the feedback fraction
If R1 = R2, then from equation (1)
we have T = 2RC ln(3)------2
Design for a frequency of 1 kHz (implies T =1ms) Let C=0.1μF
Then calculating R as
R =T/2 Cln(3)
=1*10-3/2*0.1*10-6 * 1.099
= 5*103
R = 5K

Select R=4.7KΩ
The voltage across the capacitor has a peak voltage of Vc = (R1/R1+ R2) Vsat

Circuit Diagram:

Figure 2.1: Circuit diagram for relaxation oscillator using µa 741 OPAMP

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Design 2: For Frequency = 2kHZ, Duty Cycle = 50%

The period of the output rectangular wave is given as T =2RC ln (1+β/1- β )-------- 1
Where,
β =R1/R1+ R2 is the feedback fraction
If R1 = R2, then from equation (1)
we have T = 2RC ln(3)------2
Design for a frequency of 2 kHz (implies T =0.5ms) Let C=0.01μF
Then calculating R as
R =T/2 Cln(3)
=0.5*10-3/2*0.01*10-6 * 1.099
= 0.5*10-3/0.02198*10-6
R = 23* 103

Select R=23KΩ
The voltage across the capacitor has a peak voltage of Vc = (R1/R1+ R2) Vsat

Circuit Diagram:

Figure 2.2: Circuit diagram for relaxation oscillator using µa 741 OPAMP

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Design 3: For Frequency = 1kHZ, Duty Cycle = 50%

The period of the output rectangular wave is given as T =2RC ln (1+β/1- β )-------- 1
Where,
β =R1/R1+ R2 is the feedback fraction
If R1 = R2, then from equation (1)
we have T = 2RC ln(3)------2
Design for a frequency of 1 kHz (implies T =1ms) Let C=0.01μF
Then calculating R as
R =T/2 Cln(3)
=1*10-3/2*0.01*10-6 * 1.099
= 1*10-3/0.02198*10-6
R = 46* 103

Select R=46KΩ
The voltage across the capacitor has a peak voltage of Vc = (R1/R1+ R2) Vsat

Circuit Diagram:

Figure 2.3: Circuit diagram for relaxation oscillator using µa 741 OPAMP

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Output Waveforms:

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Simulation: Circuit diagram for relaxation oscillator using µA741 OPAMP

Start Orcad and create new project by clicking File → New → Project →
Enter the Project Name and select Analog or Mixed A/D
By clicking Place → Part, select the following components
Part Library Quantity
µA741 Eval 1
Resistors Analog 3
Capacitor Analog 1
VSIN Source 1
VDC Source 2
0/CAPSYM Place Ground 3

Connect all the components using Wires.

Set the values of the component.
Place the probes at the input and output terminal of the circuit.
Then click on Save
Create a new simulation profile with Analysis type: Time domain (Transient), Run
to Time: 100ms
Save and Run the simulation.
Observe the waveform and note down.

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Waveforms from simulation

RESULT & CONCLUSION:

1) An op-amp relaxation oscillator with 1 kHz frequency 50% duty cycle is

designed and implemented.
2) An op-amp relaxation oscillator with 1 kHz frequency 50% duty cycle is simulated using
PSpice.

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Experiment No.3: Using ua 741 Opamp, design window comparator for any given
UTP and LTP. And simulate the same.

Description:

A Window Comparator is basically the inverting and the non-inverting comparators

combined into a single comparator stage. The window comparator detects input voltage
levels that are within a specific band or window of voltages, instead of indicating whether
a voltage is greater or less than some preset or fixed voltage reference point.
A window comparator will have two reference voltages implemented by a pair of
voltage comparators. One which triggers an op-amp comparator on detection of some
upper voltage threshold, VREF(UPPER) and one which triggers an op-amp comparator on
detection of a lower voltage threshold level, VREF(LOWER). Then the voltage levels between
these two upper and lower reference voltages is called the ―window‖, hence its
name.

In the voltage divider network, if we now use three equal value resistors so that R1 =
R2 = R3 = R we can create a very simple window comparator circuit as shown. Also as the
resistive values are all equal, the voltage drops across each resistor will also be equal at
one-third the supply voltage, 1/3Vcc. We can set the upper reference voltage to 2/3 Vcc and the
lower reference voltage to 1/3 Vcc. Consider the window comparator circuit below.

µa741 OPAMP PIN Diagram:

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Design 1:

 Supply Voltage: 5V Input Range: 0V – 5V

 Window Range: 1.66 V – 3.33 V

Output:
0 V to 10 V (36 V maximum)

A reference voltage, VCC, is divided down by resistors R1-R3. The two node voltages, VH
and VL, define the upper window voltage and lower window voltage, respectively. When
the input voltage is between VH and VL, the output is high, or V P. When outside the
window voltage, the output is pulled down to 0 V.
Equations (1) and (2) define VH and VL, respectively.

Solving Equations (1) and (2) for VCC, setting them equal to each other, then simplifying
yields Equation (3)

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i.e. R1 = R2

To limit the current drawn from the reference voltage source, R1 and R2 were selected as
10 KΩ
While the values of R1 and R2 are related to the ratio of the window voltages, R3
determines the voltage value. R3 is calculated in Equation (5)

In order for the output voltage to swing close to the rail, the current should be limited to less
than~4 mA.
Given a
5KΩ.
If the pull up voltage is increased, RP may have to be increased in order to obtain good
output swing to the negative rail. Notice that when the input, VIN, is between VH and
VL, the output goes to the pull-up voltage,VP.

VCC = 5V, RP = 5.1 K Ω, Vp = 10V, UTP = (2/3)VCC,

LTP=(1/3)VCC

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INPUT/OUTPUT WAVEFORMS:

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Design 2:

Circuit Diagram for Window comparator

Output waveform

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SIMULATION:

Start Orcad and create new project by clicking File → New → Project → Enter
the Project Name and select Analog or Mixed A/D.
By clicking Place → Part, select the following components

Part Library Quantity

µA741 Eval 2
Resistors Analog 7
VSIN Source 1
VDC Source 5
0/CAPSYM Place Ground 6

Connect all the components using Wires.

Set the values of the component.
Place the probes at the input and output terminal of the circuit.
Then click on Save
Create a new simulation profile with Analysis type: Time domain (Transient), Run
to Time: 100ms
Save and Run the simulation.
Observe the waveform and note down.

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SIMULATION WAVEFORM:

RESULT & CONCLUSION:

1) A window comparator is designed and implemented for any given UTP and LTP
2) A window comparator is simulated for any given UTP and LTP using PSpice

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PART - B (Digital Electronic Circuits)

Experiment No 4: Design and implement Half adder, Full Adder, Half Subtractor,
Full Subtractor using basic gates. And implement the same using HDL.

Description:

 Adder circuit is a combinational digital circuit that is used for adding numbers. A typical adder
circuit produces a sum bit (denoted by S) and a carry bit (denoted by C) as the output. Adders are
used in the arithmetic logic units, in other parts of the processor, where they are used to calculate
addresses, table indices, increment and decrement operators.

 Half-Adder: A combinational logic circuit that adds two single binary digits A and B. It has two
outputs, sum (S) and carry (C). The carry signal represents an overflow into the next digit of a
multi-digit addition.

 Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This carry
bit from its previous stage is called carry-in bit (Cin). A combinational logic circuit that adds two
data bits A, B, and a carry-in bit Cin, is called a full-adder. It has two outputs, sum (S) and carry
(C)

 Subtractor circuit is a combinational digital circuit that is used for subtracting numbers. A
typical subtractor circuit produces a difference bit (denoted by D) and a borrow bit (denoted by B) as
the output.

 Half Subtractor: The half-subtractor is a combinational circuit which is used to perform

subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D
(difference) and B (borrow).

 Full Subtractor: A combinational circuit of full-subtractor performs the operation of subtraction of

three bits—the minuend, subtrahend, and borrow generated from the subtraction operation of
previous significant digits and produces the outputs difference and borrow.

Equipment / Components Required:

1. NOT Gate ( IC 7404 ) – 1

2. 2 Input AND Gate ( IC7408 ) - 2
3. 2 Input OR Gate ( IC7432 ) -1
4. Digital IC Trainer Kit – 1
5. Patch Cords – As required

Procedure:
1. Verify all components & patch chords whether they are in good condition or not.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
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4. Give supply to the trainer kit.

5. Provide input data to the circuit via switches.
6. Observe the outputs and verify the Truth Table.

PIN diagrams:

IC 7404 Pin Diagram

IC 7408 Pin Diagram

IC 7432 Pin Diagram

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Half Adder:

Truth Table for Half Adder:

INPUT OUTPUT
A B Sum Carry
Sum = A’ . B + A . B’
0 0 0 0
Carry = A . B
0 1 1 0
1 0 1 0
1 1 0 1

Truth Table for Full Adder:

INPUT OUTPUT
A B Cin Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 0

Truth Table for Half Subtractor:

INPUT OUTPUT
A B Difference Barrow
0 0 0 0 Difference = A’ . B + A . B’
Borrow = A’B
0 1 1 1
1 0 1 0
1 1 0 0

Truth Table for Full Subtractor:

INPUT OUTPUT
A B Bin(C) Difference Barrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

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Design 1:

Circuit Diagram for Half Adder ( Using Basic Gates ):

Circuit Diagram for Full Adder ( Using Basic Gates ):

Circuit Diagram for Half Subtractor ( Using Basic Gates ):

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Circuit Diagram for Full Subtractor ( Using Basic Gates ):

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Design 2:

Circuit Diagram for Half Adder ( Using XOR ):

Circuit Diagram for Full Adder ( Using XOR ):

Circuit Diagram for Half Subtractor ( Using XoR Gate ):

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Circuit Diagram for Full Subtractor ( Using XOR Gate ):

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Simulation Variant 1:

Half Adder VHDL Code:

library IEEE;
use
IEEE.STD_LOGIC_116
4.ALL; use
IEEE.STD_LOGIC_ARI
TH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HalfAdder is
Port ( A, B : in STD_LOGIC; Sum, Carry : out STD_LOGIC);
end HalfAdder;
architecture equation of
HalfAdder is begin
sum <= ((not A)and B)or(A
and(not B));
carry <= A and B;
end equation;

Output Waveform for Half Adder:

Half Subtractor VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HalfSub is
Port ( A,B : in STD_LOGIC; Diff,Borrow : out STD_LOGIC);
end HalfSub;
architecture equation of HalfSub is begin
Diff <= ((not A)and B) or (A and(not B));
Borrow <= ((not A)and B);
end equation;

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Output Waveform for Half Subtractor:

Full Adder VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FullAdder is

Port ( A,B,C : in STD_LOGIC; Sum,Carry : out STD_LOGIC);

end FullAdder;
architecture equation of
FullAdder is begin
sum<=(((not A)and(not b)and c)or((not A)and B and(not C))or(a and(not B)and(not C))or(A and B and C));
carry<=(A and B)or(B and C)or(A and C);
end equation;

Output Waveform for Full Adder:

Full Subtractor VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FullSubtractor is
Port ( A,B,C : in STD_LOGIC; Diff,Borrow : out STD_LOGIC);
end FullSubtractor;
architecture equation of FullSubtractor is begin
Diff <= (((not A)and(not b)and c)or((not A)and B and(not C))or(a and(not B)and(not C))or(A

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and B and C));

Borrow <= (A and B)or(B and C)or(A and C); end equation;

Output Waveform for Full Subtractor:

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Simulation Variant 2:

Simulation: VHDL code

for adder, subtractor library

ieee;
use ieee.std_logic_1164.all;

entity adder is port(a,b,c: in std_logic; HAsum, HAcout, FAsum, FAcout, HSdiff,

HSborr, FSdiff, FSborr: out std_logic);
end adder;

architecture
dataflow of adder
is begin
HAsum<= a xor b;
HAcout <= a and b;
FAsum<= a xor b xor c;
FAcout <= ((a and b)or(b and c) or(a and c));
HSdiff<= a xor b;
HSborr <= (a and (not b));
FSdiff<= a xor b xor c;
FSborr <= ((b xor c) and (not a)) or (b and c);
end dataflow;

Output Waveform

Note: File name, project name, entity name should be same

Results & Conclusions:

1) The truth table of half adder, half subtractor, full adder and full subtractor is verified.
2) The output waveform of half adder, half subtractor, full adder and full subtractor is
simulated and verified.

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Experiment No.5: Given any 4-variable logic expression, simplify it using

appropriate technique and realize the simplified logic expression using 8:1
multiplexer IC. And implement the same in HDL.

Description:
The term multiplex means “many to one”. A multiplexer (MUX) has n inputs.
Each line is used to shift digital data serially. There is a single output line. One of
the data stored in the n input line is transferred to the output based on the valued
of control bits. An n to 1 multiplexer requires m control bits where n<= 2m .
To construct an 4 variable function we require a 16(24) to 1 multiplexer, whereas
using an entered variable map method a 4 variable expression can be realized using
8(23) to 1 multiplexer.

 An 8 to 1 multiplexer has 8 data inputs, 3 selector inputs and 1 output.

 Entering variable into Karnaugh map along with 0‘s, 1‘s and don‘t care conditions is called Entered
Variable K Map or Map Entered Variable K map.

 Rules for entering values in a Map Entered Variable K map are:

Rule No. MEV f Map Entry Comments
0 0 If function equals 0 for both values of MEV, enter 0 in appropriate
1 0
1 0 cell of MEV Map.
0 1
2 1 If function equals 1 for both values of MEV, enter 1.
1 1
0 0
3 1 1 MEV If function equals MEV, enter MEV
0 1
4 1 0 MEV If the function is compliment of MEV, enter MEV
0 X
5 1 X If function equals X, enter X
X
0 0
6 0 f=0 for MEV=0 and f=X for MEV=1,enter 0
1 X
0 X
7 1 0 f=X for MEV=0 and f=0 for MEV=1,enter 0
0
0 1
8 1 f=1 for MEV=0 and f=X for MEV=1,enter 1
1 X
0 X
9 1 1 f=X for MEV=0 and f=1 for MEV=1,enter 1
1

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Equipment / Components Required:

1. IC74151 ( 8:1 MUX) – 1

2. IC7404 (NOT Gate) - 1
3. Digital IC Trainer Kit – 1
4. Patch Cords – As required

Procedure:
1. Assume that the 4-variable Boolean function Y = F(A,B,C,D) = ∑ (2, 4, 5, 7, 10,
14) is to be implemented using 8:1 multiplexer IC 74151.

2. Considering A, B, C as the control inputs and D as the data input, implantation table will be Data
input to MUX

3.

.
4. Check all the components for their working.
5. Insert the appropriate IC into the IC base.
6. Make connections as shown in the circuit diagram.
7. Give supply to the trainer kit.
8. Provide input data to the circuit via switches.
9. Observe the outputs and verify the Truth Table.

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PIN diagrams:

IC 7404 Pin Diagram

IC 74151 Pin Diagram

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Design1: 4-variable Boolean function design using IC74151:

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Design2: 4-variable Boolean function design using IC74151:

Y = F(A,B,C,D) = ∑ (0, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 15)

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Simulation Variant 1:

VHDL code for 8:1

MUX

Description:
An 8:1 multiplexer has 8 inputs and one output. The data stored in one of these 8 input line is
transferred serially to the output based on the value of the selection bits

Truth table:
INPUTS OUTPUTS
SEL (2) SEL (1) SEL (0) Zout
0 0 0 I(0)
0 0 1 I(1)
0 1 0 I(2)
0 1 1 I(3)
1 0 0 I(4)
1 0 1 I(5)
0 1 1 I(6)
1 1 1 I(7)

VHDL code for 8 to 1 MUX (behavioral modeling):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; // includes the standard library entity mux1 is
Port ( I : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(2 downto 0); //Input and output is declared as ports
zout : out std_logic);
end mux1;
architecture
Behavioral of
mux1 is begin
zout<= I(0) when sel="000" else // Based on the value of selection the
value of data I(1)
when sel="001" else I(2) //stored in the array I is stored in zout
when sel="010" else I(3)
when sel="011" else I(4)
when sel="100" else I(5)
when sel="101" else I(6)
when sel="110" else I(7);
end Behavioral;

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Wavefrom:

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Simulation Variant 2:
8:1 multiplexer VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux8to1 is
Port ( S : in STD_LOGIC_VECTOR (2 downto 0);

D : in STD_LOGIC_VECTOR (7 downto 0);

Y : out STD_LOGIC);
end mux8to1;
architecture Dataflow
of mux8to1 is begin
with S select
Y <= D(0) when "000",

D(1) when "001",

D(2) when "010",
D(3) when "011",
D(4) when "100",
D(5) when "101",
D(6) when "110",
D(7) when others;

End Dataflow;

Observation Table for 8:1 multiplexer:

Selector Inputs Data Inputs Output

A B C D0 D1 D2 D3 D4 D5 D6 D7 Y
0 0 0 1 0 0 0 0 0 0 0 1
0 0 1 0 1 0 0 0 0 0 0 1
0 1 0 0 0 1 0 0 0 0 0 1
0 1 1 0 0 0 1 0 0 0 0 1
1 0 0 0 0 0 0 1 0 0 0 1
1 0 1 0 0 0 0 0 1 0 0 1
1 1 0 0 0 0 0 0 0 1 0 1
1 1 1 0 0 0 0 0 0 0 1 1

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Output Waveform for 8:1 multiplexer:

Results & Conclusions:

1) Given 4 variable Boolean function is implemented using 8:1 multiplexer of IC 74151.

2) The output waveform of 8:1 multiplexer is simulated and verified.

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Experiment No.6: Realize a J-K Master/Slave FF using NAND gates and verify its
truth table. And implement the same in HDL.

Description:
A flip-flop is a device very much like a latch in that it is a bistable multivibrator,
having two states and a feedback path that allows it to store a bit of information.
The difference between a latch and a flip-flop is that a latch is asynchronous, and
the outputs can change as soon as the inputs do (or at least after a small
propagation delay). A flip-flop, on the other hand, is edge-triggered and only
changes state when a control signal goes from high to low or low to high.

Master Slave Flip Flop:

The control inputs to a clocked flip flop will be making a transition at
approximately the same times as triggering edge of the clock input occurs. This
can lead to unpredictable triggering.
A JK master flip flop is positive edge triggered, whereas slave is negative edge
triggered. Therefore master first responds to J and K inputs and then slave. If J=0
and K=1, master resets on arrival of positive clock edge. High output of the master
drives the K input of the slave.
For the trailing edge of the clock pulse the slave is forced to reset. If both the
inputs are high, it changes the state or toggles on the arrival of the positive clock
edge and the slave toggles on the negative clock edge. The slave does exactly what
the master does.

Equipment / Components Required:

1. IC7404 (NOT Gate) – 1

2. IC 7410 ( 3 i/p NAND Gate ) – 2
3. IC 7400 ( 2 i/p NAND Gate ) – 1
4. Digital IC Trainer Kit – 1
5. Patch Cords – As required

Procedure:
1. Verify all components & patch chords whether they are in good
condition or not.
2. Make connections as shown in the circuit diagram.
3. Give supply to the trainer kit.
4. Provide input data to circuit via switches.
5. Verify truth table sequence & observe outputs.

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PIN diagrams:

IC 7404 Pin Diagram

IC 7410 Pin Diagram

IC 7400 Pin Diagram

Truth Table for JK-Master/Slave Flip-Flop

INPUTS Q(t) BEFORE CP OUTPUTS

J K (Establish using PRSET Q(t+1) Q(t+1)‘
& CLEAR)
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 0 1
1 0 0 1 0
1 0 1 1 0
1 1 0 1 0
1 1 1 0 1

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(Simplified Table)

INPUTS NORMAL
OUTPUT
J K Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q(t)‘

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Design1: JK Master Slave Flip Flop Circuit:

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Simulation Variant 1:

J-K Master/Slave flip flop VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jk_ff is
port(j,k,cr,pr,clk:in std_logic; q,qbar:out std_logic);
end jk_ff;
architecture behavioural of jk_ff is
signal input:std_logic_vector(1 downto 0);
begin
input<=j&k;
process(clk,j,k,pr,cr)
variable temp:std_logic:='0';
begin
if(cr='1' and pr='1')then
if rising_edge(clk) then
case input is
when "10"=> temp:='1';
when "01"=> temp:='0';
when "11"=> temp:=not temp;
when others=> null;
end case;
end if;
else
temp:=’0’
end if;
q<=temp;
qbar<=not temp;
end process;
end behavioural;

Output Waveform for J-K flip flop:

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Simulation Variant 2:
VHDL code for JK master slave Flipflop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity jkflip is
Port ( J, K, clk : in std_logic; Q : buffer std_logic);
end jkflip;

architecture Behavioral of jkflip is begin

process(clk) begin
if rising_edge(clk) then
Q<= ((J and (not Q)) or ((not K) and Q));
end if;
end process;
end Behavioral;

Output Waveform

Result & Conclusions:

1) J-K Master/Slave flip flop is realized using NAND gates and its truth table is verified.
2) The output waveform of J-K Master/Slave flip flop is simulated and verified.

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Experiment No 7: Design and implement code converter I) Binary to Gray

II) Gray to Binary Code using basic gates.

Description:
Gray Code is one of the most important codes. It is a non-weighted code which
belongs to a class of codes called minimum change codes. In this codes while
traversing from one step to another step only one bit in the code group changes. In
case of Gray Code two adjacent code numbers differs from each other by only one
bit.
Binary to gray code conversion is a very simple process. There are several steps
to do this types of conversions.
Steps given below elaborate on the idea on this type of conversion.
(1) The M.S.B. of the gray code will be exactly equal to the first bit of the
given binary number.
(2) Now the second bit of the code will be exclusive-or of the first and
second bit of the given binary number, i.e if both the bits are same the result
will be 0 and if they are different the result will be 1.
(3) The third bit of gray code will be equal to the exclusive-or of the second
and third bit of the given binary number. Thus the Binary to gray code
conversion goes on. One example given below can make your idea clear on
this type of conversion.

Any binary number can be converted into equivalent Gray code by the following steps:
(i) The MSB of the Gray code is the same as the MSB of the binary number.
(ii) The second MSB (adjacent to the MSB) of the Gray code equals the Ex-OR of the
MSB and second MSB of the binary number.
(iii)The third MSB (adjacent to the second MSB) of the Gray code equals the
exclusive-OR of the second and third MSB bits of the binary number.
(iv) The process continues until we obtain the LSB of the Gray code number by the
addition of the LSB and the next higher adjacent bit of the binary number.

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Any Gray code can be converted into equivalent binary number by the following steps:
(i) The MSB of the binary number is the same as the MSB of the Gray code.
(ii) The second MSB (adjacent to the MSB) of the binary number equals the Ex-OR of
the MSB of the binary number and second MSB (adjacent to the MSB) of the
Gray code.
(iii) The third MSB (adjacent to the MSB) of the binary number equals the exclusive-
OR of the second MSB of the binary number and third MSB of the Gray
code.
(iv) The process continues until we obtain the LSB of the binary number.

Equipment / Components Required:

1. IC7404 (NOT Gate) – 1

2. IC 7408 (AND Gate) – 2
3. IC 7432 (OR Gate ) – 1
4. Digital IC Trainer Kit – 1
5. Patch Cords – As required

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PIN diagrams:

IC 7404 Pin Diagram

IC 7408 Pin Diagram

IC 7432 Pin Diagram

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Truth table for Binary to Gray Code Conversion: Truth table for Gray Code to Binary Conversion:

BINARY GRAY GRAY BINARY

B3 B2 B1 B0 G3 G2 G1 G0 G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0

0 1 1 0 0 1 0 1 0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1

1 0 0 0 1 1 0 0 1 0 0 0 1 1 1 1

1 0 0 1 1 1 0 1 1 0 0 1 1 1 1 0

1 0 1 0 1 1 1 1 1 0 1 0 1 1 0 0

1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 1

1 1 0 0 1 0 1 0 1 1 0 0 1 0 0 0

1 1 0 1 1 0 1 1 1 1 0 1 1 0 0 1

1 1 1 0 1 0 0 1 1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0
1 1 1 1 1 0 0 0

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Design 1: Gray to Binary & Binary to Gray

Gray to Binary:
Equations:

B3 = G3
B2 = G3 ⊕ G2
B1 = B2 ⊕ G1 = (G3 ⊕ G2) ⊕ G1
B0 = B1 ⊕G0 = (G3 ⊕G2) ⊕ (G1 ⊕ G0)

Binary to Gray
Equations:

G3 = B3
G2 = B3 ⊕ B2
G1 = B2 ⊕ B1
G0 = B1 ⊕ B0

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Design 2: Gray to Binary & Binary to Gray

Binary to Gray:

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Gray to Binary:

Results & Conclusions:

1) Binary to gray code conversion is realized using basic gates and truth table is verified.
2) Gray to binary code conversion is realized using basic gates and truth table is verified.

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Experiment No.8: Design and implement a mod n (n<8) synchronous up counter using
JK Flip Flop ICs and demonstrate its working.

Description:

The ripple counter requires a finite amount of time for each flip flop to change
state. This problem can be solved by using a synchronous parallel counter where
every flip flop is triggered in synchronism with the clock, and all the output which
are scheduled to change do so simultaneously.
The counter progresses counting upwards in a natural binary sequence from count
000 to count 100 advancing count with every negative clock transition and get
back to 000 after this cycle.

Equipment / Components Required:

1. IC7476 (JK Flip Flop) – 2

2. IC 7408 (AND Gate) – 1
3. IC 7404 (NOT Gate) - 1
4. Digital IC Trainer Kit – 1
5. Patch Cords – As required

PIN diagrams:

IC 7404 Pin Diagram

IC 7408 Pin Diagram

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IC 7476 Pin Diagram

PROCEDURE:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Give supply to the trainer kit.
5. Provide input data to the circuit via switches.
6. Observe the outputs and verify the Truth Table.

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Design 1: Synchronous MOD 8 Counter Design

To successfully design synchronous counters we may employ the

following six basic steps:
1. Create the state transition diagram.
2. Create a present state-next state table (often referred to as the next state
table).
3. Expand the table to form the transition table for each flip-flop in the
circuit. The transition table shows the flip-flop inputs required to
make the counter go from present state to the desired next state. This
is also referred to as the excitation table.
4. Determine the logic functions of the J and K inputs as a function of the present
states.
5. Analyse the counter to verify the design.
6. Construct and test the counter.

Function Table:

Functional Truth Table for J-K Flip Flop:

J K Qn Qn+1
0 0
0 0
1 1
0 0
0 1
1 0
0 1
1 0
1 1
0 1
1 1
1 0

State Synthesis Table for JK Flip Flop

Present state Next state J K

0 0 0 X
0 1 1 X

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1 0 X 1
1 1 X 0
Employ these techniques to design a MOD-8 counter to count in the
following sequence: 0, 1, 2, 3, 4, 5, 6, 7.
Step1: Creating state transition diagram.

Step 2: Creating present state-next state table

Present State Next State

Qc Qb Qa Qc Qb Qa
0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1 0 0 0

Step 3: Expand the present state-next state table to form the transition table.
Present State Next State Present inputs

Q Q Q Q Q Q J K JB K JA KA
c B A C B A C c B
0 0 0 0 0 0 1 0 X 0 X 1 X

1 0 0 1 0 1 0 0 X 1 X X 1

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2 0 1 0 0 1 1 0 X X 0 1 X

3 0 1 1 1 0 0 1 X X 1 X 1

4 1 0 0 1 0 1 X 0 0 X 1 X

5 1 0 1 1 1 0 X 0 1 x X 1

6 1 1 0 1 1 1 X 0 X 0 1 X

7 1 1 1 0 0 0 X 1 X 1 X 1

Step 4: Use Karnaugh maps to identify the present state logic functions for each of
the input.
‘X’ indicates a "don’t care" condition.

C C
00 01 11 10 00 01 11 10
BA BA
0 0 1 0 x x x x
0 0
X x X x 0 0 1 0
Jc = QbQa Kc=QbQa

C C
00 01 11 10 00 01 11 10
BA BA
0 1 X x x X 1 0
0 0
0 1 X x x X 1 0
Jb = Qa Kb = Qa

C C
00 01 11 10 00 01 11 10
BA BA
1 X X 1 X 1 1 X
0 0
1 X X 1 X 1 1 X
Ja = 1 Ka = 1

Step 5: Trace through indicates circuit should work correctly.

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Step 6: Constructing Circuit

A three-bit synchronous counter

Note:
Connect preset and clear to high to work on normal operation

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Design 2: Synchronous MOD 8 Counter Design

Truth Table for JK-Master/Slave Flip-Flop

Clock Outputs
Count QC QB QA
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 0 0 0

In order to design a MOD-5, which has five distinct states (N=5), the number of flip-flops
required is
3. The state diagram for MOD 5 counter is shown below.

State table of the counter is derived with the excitation table of the JK flip-flop given
below.

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After K-Map simplification, expressions for the flip-flop inputs are as shown below:

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MOD 5 Synchronous Up Counter Circuit:

Experiment No.9: Design and implement asynchronous counter using decade

counter IC to count up from 0 to n (n≤9) and demonstrate on seven segment
display (using IC- 7447).

Description:
Asynchronous counter is a counter in which the clock signal is connected to the clock input of only
first stage flip flop. The clock input of the second stage flip flop is triggered by the output of the
first stage flip flop and so on. This introduces an inherent propagation delay time through a flip
flop. A transition of input clock pulse and a transition of the output of a flip flop can never occur
exactly at the same time. Therefore, the two flip flops are never simultaneously triggered, which
results in asynchronous counter operation.
A binary Coded Decimal (BCD) is a serial digital counter that counts ten digits and it resets for
every new clock input. As it can go through 10 unique combinations of output, it is also called as
Decade Counter. 7490 is an asynchronous decade counter.

Equipment / Components Required:

1. IC7490 (Decade Counter) – 1

2. IC 7447 (BCD to Seven Segment Decoder) – 1
3. Digital IC Trainer Kit – 1
4. Patch Cords – As required

Procedure:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Give supply to the trainer kit.

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5. Provide input data to the circuit via switches.

6. Observe the outputs and verify the Truth Table.

Truth Table for MOD10 asynchronous counter Truth Table for MOD 7 asynchronous
counter
Output Output
Clock Clock
7490 7490
Count 7447 Count 7447
QD QC QB QA QC QB QA
0(by reset) 0 0 0 0 0 0(by reset) 0 0 0 0
1 0 0 0 1 1 1 0 0 1 1
2 0 0 1 0 2 2 0 1 0 2
3 0 0 1 1 3 3 0 1 1 3
4 0 1 0 0 4 4 1 0 0 4
5 0 1 0 1 5 5 1 0 1 5
6 0 1 1 0 6 6 1 1 0 6
7 0 1 1 1 7 7(repeats) 0 0 0 0
8 1 0 0 0 8
9 1 0 0 1 9
10(repeats) 0 0 0 0 0

Truth Table for MOD 6 asynchronous counter Truth Table for MOD 5 asynchronous
counter
Output Output
Clock Clock
7490 7490
Count 7447 Count 7447
QC QB QA QC QB QA
0(by reset) 0 0 0 0 0(by reset) 0 0 0 0
1 0 0 1 1 1 0 0 1 1
2 0 1 0 2 2 0 1 0 2
3 0 1 1 3 3 0 1 1 3
4 1 0 0 4 4 1 0 0 4
5 1 0 1 5 5(repeats) 0 0 0 0
6(repeats) 0 0 0 0

Truth Table for MOD 4 asynchronous counter Truth Table for MOD 3 asynchronous
counter
Output Output
Clock Clock
7490 7490
Count Count
QB QA 7447 QB QA 7447
0(by reset) 0 0 0 0(by reset) 0 0 0
1 0 1 1 1 0 1 1
2 1 0 2 2 1 0 2
3 1 1 3 3(repeats) 0 0 0
4(repeats) 0 0 0

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PIN diagrams:

IC 7490 Pin Diagram

IC 7447 Pin Diagram

MOD 10 asynchronous counter with 7 segment display Circuit

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MOD 7 asynchronous counter with 7 segment display Circuit

MOD 6 asynchronous counter with 7 segment display Circuit

MOD 5 asynchronous counter with 7 segment display Circuit

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MOD 4 asynchronous counter with 7 segment display Circuit

MOD 3 asynchronous counter with 7 segment display Circuit

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Design 2:

Pin Names Description of 7447:

A0–A3 =BCD Inputs
RBI =Ripple Blanking Input (Active LOW)
LT= Lamp Test Input (Active LOW)
RBO =Ripple Blanking Output (Active LOW)
a –g =Segment Outputs (Active LOW)
Pin Names Description of 7490:
R1 and R2-clear all filpflop (high active and low for not active)
S1 and S2- set all flip flop (high active and low for not active)
CLKA-clock pulse to first flip flop
CLKB-clock pulse to second flip flop (output of first flip flop clock for second filp
flop)

Circuit Diagram:

For mod 9
Connect Q0 and Q3 to reset(clear) through an AND gate. Reset should not be connected to
the switch
For mod8
Connect Q3 to reset
For mod7
Connect Q2, Q1,Q0 to reset through an And Gate
For Mod 6
Connect Q2 and Q1 to reset through an AND gate
For mod 5
Connect Q0 and Q2 to reset through an AND gate
For Mod 4

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Connect Q2 to reset
For mod 3
Connect Q1 and Q0 to reset through an AND gate
For mod 2
Connect Q1 to reset

Function Table:

Clock Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

Results & Conclusion: Asynchronous counter to count up from 0 to n (n≤9) is realized using
decade counter IC and seven segment display IC-7447.

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Sample Viva Questions

1. Why operational amplifier is called by its name?

2. Explain the advantages of OPAMP over transistor amplifiers.
3. List the OPAMP ideal characteristics.
4. Give the symbol of OPAMP
5. Explain the various applications of OPAMP
6. Define UTP and LTP
7. Mention the applications of schmitt trigger
8. What is a square wave generator/ Regenerative comparator?
9. Give the hysterisis curve of a schmitt trigger
10. What is a bipolar and unipolar devices? Give examples
11. Define resolution
12. Explain the need of D/A and A/D converters.
13. List the different types of A/D and D/ A converters
14. What is a multivibrators?
15. What is a bistable multivibrators?
16. Give the applications of monostable and astable multivibrators
17. Explain the working of 555 timer as astable and monostable multivibrator
18. Why astable multivibrator is called as free running multivibrato
19. Define duty cycle.
20. List the applications of 555 timer
21. Explain 555 timer as astable multivibrator to generate a rectangular wave of
duty cycle of less than 0.5
22. Define a logic gate.
23. What are basic gates?
24. Why NAND and NOR gates are called as universal gates?
25. State De morgans theorem
26. Give examples for SOP and POS
27. Explain how transistor can be used as NOT gate
28. Realize logic gates using NAND and NOR gates only
29. List the applications of EX-OR and EX~NOR gates
30. What is a half adder?
31. What is a full adder?
32. Differentiate between combinational and sequential circuits. Give examples
33. Give the applications of combinational and sequential circuits
34. Define flip flop
35. What is an excitation table?
36. What is race around condition?
37. How do you eliminate race around condition?

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38. What is minterm an d max term?

39. Define multiplexer/ data selector
40. What is a demultiplexer?
41. Give the applications of mux and demux
42. What is a encoder and decoder?
43. Compare mux and encoder
44. Compare demux and decoder
45. What is a priority encoder?
46. What are counters? Give their applications.
47. Compare synchronous and asynchronous counters
48. What is modulus of a number?
49. What is a shift register?
50. What does LS stand for, in 74LSOO?
51. What is positive logic and negative logic?

52. What are code converters?

53. What is the necessity of code conversions?
54. What is gray code?
55. Realize the Boolean expressions for
a Binary to gray code conversion
b Gray to binary code conversion

Note:
All the above questions are the most commonly asked and the depth of it may
vary based on the answers which you give during the viva voice procedure.

All the very best!

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