RTL TO GDS

Article-18
RTL DESIGN Examples

Semiconductor
Industry

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 DAY-1
#100DAYSRTL
Aim:- To design the Clock divider (by clk/2n)
Verilog Code:-

Waveforms:-
Schematics:-
 DAY-3
#100DAYSRTL
“Aim”:- To verify the Clock divider (by clk/odd) using Verilog
“Verilog Code”:-

Schematics:-
Waveforms:-
 DAY-5
#100DAYSRTL
“Aim”:- To Design the 4 bit ripple carry adder using Verilog
“Verilog Code”:-

“Schematics”:-
“Waveforms”:-

“Console Results”:-
 DAY-7
#100DAYSRTL
“Aim”:- To Design the 4 bit Carry Look Ahead adder using
Verilog
“Verilog Code”:-
“Schematics”:-

“Waveforms”:-

“Console Results”:-
TopModule:-
 DAY-9
#100DAYSRTL
“Aim”:- To Design the 4 bit Adder-Subtractor using Verilog
“Verilog Code”:-

“Schematics”:-
“Waveforms”:-
For Addition

For Subtraction
 DAY-11
#100DAYSRTL
“Aim”:- To Design the 4 bit multiplier using Verilog
“Verilog Code”:-

“Schematics”:-

“Waveforms”:-
 DAY-12
#100DAYSRTL
“Aim”:- To Design the 4bit Gray to Binary converter and
Binary to Gray converter Verilog
“Verilog Code”:-

“Schematics”:-
“Waveforms”:-
 DAY-13
#100DAYSRTL
“Aim”:- To Design the CMOS inverter using Verilog
“Verilog Code”:-

“Schematics”:-

“Waveforms”:-
 DAY-14
#100DAYSRTL
“Aim”:- To Design the Decoder which converts the binary
value to octal, decimal and Hexadecimal
“Verilog Code”:-
“Schematics”:-

“Waveforms”:-
 DAY-15
#100DAYSRTL
“Aim”:- To Design the Encoder that converts Decimal, Octal,
and Hexadecimal into binary values.
“Verilog Code”:-
“Schematics”:-

“Waveforms”:-
 DAY-16
#100DAYSRTL
“Aim”:- To Design BCD to a seven-segment display Decoder
“Verilog Code”:-
“Schematics”:-

“Waveforms”:-

“Console Results”:-
 DAY-17
#100DAYSRTL
“Aim”:- To Design the water level indicator using 8X3 encoder
“Verilog Code”:-
“Schematics”:-

“Waveforms”:-

“Console Results”:-
 DAY-18
#100DAYSRTL
“Aim”:- To Design the Parity Checker
“Verilog Code”:-

“Schematics”:-

“Waveforms”:-

“Console Results”:-
 DAY-19
#100DAYSRTL
“Aim”:- To Design the Binary Digit Counter Which Counts the
occurrence of ones and zeros.
“Design Code”:-

“Schematics”:-

“Waveforms”:-
 DAY-20
#100DAYSRTL
“Aim”:- To Design the Arithmetic Logic unit (ALU) which
performs 16 operations
“Design Code”:-

“Schematics”:-
“Waveforms”:-
 DAY-21
#100DAYSRTL
“Aim”:-To Design a MUX that acts as an Asynchronous PISO
“Design Code”:-

“Schematics”:-

“Waveforms”:-
“Console”:-
 DAY-22
#100DAYSRTL
“Aim”:-To Design a DEMUX that acts as an Asynchronous
SIPO using System Verilog Design style
“Design Code”:-
“Schematics”:-

“Console”:-
 DAY-23
#100DAYSRTL
“Aim”:- To Design the input majority circuit in Mixed
modeling (Gate & Data Flow).
“Design Code”:-

The min-terms notation for the 5-input majority function is:

“Console”:-
 DAY-24
#100DAYSRTL
“Aim”:- To Design the Circuit which gives HCF(Highest
common factor) of two numbers using System Verilog.
“Design Code”:-
“Waveforms”:-

“Console”:-
 DAY-25
#100DAYSRTL
“Aim”:- To Design a synchronous Traffic Light Controller
circuit using Verilog
“Design Code”:-
“Waveforms”:-

“Schematics”:-

“Console”:-
 DAY-26
#100DAYSRTL
“Aim”:-To design SR Latch using Nand Gates or Nor Gates
“SR latch Using Nand Gates” :-
“Design Code”:-

“Schematics”:-

“Waveforms”:-
“Console”:-

When !Q=Q , Then it is invalid condition

“Schematics”:-

“Waveforms”:-

“Console”:-

When !Q=Q , Then it is invalid condition

“Waveforms”:-
“D Latch” :-
“Design Code”:-

“Schematics”:-
“Waveforms”:-
 DAY-28
#100DAYSRTL
“Aim”:-To design all single bit flipflops (SR,JK,T,D)
“SR Flipflop” :-
“Design Code”:-

“Waveforms”:-
“Schematics”:-
“JK Flipflop” :-
“Design Code”:-

“Schematics”:-
“Waveforms”:-
“D Flipflop” :-
“Design Code”:-

“Schematics”:-
“Waveforms”:-
“T Flipflop” :-
“Design Code”:-

“Schematics”:-
“Waveforms”:-
 DAY-29
#100DAYSRTL
“Aim”:-To Specify the differences between a Multi bit flip flop
and a register.
Multi-bit Flipflop vs Register :-

D-4bitFlipFlop
“Design Code”:-
“Waveforms”:-

“Schematics”:-
“4bitRegister” :-
“Design Code”:-

“Schematics”:-

“Waveforms”:-
 DAY-30
#100DAYSRTL
“Aim”:-To Design Serial Input and Serial output & Serial input
and Parallel output
“SISO”
“Design Code”:-

“Waveforms”:-

“Schematics”:-
“SIPO”
“Design Code”:-

“Schematics”:-
“Waveforms”:-
 DAY-31
#100DAYSRTL
“Aim”:-To Design Parallel Input and Serial output & Parallel
input and Parallel output
“PISO”
“Design Code”:-

“Waveforms”:-

“Schematics”:-
“PIPO”
“Design Code”:-

“Schematics”:-
“Waveforms”:-
 DAY-32
#100DAYSRTL
“Aim”:-To Design Universal Shift register which performs
linear circular left and right shift operations

“Design Code”:-

“Schematics”:-
“Waveforms”:-
 DAY-33
#100DAYSRTL
“Aim”:-To Design Binary Ripple counter or Asynchronous
(series) counter
“Design Code”:-

“Waveforms”:-
“Schematics”:-
 DAY-34
#100DAYSRTL
“Aim”:-To Design Non-binary Ripple counter (Decade counter
or Mod10 counter).
“Design Code”:-

“Waveforms”:-
“Schematics”:-
 DAY-35
#100DAYSRTL
“Aim”:-To Design Ring Counter (non self starting counter)
“Design Code”:-

“Waveforms”:-
“Schematics”:-
 DAY-36
#100DAYSRTL
“Aim”:-To Design JhonSonCounter (SwitchTailRing counter)
“Design Code”:-

“Waveforms”:-
“Schematics”:-
 DAY-37
#100DAYSRTL
“Aim”:-To Design a Synchronous series counter
“Design Code”:-

“Waveforms”:-
“Schematics”:-
 DAY-38
#100DAYSRTL
“Aim”:-To Design a Universal Counter ( Down & Up )
“Design Code”:-

“Waveforms”:-

“Elaborated Design”:-
“Implemented Design”:-
 DAY-39
#100DAYSRTL
“Aim”:-To design a Multi-Functional barrel shifter (rotates left
or right )
“Design Code”:-

“Waveforms”:-
“Console”:-

“Elaborated Design”:-

“Implemented Design”:-
 DAY-40
#100DAYSRTL
“Aim”:-To design Positive Edge detector Circuit and Negative
Edge detector Circuit
“Positive Edge detector Circuit”
“Design Code”:-

“Waveforms”:-

“Elaborated Design”:-
“Implemented Design”:-

“Negative Edge detector Circuit”

“Waveforms”:-
“Elaborated Design”:-

“Implemented Design”:-
 DAY-41
#100DAYSRTL
“Aim”:-To design a Memory of Size 1 MB 32 bit .
“Design Code”:-

“Waveforms”:-

“Elaborated Design”:-
“Implemented Design”:-
 DAY-42
#100DAYSRTL
“Aim”:-To design a synchronous 32 bit depth FIFO
“Design Code”:-
“Waveforms”:-

“Elaborated Design”:-
“Implemented Design”:-
 DAY-43
#100DAYSRTL
“Aim”:-To design a 32-bit Single Port RAM
“Design Code”:-

“Waveforms”:-
“Elaborated Design”:-

“Implemented Design”:-
 DAY-44
#100DAYSRTL
“Aim”:-To design a 32-bit Dual Port RAM
“Design Code”:-

“Waveforms”:-
“Elaborated Design”:-

“Implemented Design”:-
 DAY-45
#100DAYSRTL
“Aim”:-To design a 16 bit depth Asynchronous FIFO
“Design Code”:-
“Waveforms”:-

“Implemented Design”:-
 DAY-46
#100DAYSRTL
“Aim”:-To design a Melay FSM sequence detector to detect the
sequence 11 or 00 (Non Overlapping)
“Theory”:-

• Mealy machine depends on present state and present input

“Design Code”:-
“Waveforms”:-

“Console”:-

“Elaborated Design”:-

“Implemented Design”:-
 DAY-47
#100DAYSRTL
“Aim”:- To design a Moore FSM sequence detector to detect
the sequence 11 or 00 (Non Overlapping)
“Theory”:-

• Moore FSM depends on the present state only

“Design Code”:-
“Waveforms”:-

“Console”:-

“Elaborated design”:-
“Implemented design”:-
 DAY-48
#100DAYSRTL
“Aim”:- To design a Sequence Generator which generates
starting five prime numbers (2,3,5,7,11)
“Theory”:-

“Design Code”:-
“Waveforms”:-

“Elaborated design”:-

“Implemented design”:-
 DAY-49
#100DAYSRTL
“Aim”:- To design a Strict or Fixed priority arbiter.
“Theory”:-

• A fixed priority arbiter selects one of the requesters based on a predefined priority
scheme. In a fixed priority arbiter, the highest priority request is granted access
first. If multiple requests have the same priority, the arbiter selects one of the
requests in a round-robin fashion.
“Design Code”:-

“Waveforms”:-

“Elaborated design”:-
“Implemented design”:-
 DAY-50
#100DAYSRTL
“Aim”:- To design a Round Robin Arbiter
“Theory”:-

• An arbiter in which the priority of requests is set in which all the requested agents
get equal sharing of access is called Round Robin Arbiter
• “Design Code”:-

“Waveforms”:-
“Elaborated design”:-

“Implemented design”:-
THANK YOU !

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