The CD54HC158 and CD54/74HC157, CD54/74HCT157,

CD74HC158 are obsolete and

no longer are supplied. CD54/74HC158, CD54/74HCT158
Data sheet acquired from Harris Semiconductor
SCHS153C
High-Speed CMOS Logic
September 1997 - Revised October 2003 Quad 2-Input Multiplexers

Features Description
• Common Select Inputs The ’HC157, ’HCT157, ’HC158, and ’HCT158 are quad 2-
input multiplexers which select four bits of data from two
[ /Title • Separate Enable Inputs
sources under the control of a common Select input (S). The
(CD74H • Buffered inputs and Outputs Enable input (E) is active Low. When (E) is High, all of the
C157, outputs in the 158, the inverting type, (1Y-4Y) are forced
• Fanout (Over Temperature Range) High and in the 157, the non-inverting type, all of the outputs
CD74H - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads (1Y-4Y) are forced Low, regardless of all other input
CT157, - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads conditions.
CD74H • Wide Operating Temperature Range . . . -55oC to 125oC Moving data from two groups of registers to four common
C158, output buses is a common use of these devices. The state of
• Balanced Propagation Delay and Transition Times
CD74H the Select input determines the particular register from
CT158) • Significant Power Reduction Compared to LSTTL which the data comes. They can also be used as function
Logic ICs generators.
/Subject
(High • HC Types
Ordering Information
Speed - 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at TEMP. RANGE
VCC = 5V PART NUMBER (oC) PACKAGE

• HCT Types CD54HC157F3A -55 to 125 16 Ld CERDIP

- 4.5V to 5.5V Operation
CD54HCT157F3A -55 to 125 16 Ld CERDIP
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min) CD54HCT158F3A -55 to 125 16 Ld CERDIP
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH CD74HC157E -55 to 125 16 Ld PDIP

CD74HC157M -55 to 125 16 Ld SOIC

Pinout CD74HC157MT -55 to 125 16 Ld SOIC
CD54HC157, CD54HCT157, CD54HC158, CD54HCT158 CD74HC157M96 -55 to 125 16 Ld SOIC
(CERDIP)
CD74HC157, CD74HCT157, CD74HC158 CD74HCT157E -55 to 125 16 Ld PDIP
(PDIP, SOIC)
CD74HCT158 CD74HCT157M -55 to 125 16 Ld SOIC
(PDIP)
TOP VIEW CD74HCT157MT -55 to 125 16 Ld SOIC

S 1 16 VCC CD74HCT157M96 -55 to 125 16 Ld SOIC

1I0 2 15 E CD74HCT158E -55 to 125 16 Ld PDIP

1I1 3 14 4I0
NOTE: When ordering, use the entire part number. The suffix 96
1Y 4 13 4I1 denotes tape and reel. The suffix T denotes a small-quantity reel of
2I0 5 12 4Y 250.

2I1 6 11 3I0

2Y 7 10 3I1

GND 8 9 3Y

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
 CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158

Functional Diagram

HC/HCT HC/HCT
157 158
2
1I0 4
3 1Y 1Y
1I1

5
2I0 7
6 2Y 2Y
2I1

11
3I0 9
10 3Y 3Y
3I1

14
4I0 12
13 4Y 4Y
4I1

1 15
S
E

TRUTH TABLE

OUTPUT
SELECT
ENABLE INPUT DATA INPUTS 157 158

E S I0 I1 Y Y

H X X X L H

L L L X L H

L L H X H L

L H X L L H

L H X H H L

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

2
 CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA (oC/W)
DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73
DC Output Diode Current, IOK Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
DC Output Source or Sink Current per Output Pin, IO Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA (SOIC - Lead Tips Only)
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V
Voltage
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V
Voltage
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
Voltage
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
CMOS Loads
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output - - - - - - - - - V
Voltage
-4 4.5 3.98 - - 3.84 - 3.7 - V
TTL Loads
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
Voltage
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
CMOS Loads
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output - - - - - - - - - V
Voltage
4 4.5 - - 0.26 - 0.33 - 0.4 V
TTL Loads
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA
Current GND

3
 CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HCT TYPES
High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V
Voltage 5.5
Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V
Voltage 5.5
High Level Output VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
Voltage
CMOS Loads
High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads
Low Level Output VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Voltage
CMOS Loads
Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads
Input Leakage II VCC and 0 5.5 - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA
Current GND
Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA
Device Current Per (Note 2) -2.1 5.5
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

UNIT LOADS
INPUT HCT157 HCT158
I (All) 0.95 0.4
E 0.6 0.6
S 3 2.8
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.

Switching Specifications Input tr, tf = 6ns

25oC -40oC TO 85oC -55oC TO 125oC
TEST VCC
PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC/HCT157 TYPES
Propagation Delay (Figure 1) tPLH, tPHL CL = 50pF 2 - - 125 - 155 - 190 ns
Data to Output 4.5 - - 25 - 31 - 38 ns
HC157 CL =15pF 5 - 10 - - - - - ns
HCT157 - 12 - - - - - ns
CL = 50pF 6 - - 21 - 26 - 32 ns

4
 CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158

Switching Specifications Input tr, tf = 6ns (Continued)

25oC -40oC TO 85oC -55oC TO 125oC

TEST VCC
PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Enable to Output tPLH, tPHL CL = 50pF 2 - - 135 - 170 - 205 ns
4.5 - - 27 - 34 - 41 ns
HC157 CL =15pF 5 - 11 - - - - - ns
HCT157 - 12 - - - - - ns
CL = 50pF 6 - - 23 - 29 - 35 ns
Select to Output tPLH, tPHL CL = 50pF 2 - - 145 - 180 - 220 ns
4.5 - - 29 - 36 - 44 ns
HC157 CL =15pF 5 - 12 - - - - - ns
HCT157 - 15 - - - - - ns
CL = 50pF 6 - - 25 - 31 - 38 ns
Power Dissipation CPD - 5
Capacitance (Notes 3, 4)
HC157 - 62 - - - - - pF
HCT157 - 70 - - - - - pF
HC/HCT158 TYPES
Data to Output tPLH, tPHL CL = 50pF 2 - - 140 - 175 - 210 ns
4.5 - - 28 - 35 - 42
HC158 CL =15pF 5 - 11 - - - - - ns
HCT 158 - 13 - - - - - ns
CL = 50pF 6 - - 24 - 30 - 36 ns
Enable to Output tPLH, tPHL CL = 50pF 2 - - 160 - 200 - 240 ns
4.5 - - 32 - 40 - 48 ns
HC158 CL =15pF 5 - 13 - - - - - ns
HCT 158 - 15 - - - - - ns
CL = 50pF 6 - - 27 - 34 - 41 ns
Select to Output tPLH, tPHL CL = 50pF 2 - - 150 - 190 - 225 ns
4.5 - - 30 - 38 - 45 ns
HC158 CL =15pF 5 - 12 - - - - - ns
HCT 158 - 14 - - - - - ns
CL = 50pF 6 - - 26 - 33 - 38 ns
Output Transition Time tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Power Dissipation CPD - 5
Capacitance (Notes 3, 4)
HC158 - 35 - - - - - pF
HCT 158 - 35 - - - - - pF
Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per multiplexer.
4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

5
 CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158

Test Circuits and Waveforms

tr = 6ns tf = 6ns tr = 6ns tf = 6ns

VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

tTHL tTLH tTHL tTLH

90% 90%
50% 1.3V
INVERTING 10% INVERTING
10%
OUTPUT OUTPUT
tPHL tPLH tPHL tPLH

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA- FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC

6
 PACKAGE OPTION ADDENDUM

www.ti.com 8-Sep-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-9070201MEA ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9070201ME Samples
& Green A
CD54HCT157F3A
5962-9070301MEA ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9070301ME Samples
& Green A
CD54HCT158F3A
CD54HC157F ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD54HC157F Samples
& Green
CD54HC157F3A ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8606101EA Samples
& Green CD54HC157F3A
CD54HCT157F3A ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9070201ME Samples
& Green A
CD54HCT157F3A
CD54HCT158F3A ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9070301ME Samples
& Green A
CD54HCT158F3A
CD74HC157E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC157E Samples

CD74HC157M LIFEBUY SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC157M
CD74HC157M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC157M Samples

CD74HC157MT LIFEBUY SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC157M
CD74HCT157E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT157E Samples

CD74HCT157M LIFEBUY SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT157M
CD74HCT157M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT157M Samples

CD74HCT157MT LIFEBUY SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT157M
CD74HCT158E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT158E Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 8-Sep-2023

OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC157, CD54HCT157, CD54HCT158, CD74HC157, CD74HCT157, CD74HCT158 :

• Catalog : CD74HC157, CD74HCT157, CD74HCT158

• Military : CD54HC157, CD54HCT157, CD54HCT158

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC157M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT157M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC157M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HCT157M96 SOIC D 16 2500 340.5 336.1 32.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC157E N PDIP 16 25 506 13.97 11230 4.32
CD74HC157E N PDIP 16 25 506 13.97 11230 4.32
CD74HC157M D SOIC 16 40 507 8 3940 4.32
CD74HCT157E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT157E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT157M D SOIC 16 40 507 8 3940 4.32
CD74HCT158E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT158E N PDIP 16 25 506 13.97 11230 4.32

Pack Materials-Page 3
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