e system refused the connection.

The remote system refused the connection.

The remote system refused the connection.
root@hcpm:~# dbg
2000/09/10 14:05:13 socat[4078] E connect(5, AF=2 127.0.0.1:1123, 16): Connection
refused
root@hcpm:~#

U-Boot 2015.01 yocto-2.0 (Jul 11 2019 - 19:06:05) v4.0.12+, build: safe A

CPU0: T1042E, Version: 1.1, (0x85280211)
Core: e5500, Version: 2.1, (0x80241021)
Source Clock Mode: Single ended input
Clock Configuration:
CPU0:1200 MHz, CPU1:1200 MHz, CPU2:1200 MHz, CPU3:1200 MHz,
CCB:500 MHz,
DDR:533.333 MHz (1066.667 MT/s data rate) (Asynchronous),
IFC:31.250 MHz
FMAN1: 500 MHz
QMAN: 250 MHz
PME: 250 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 0a10000c 0c000000 00000000 00000000
00000010: 85000000 00404102 fc027000 21000000
00000020: 00000000 00000000 00000000 0001f002
00000030: 00000100 d556aa05 00000000 00000000
Board: HCPM-based board
(36-bit physical address map)
(devices at high phys.addresses)
PMUXCR: config QE IO clocks as GPIO's
GPIO: ready
Disable unused HW devices:
eSDHC: disable
USB-1: disable
USB-2: disable
SATA-1: disable
SATA-2: disable
DIU: disable
dual I2C 2: disable
DUART-2: disable
NAL: disable
I2C: ready
DRAM: Initializing ... using SPD
Init LEDs on I/O Expander
Config pin directions
Set ON all LEDs
Resetting the DDR3 module ... done
Detected UDIMM SP004GISLU160NH0EI
DDR caslat 7 clocks
DDR wait for D_INIT ... done.
LAW: idx 15, addr 0x0, law_sz 0x1f, trgt_if 0x10
Memory Controller 0 Slot 0: 1 rank DIMM
Memory Controller 0: number of installed DIMM's = 1
DDR TLB Warning: 2 GiB left unmapped
DDR: 4 GiB (DDR3, 64-bit, CL=7, ECC off)
Effective RAM size: 2 GiB
Memory Controller 0 err_detect: 0x00000000
Memory Probe start ...
Testing DRAM from 0x00200000 to 0x00201000
Testing DRAM from 0x10200000 to 0x10201000
Testing DRAM from 0x20200000 to 0x20201000
Testing DRAM from 0x30200000 to 0x30201000
Testing DRAM from 0x40200000 to 0x40201000
Testing DRAM from 0x50200000 to 0x50201000
Testing DRAM from 0x60200000 to 0x60201000
Testing DRAM from 0x70200000 to 0x70201000
Memory Probe finished (passed 24576, failed 0).
DRAM test successfully passed.

Go to relocate_code ...
Now running in RAM - U-Boot at: 7ff30000
List of enabled ERRATUM workarounds:
Work-around for Erratum ESDHC111 (AUTO_CMD12 support) enabled
Init I/O Expander 1
Config input data polarity
Config pins direction
Main Board presence: Yes
MALLOC: ready
Flash: 16 MiB
L2: [backside] 256 KiB enabled
Look for en_cpc option in board_hwconfig
Look for en_cpc option in cpu_hwconfig
Corenet Platform Cache: 256 KiB enabled
Using SERDES1 Protocol: 133 (0x85)
CPU up succeeded. CPU up mask is f.
Environment on NOR flash
Update 'ethaddr' with SYS MAC (f8:54:af:04:32:00)
PCIE1: disable
PCIE2: enabled
PCIE3: disable
PCIE4: disable
STDIO: ready
JUMP_TABLE: ready
In: serial
Out: serial
Err: serial
Fix environment variables ...
Update 'cardtype' from IDPROM
ENV: 'ctrl_fdt_blob' = '0xefd40000'
Fix environment variables finished.
INTERRUPT: ready
Net:
FMan ucode on NOR flash
Fman1: Uploading microcode version 107.4.2
FM1@DTSEC1 connected to MEMAC1_MDIO:0 'FSL TBI PHY'
FSL TBI PHY => perform phy config
FM1@DTSEC2 connected to MEMAC2_MDIO:0 'FSL TBI PHY'
FSL TBI PHY => perform phy config
FM1@DTSEC3 connected to MEMAC3_MDIO:0 'FSL TBI PHY'
FSL TBI PHY => perform phy config
FM1@DTSEC4 connected to MEMAC4_MDIO:0 'FSL TBI PHY'
FSL TBI PHY => perform phy config
FM1@DTSEC5 Nothing to connect
FM1@DTSEC1 [PRIME], FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5
Warning: Your board does not use generic board. Please read
doc/README.generic-board and take action. Boards not
upgraded by the late 2014 may break or be removed.
***************************************************************
HCPM U-BOOT SOFT COPY A

U-Boot 2015.01 yocto-2.0 (Jul 11 2019 - 19:06:05) v4.0.12+, Build: safe A

Board Identification information

CPU0 : T1042E Version 1.1 (0x85280211)
Core : e5500 Version 2.1 (0x80241021)
 Board Type : MIO200B
Board Network Number : 228 (0xe4)
CPM Serial Number : 503948004
CPM Card Type : 0x85cb
CPM HW Revision : B 0009 (0x00420009)
CPM HW Options : 0x000d
IO Serial Number : 503943317
IO Card Type : 0x8a54
IO HW Revision : A 0000 (0x00410000)
IO HW Options : 0x000d
IO FIPS support : disabled
***************************************************************
Running NETW Setup procedure ...

Checking Card Presence ... OK.

Set ON all LEDs
Boot Device is RCP (via backplane port)
Setup ethernet ports MACs (slot u4):
Update 'eth1addr' upon Slot# (02:02:0E:00:D0:06)
Resetting Ethernet Switch 1 ... Done.
Init Ethernet Switch 98DX106 - 10 ports managed (ID 0xD3D3 Rev 0x0)
Setup Ethernet Switch ports:
(to CODM )(SGMII, Autoneg 100BT Full) Port 0: mac status=0xe802
(to RCP-A)(1000Base-X, Fixed 1GB) Port 1: mac status=0xe00f
(to RCP-B)(1000Base-X, Fixed 1GB) Port 2: mac status=0xa40e
(to mEMAC1 'debug VLAN') (SGMII, Fixed 1GB) Port 5: mac status=0xe00f
(to mEMAC2 'backplane VLAN')(SGMII, Fixed 1GB) Port 6: mac status=0xe00f
m98dx106: VLAN ID 4091 MAC learning disable
m98dx106: VLAN ID 4092 MAC learning disable
m98dx106: VID + MAC are used for FDB lookup and learning
Setup network environment:
Set empty 'bootseq'
Update 'ipaddr' from IDPROM
Update 'ethact' to 'FM1@DTSEC2'
Clean 'ipaddr'
Clean 'bootargs'
Update 'bootpath'
Setup FPGA environment variables ... done.

NETW Setup finished.

***************************************************************
Board Status information
Presence (K3) : yes (val 1)
GA bit layout : LSB 0 (legacy)
Geographical Address : 5 (slot# 4) u4
Board installed in : chassis
Reset Reason : power
Boot Device : backplane
Boot Mode : chassis (from RCP using DHCP)
Boot Delay : 5
***************************************************************
Hit any key to stop autoboot: 0
hcpm=> reset
Going to reset ...
ÿ

U-Boot 2015.01 yocto-2.0 (Jul 11 2019 - 19:06:05) v4.0.12+, build: safe A

CPU0: T1042E, Version: 1.1, (0x85280211)

Core: e5500, Version: 2.1, (0x80241021)
Source Clock Mode: Single ended input
Clock Configuration:
CPU0:1200 MHz, CPU1:1200 MHz, CPU2:1200 MHz, CPU3:1200 MHz,
CCB:500 MHz,
DDR:533.333 MHz (1066.667 MT/s data rate) (Asynchronous),
IFC:31.250 MHz
FMAN1: 500 MHz
QMAN: 250 MHz
PME: 250 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 0a10000c 0c000000 00000000 00000000
00000010: 85000000 00404102 fc027000 21000000
00000020: 00000000 00000000 00000000 0001f002
00000030: 00000100 d556aa05 00000000 00000000
Board: HCPM-based board
(36-bit physical address map)
(devices at high phys.addresses)
PMUXCR: config QE IO clocks as GPIO's
GPIO: ready
Disable unused HW devices:
eSDHC: disable
USB-1: disable
USB-2: disable
SATA-1: disable
SATA-2: disable
DIU: disable
dual I2C 2: disable
DUART-2: disable
NAL: disable
I2C: ready
DRAM: Initializing ... using SPD
Init LEDs on I/O Expander
Config pin directions
Set ON all LEDs
Resetting the DDR3 module ... done
Detected UDIMM SP004GISLU160NH0EI
DDR caslat 7 clocks
DDR wait for D_INIT ... done.
LAW: idx 15, addr 0x0, law_sz 0x1f, trgt_if 0x10
Memory Controller 0 Slot 0: 1 rank DIMM
Memory Controller 0: number of installed DIMM's = 1
DDR TLB Warning: 2 GiB left unmapped
DDR: 4 GiB (DDR3, 64-bit, CL=7, ECC off)
Effective RAM size: 2 GiB
Memory Controller 0 err_detect: 0x00000000
Memory Probe start ...
Testing DRAM from 0x00200000 to 0x00201000
Testing DRAM from 0x10200000 to 0x10201000
Testing DRAM from 0x20200000 to 0x20201000
Testing DRAM from 0x30200000 to 0x30201000
Testing DRAM from 0x40200000 to 0x40201000
Testing DRAM from 0x50200000 to 0x50201000
Testing DRAM from 0x60200000 to 0x60201000
Testing DRAM from 0x70200000 to 0x70201000
Memory Probe finished (passed 24576, failed 0).
DRAM test successfully passed.
Go to relocate_code ...
Now running in RAM - U-Boot at: 7ff30000
List of enabled ERRATUM workarounds:
Work-around for Erratum ESDHC111 (AUTO_CMD12 support) enabled
Init I/O Expander 1
Config input data polarity
Config pins direction
Main Board presence: Yes
MALLOC: ready
Flash: 16 MiB
L2: [backside] 256 KiB enabled
Look for en_cpc option in board_hwconfig
Look for en_cpc option in cpu_hwconfig
Corenet Platform Cache: 256 KiB enabled
Using SERDES1 Protocol: 133 (0x85)
CPU up succeeded. CPU up mask is f.
Environment on NOR flash
Update 'ethaddr' with SYS MAC (f8:54:af:04:32:00)
PCIE1: disable
PCIE2: enabled
PCIE3: disable
PCIE4: disable
STDIO: ready
JUMP_TABLE: ready
In: serial
Out: serial
Err: serial
Fix environment variables ...
Update 'cardtype' from IDPROM
ENV: 'ctrl_fdt_blob' = '0xefd40000'
Fix environment variables finished.
INTERRUPT: ready
Net:
FMan ucode on NOR flash
Fman1: Uploading microcode version 107.4.2
FM1@DTSEC1 connected to MEMAC1_MDIO:0 'FSL TBI PHY'
FSL TBI PHY => perform phy config
FM1@DTSEC2 connected to MEMAC2_MDIO:0 'FSL TBI PHY'
FSL TBI PHY => perform phy config
FM1@DTSEC3 connected to MEMAC3_MDIO:0 'FSL TBI PHY'
FSL TBI PHY => perform phy config
FM1@DTSEC4 connected to MEMAC4_MDIO:0 'FSL TBI PHY'
FSL TBI PHY => perform phy config
FM1@DTSEC5 Nothing to connect
FM1@DTSEC1 [PRIME], FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5
Warning: Your board does not use generic board. Please read
doc/README.generic-board and take action. Boards not
upgraded by the late 2014 may break or be removed.
***************************************************************
HCPM U-BOOT SOFT COPY A

U-Boot 2015.01 yocto-2.0 (Jul 11 2019 - 19:06:05) v4.0.12+, Build: safe A

Board Identification information

CPU0 : T1042E Version 1.1 (0x85280211)
Core : e5500 Version 2.1 (0x80241021)
Board Type : MIO200B
Board Network Number : 228 (0xe4)
 CPM Serial Number : 503948004
CPM Card Type : 0x85cb
CPM HW Revision : B 0009 (0x00420009)
CPM HW Options : 0x000d
IO Serial Number : 503943317
IO Card Type : 0x8a54
IO HW Revision : A 0000 (0x00410000)
IO HW Options : 0x000d
IO FIPS support : disabled
***************************************************************
Running NETW Setup procedure ...

Checking Card Presence ... OK.

Set ON all LEDs
Boot Device is RCP (via backplane port)
Setup ethernet ports MACs (slot u4):
Update 'eth1addr' upon Slot# (02:02:0E:00:D0:06)
Resetting Ethernet Switch 1 ... Done.
Init Ethernet Switch 98DX106 - 10 ports managed (ID 0xD3D3 Rev 0x0)
Setup Ethernet Switch ports:
(to CODM )(SGMII, Autoneg 100BT Full) Port 0: mac status=0xe802
(to RCP-A)(1000Base-X, Fixed 1GB) Port 1: mac status=0xe00f
(to RCP-B)(1000Base-X, Fixed 1GB) Port 2: mac status=0xa40e
(to mEMAC1 'debug VLAN') (SGMII, Fixed 1GB) Port 5: mac status=0xe00f
(to mEMAC2 'backplane VLAN')(SGMII, Fixed 1GB) Port 6: mac status=0xe00f
m98dx106: VLAN ID 4091 MAC learning disable
m98dx106: VLAN ID 4092 MAC learning disable
m98dx106: VID + MAC are used for FDB lookup and learning
Setup network environment:
Set empty 'bootseq'
Update 'ipaddr' from IDPROM
Update 'ethact' to 'FM1@DTSEC2'
Clean 'ipaddr'
Clean 'bootargs'
Update 'bootpath'
Setup FPGA environment variables ... done.

NETW Setup finished.

***************************************************************
Board Status information
Presence (K3) : yes (val 1)
GA bit layout : LSB 0 (legacy)
Geographical Address : 5 (slot# 4) u4
Board installed in : chassis
Reset Reason : power
Boot Device : backplane
Boot Mode : chassis (from RCP using DHCP)
Boot Delay : 5
***************************************************************
Hit any key to stop autoboot: 0
Send BOOTP request to 0.0.0.0 ...
BOOTP broadcast 1
BOOTP secs 5
BOOTP NetOurEther 02:02:0e:00:d0:06
BOOTP uptime 5696 ms
BOOTP xid 0x0e00d006

BOOTP got xid 0x0e00d006 ... match.

Network settings after BOOTP reply:
NetServerIP : 192.168.127.17
NetOurIP : 192.168.127.41
NetOurGatewayIP : 192.168.127.128 (routers)
NetOurSubnetMask: 255.255.255.0
BootFile : /usr/st/opb/linux/release/hcpm/uboot/uImage-hcpm.bin

Update 'serverip' upon BOOTP : 192.168.127.128

Update 'ipaddr' upon BOOTP : 192.168.127.41
Update 'netmask' upon BOOTP : 255.255.255.0
Update 'bootfile' upon BOOTP : /usr/st/opb/linux/release/hcpm/uboot/uImage-hcpm.bin

SET NETW OK

>> Executing BOOTCOMMAND ...

>> Get Master Script
Using FM1@DTSEC2 device
TFTP from server 192.168.127.128; our IP address is 192.168.127.41
Filename '/usr/st/opb/linux/release/hcpm/uboot/master-script.img'.
Load address: 0x10e00000
Loading: ##
1.4 MiB/s
done
Bytes transferred = 7326 (1c9e hex)
Master Script download OK

## Checking Image at 10e00000 ...

Legacy image found
Image Name: master-script
Created: 2025-02-10 22:11:48 UTC
Image Type: PowerPC Linux Script (uncompressed)
Data Size: 7262 Bytes = 7.1 KiB
Load Address: 00000000
Entry Point: 00000000
Contents:
Image 0: 7254 Bytes = 7.1 KiB
Verifying Checksum ... Legacy image is OK

override_bootpath=
othbootargs=
othbootargs2=

>> Executing Master Script ...

## Executing script at 10e00000

Start Master-script execution

--- input params ---
netretry=yes
bootdev=backplane
app_user=release
cardtype=8a54
u_name=hcpm
--------------------
systype=uboot
Get alternative master script
Using FM1@DTSEC2 device
TFTP from server 192.168.127.128; our IP address is 192.168.127.41
Filename '/usr/st/opb/linux/slot4/release/hcpm/uboot/master-script.img'.
Load address: 0x10f00000
Loading: *
TFTP error: 'Access violation' (2)
Not retrying...
FINISHED
FAIL
Alternative master script NOT found
Set master_path to /usr/st/opb/linux/release/hcpm/uboot/
Get board-names script
Using FM1@DTSEC2 device
TFTP from server 192.168.127.128; our IP address is 192.168.127.41
Filename '/usr/st/opb/linux/release/hcpm/uboot//board-names.img'.
Load address: 0x11000000
Loading: #
1.5 MiB/s
done
Bytes transferred = 3086 (c0e hex)
FINISHED
OK

## Checking Image at 11000000 ...

Legacy image found
Image Name: board-names
Created: 2025-02-10 22:11:48 UTC
Image Type: PowerPC Linux Script (uncompressed)
Data Size: 3022 Bytes = 3 KiB
Load Address: 00000000
Entry Point: 00000000
Contents:
Image 0: 3014 Bytes = 2.9 KiB
Verifying Checksum ... Legacy image is OK
Execute board-names script
## Executing script at 11000000

## Script at 11000000 finished with rcode 0.

cardname=mio200b
--------------------
Get mio200b board script
Using FM1@DTSEC2 device
TFTP from server 192.168.127.128; our IP address is 192.168.127.41
Filename '/usr/st/opb/linux/release/hcpm/uboot//mio200b.img'.
Load address: 0x11000000
Loading: #
34.2 KiB/s
done
Bytes transferred = 351 (15f hex)
FINISHED
OK

## Checking Image at 11000000 ...

Legacy image found
Image Name: mio200b
Created: 2025-02-10 22:16:42 UTC
Image Type: PowerPC Linux Script (uncompressed)
Data Size: 287 Bytes = 287 Bytes
Load Address: 00000000
Entry Point: 00000000
Contents:
Image 0: 279 Bytes = 279 Bytes
 Verifying Checksum ... Legacy image is OK
Execute board script
## Executing script at 11000000

## Script at 11000000 finished with rcode 0.

Setting main boot path /usr/st/opb/linux

bootpath=/usr/st/opb/linux/release/mio200b/uboot
bootfile=/usr/st/opb/linux/release/mio200b/uboot/uImage-hcpm.bin
bootcmd=run boot_std
--------------------
Running U-boot version is v4.0.12+
Required U-boot version is v4.0.12+
No need to upgrade u-boot
Master-script Done!

## Script at 10e00000 finished with rcode 0.

>> Master Script finished.

>> Executing Post Master Script ...

cardname=mio200b
app_user=release
bootpath=/usr/st/opb/linux/release/mio200b/uboot
cfpgafile=/usr/st/opb/linux/release/mio200b/uboot/MIO200CTR.UMD
othbootargs=
othbootargs2=panic=10 cardname=mio200b ftpserverip=192.168.127.128
ftpserverport=3021 app_prefix=/usr/st/opb/linux
alt_app_prefix=/usr/st/opb/linux/slot4 maxcpus=1
bootseq=fpgaim burn 0;if fpgaim stat 0;then;mw.w 0xe0000006 0x0;mw.w 0xe0000016
0x0;mw.w 0xe0000026 0x01;mw.w 0xe0000006 0x73;fi;
override_bootseq=

Update 'bootargs' (bootdev is backplane) ... new 'bootargs' size: 516 bytes.

bootargs=rw
ip=192.168.127.41:192.168.127.128:192.168.127.128:255.255.255.0:hcpm:eth1:off
ip_ext=192.168.152.228,147.234.244.143,192.168.153.254,255.255.254.0,hcpm,eth0,off
app_user=release cardtype=8a54 ddrsize=0x100000000 slot=4 uslot=4 opmode=backplane
rstreason=power bootver=v4.0.12+ uname=hcpm build=safe copyid=1 udate=Jul/11/2019
utime=19.06.05 console=ttyS0,115200 panic=10 cardname=mio200b
ftpserverip=192.168.127.128 ftpserverport=3021 app_prefix=/usr/st/opb/linux
alt_app_prefix=/usr/st/opb/linux/slot4 maxcpus=1

>> Post Master Script finished.

>> Executing Boot Sequence ...
Using FM1@DTSEC2 device
TFTP from server 192.168.127.128; our IP address is 192.168.127.41
Filename '/usr/st/opb/linux/release/mio200b/uboot/MIO200CTR.UMD'.
Load address: 0x10d00000
Loading: #################################################################
###################################
1.5 MiB/s
done
Bytes transferred = 511880 (7cf88 hex)
TFTP image transfer succeeded.
Skip UMD image header (1024 bytes).
*** FPGA loading start ... ***
FPGA image file: /usr/st/opb/linux/release/mio200b/uboot/MIO200CTR.UMD
Loading FPGA Device 16976384... perform serial
loading ......................................... OK? ... OK
Done.
FPGA reset sequence is done.
FPGA image version is 0x03 (3).
*** FPGA loading succeeded ***

FPGA 0 load status: OK

>> Boot Sequence finished.

Using FM1@DTSEC2 device

TFTP from server 192.168.127.128; our IP address is 192.168.127.41
Filename '/usr/st/opb/linux/release/mio200b/uboot/uImage-hcpm.bin'.
Load address: 0x11000000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
###########################################################
1.6 MiB/s
done
Bytes transferred = 4290585 (417819 hex)

BootFile download OK

## Checking Image at 11000000 ...

Legacy image found
Image Name: Linux-4.1.35-2-hcpm-rt41
Created: 2020-12-06 4:53:28 UTC
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 4290521 Bytes = 4.1 MiB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... Legacy image is OK

Using FM1@DTSEC2 device

TFTP from server 192.168.127.128; our IP address is 192.168.127.41
Filename '/usr/st/opb/linux/release/mio200b/uboot/uImage-hcpm.dtb'.
Load address: 0x10c00000
Loading: ########
1.7 MiB/s
done
Bytes transferred = 36394 (8e2a hex)

FDT download OK

## Checking Image at 10c00000 ...

FIT image found
Bad FIT image format!

Using FM1@DTSEC2 device

TFTP from server 192.168.127.128; our IP address is 192.168.127.41
Filename '/usr/st/opb/linux/release/mio200b/uboot/io-image-hcpm.cpio.gz.u-boot'.
Load address: 0x13000000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
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 #################################################################
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###################################################################################
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###################
 1.4 MiB/s
done
Bytes transferred = 37640806 (23e5a66 hex)
InitRD download OK

## bootm - boot application image from memory ...

WARNING: adjusting available memory to 30000000
## Booting kernel from Legacy Image at 11000000 ...
Image Name: Linux-4.1.35-2-hcpm-rt41
Created: 2020-12-06 4:53:28 UTC
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 4290521 Bytes = 4.1 MiB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 13000000 ...
Image Name: io-image-hcpm64-9.5MY16-344976-2
Created: 2020-12-06 5:15:51 UTC
Image Type: PowerPC Linux RAMDisk Image (gzip compressed)
Data Size: 37640742 Bytes = 35.9 MiB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
## Flattened Device Tree blob at 10c00000
Booting using the fdt blob at 0x10c00000
Uncompressing Kernel Image ... OK
Loading Ramdisk to 2dc1a000, end 2ffffa26 ... OK
Loading Device Tree to 0ffe3000, end 0fffee29 ... OK
FDT fixup: memory base = 0x0, size = 0x100000000
FDT fixup: create 'fips' node
## Transferring control to Linux (at address 00000000) ...
## Booting Linux using OF flat tree at 0ffe3000 (r3), bootm_mapsize 10000000
(r7) ...

Reserved memory: initialized node bman-fbpr, compatible id fsl,bman-fbpr

Reserved memory: initialized node qman-fqd, compatible id fsl,qman-fqd
Reserved memory: initialized node qman-pfdr, compatible id fsl,qman-pfdr
Reserved memory: initialized node pme-pdsr, compatible id fsl,pme-pdsr
Reserved memory: initialized node pme-sre, compatible id fsl,pme-sre
Using CoreNet Generic machine description
MMU: Supported page sizes
4 KB as direct
4096 KB as direct
16384 KB as direct
65536 KB as direct
262144 KB as direct
1048576 KB as direct
MMU: Book3E HW tablewalk not supported
Found initrd at 0xc00000002dc1a000:0xc00000002ffffa26
bootconsole [udbg0] enabled
CPU maps initialized for 1 thread per core
Starting Linux PPC64 #1 SMP PREEMPT Sun Dec 6 06:53:10 IST 2020
-----------------------------------------------------
ppc64_pft_size = 0x0
phys_mem_size = 0x100000000
dcache_line_size = 0x40
icache_line_size = 0x40
cpu_features = 0x00180400581802c0
possible = 0x00180480581802c0
always = 0x00180400581802c0
cpu_user_features = 0xcc008000 0x08000000
mmu_features = 0x000a0010
firmware_features = 0x0000000000000000
-----------------------------------------------------
<- setup_system()
Linux version 4.1.35-2-hcpm-rt41 (apinteg2@gen11) (gcc version 5.2.0 (GCC) ) #1 SMP
PREEMPT Sun Dec 6 06:53:10 IST 2020
CoreNet Generic board
Zone ranges:
DMA [mem 0x0000000000000000-0x000000007fffffff]
DMA32 empty
Normal [mem 0x0000000080000000-0x00000000ffffffff]
Movable zone start for each node
Early memory node ranges
node 0: [mem 0x0000000000000000-0x00000000ffffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x00000000ffffffff]
MMU: Allocated 2112 bytes of context maps for 255 contexts
PERCPU: Embedded 16 pages/cpu @c0000000ffe00000 s25432 r0 d40104 u262144
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 1034240
Kernel command line: rw
ip=192.168.127.41:192.168.127.128:192.168.127.128:255.255.255.0:hcpm:eth1:off
ip_ext=192.168.152.228,147.234.244.143,192.168.153.254,255.255.254.0,hcpm,eth0,off
app_user=release cardtype=8a54 ddrsize=0x100000000 slot=4 uslot=4 opmode=backplane
rstreason=power bootver=v4.0.12+ uname=hcpm build=safe copyid=1 udate=Jul/11/2019
utime=19.06.05 console=ttyS0,115200 panic=10 cardname=mio200b
ftpserverip=192.168.127.128 ftpserverport=3021 app_prefix=/usr/st/opb/linux
alt_app_prefix=/usr/st/opb/linux/slot4 maxcpus=1
log_buf_len individual max cpu contribution: 16384 bytes
log_buf_len total cpu_extra contributions: 49152 bytes
log_buf_len min size: 16384 bytes
log_buf_len: 65536 bytes
early log buf free: 12128(74%)
PID hash table entries: 4096 (order: 3, 32768 bytes)
Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
Sorting __ex_table...
Memory: 3931636K/4194304K available (6708K kernel code, 1036K rwdata, 2540K rodata,
316K init, 716K bss, 262668K reserved, 0K cma-reserved)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
Preemptible hierarchical RCU implementation.
RCU kthread priority: 1.
NR_IRQS:512 nr_irqs:512 16
mpic: Setting up MPIC " OpenPIC " version 1.2 at ffe040000, max 4 CPUs
mpic: ISU size: 512, shift: 9, mask: 1ff
mpic: Initializing for 512 sources
clocksource timebase: mask: 0xffffffffffffffff max_cycles: 0xe6a171046,
max_idle_ns: 881590405314 ns
clocksource: timebase mult[10000000] shift[23] registered
Console: colour dummy device 80x25
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 8192 (order: 4, 65536 bytes)
Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes)
e500 family performance monitor hardware support registered
Brought up 1 CPUs
devtmpfs: initialized
clocksource jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns:
1911260446275000 ns
NET: Registered protocol family 16
Bman ver:0a02,02,01
qman-fqd addr 0x00000000ff000000 size 0x800000
qman-pfdr addr 0x00000000fc000000 size 0x2000000
Qman ver:0a01,03,01,03
Found FSL PCI host bridge at 0x0000000ffe250000. Firmware bus number: 0->255
PCI host bridge /pcie@ffe250000 ranges:
MEM 0x0000000c00000000..0x0000000c5fffffff -> 0x0000000080000000
MEM 0x0000000c60000000..0x0000000c7fffffff -> 0x00000000e0000000 Prefetch
/pcie@ffe250000: PCICSRBAR @ 0x7f000000
setup_pci_atmu: end of DRAM 100000000
/pcie@ffe250000: Setup 64-bit PCI DMA window
/pcie@ffe250000: DMA window size is 0x7f000000
PCI Inbound ATMUs:
ATMU_0: tar=00000000, wbar=00000000, wbear=00000000, war=00000000
ATMU_1: tar=00000000, wbar=10000000, wbear=00000000, war=a0f5501f
ATMU_2: tar=00000000, wbar=00000000, wbear=00000000, war=a0f5501e
ATMU_3: tar=00ffe000, wbar=00000000, wbear=00000000, war=80e44017
PCI Outbound ATMUs:
ATMU_0: tar=00000000, tear=00000000, wbar=00000000, war=80044027
ATMU_1: tar=00080000, tear=00000000, wbar=00c00000, war=8004401d
ATMU_2: tar=000c0000, tear=00000000, wbar=00c40000, war=8004401c
ATMU_3: tar=000e0000, tear=00000000, wbar=00c60000, war=9004401c
ATMU_4: tar=00000000, tear=00000000, wbar=00000000, war=00000000
software IO TLB [mem 0xf2e00000-0xf6e00000] (64MB) mapped at [c0000000f2e00000-
c0000000f6dfffff]
PCI: Probing PCI hardware
PCI: I/O resource not set for host bridge /pcie@ffe250000 (domain 0)
fsl-pci ffe250000.pcie: PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [mem 0xc00000000-0xc5fffffff] (bus address
[0x80000000-0xdfffffff])
pci_bus 0000:00: root bus resource [mem 0xc60000000-0xc7fffffff pref] (bus address
[0xe0000000-0xffffffff])
pci_bus 0000:00: root bus resource [bus 00-ff]
pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
PCIe FIXUP: dev 0000:01:00.0 FDT node /PLX8624/bus01/dev00
pci 0000:00:00.0: PCI bridge to [bus 01-ff]
PCIe FIXUP: dev 0000:02:01.0 FDT node /PLX8624/bus02/dev01
PCIe FIXUP: dev 0000:02:04.0 FDT node /PLX8624/bus02/dev04
PCIe FIXUP: dev 0000:02:05.0 FDT node /PLX8624/bus02/dev05
PCIe FIXUP: dev 0000:02:06.0 FDT node /PLX8624/bus02/dev06
PCIe FIXUP: dev 0000:02:08.0 FDT node /PLX8624/bus02/dev08
PCIe FIXUP: dev 0000:02:09.0 FDT node /PLX8624/bus02/dev09
pci 0000:01:00.0: PCI bridge to [bus 02-08]
pci 0000:02:01.0: PCI bridge to [bus 03]
pci 0000:02:04.0: PCI bridge to [bus 04]
pci 0000:02:05.0: PCI bridge to [bus 05]
pci 0000:02:06.0: PCI bridge to [bus 06]
pci 0000:02:08.0: PCI bridge to [bus 07]
pci 0000:02:09.0: PCI bridge to [bus 08]
PCI: Cannot allocate resource region 0 of device 0000:00:00.0, will remap
PCI: Cannot allocate resource region 0 of device 0000:06:00.0, will remap
PCI: Cannot allocate resource region 2 of device 0000:06:00.0, will remap
PCI: Cannot allocate resource region 0 of device 0000:06:00.1, will remap
PCI: Cannot allocate resource region 2 of device 0000:06:00.1, will remap
pci 0000:00:00.0: BAR 0: no space for [mem size 0x01000000]
pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x01000000]
pci 0000:00:00.0: BAR 7: no space for [io size 0x3000]
pci 0000:00:00.0: BAR 7: failed to assign [io size 0x3000]
pci 0000:00:00.0: BAR 0: no space for [mem size 0x01000000]
pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x01000000]
pci 0000:00:00.0: BAR 7: no space for [io size 0x3000]
pci 0000:00:00.0: BAR 7: failed to assign [io size 0x3000]
pci 0000:01:00.0: BAR 7: no space for [io size 0x3000]
pci 0000:01:00.0: BAR 7: failed to assign [io size 0x3000]
pci 0000:01:00.0: BAR 7: no space for [io size 0x3000]
pci 0000:01:00.0: BAR 7: failed to assign [io size 0x3000]
pci 0000:02:01.0: BAR 8: assigned [mem 0xc00100000-0xc002fffff]
pci 0000:02:01.0: BAR 9: assigned [mem 0xc62000000-0xc621fffff 64bit pref]
pci 0000:02:05.0: BAR 9: assigned [mem 0xc62200000-0xc623fffff 64bit pref]
pci 0000:02:09.0: BAR 9: assigned [mem 0xc62400000-0xc625fffff 64bit pref]
pci 0000:02:01.0: BAR 7: no space for [io size 0x1000]
pci 0000:02:01.0: BAR 7: failed to assign [io size 0x1000]
pci 0000:02:05.0: BAR 7: no space for [io size 0x1000]
pci 0000:02:05.0: BAR 7: failed to assign [io size 0x1000]
pci 0000:02:09.0: BAR 7: no space for [io size 0x1000]
pci 0000:02:09.0: BAR 7: failed to assign [io size 0x1000]
pci 0000:02:09.0: BAR 7: no space for [io size 0x1000]
pci 0000:02:09.0: BAR 7: failed to assign [io size 0x1000]
pci 0000:02:05.0: BAR 7: no space for [io size 0x1000]
pci 0000:02:05.0: BAR 7: failed to assign [io size 0x1000]
pci 0000:02:01.0: BAR 7: no space for [io size 0x1000]
pci 0000:02:01.0: BAR 7: failed to assign [io size 0x1000]
pci 0000:02:01.0: PCI bridge to [bus 03]
pci 0000:02:01.0: bridge window [mem 0xc00100000-0xc002fffff]
pci 0000:02:01.0: bridge window [mem 0xc62000000-0xc621fffff 64bit pref]
pci 0000:02:04.0: PCI bridge to [bus 04]
pci 0000:02:05.0: PCI bridge to [bus 05]
pci 0000:02:05.0: bridge window [mem 0xc10000000-0xc1fffffff]
pci 0000:02:05.0: bridge window [mem 0xc62200000-0xc623fffff 64bit pref]
pci 0000:06:00.0: BAR 2: assigned [mem 0xc60000000-0xc607fffff 64bit pref]
pci 0000:06:00.1: BAR 2: assigned [mem 0xc60800000-0xc60ffffff 64bit pref]
pci 0000:06:00.0: BAR 0: assigned [mem 0xc61000000-0xc61007fff 64bit pref]
pci 0000:06:00.1: BAR 0: assigned [mem 0xc61008000-0xc6100ffff 64bit pref]
pci 0000:02:06.0: PCI bridge to [bus 06]
pci 0000:02:06.0: bridge window [mem 0xc20000000-0xc2fffffff]
pci 0000:02:06.0: bridge window [mem 0xc60000000-0xc61ffffff 64bit pref]
pci 0000:02:08.0: PCI bridge to [bus 07]
pci 0000:02:08.0: bridge window [mem 0xc30000000-0xc3fffffff]
pci 0000:02:09.0: PCI bridge to [bus 08]
pci 0000:02:09.0: bridge window [mem 0xc40000000-0xc4fffffff]
pci 0000:02:09.0: bridge window [mem 0xc62400000-0xc625fffff 64bit pref]
pci 0000:01:00.0: PCI bridge to [bus 02-08]
pci 0000:01:00.0: bridge window [mem 0xc00100000-0xc5fffffff]
pci 0000:01:00.0: bridge window [mem 0xc60000000-0xc7fffffff 64bit pref]
pci 0000:00:00.0: PCI bridge to [bus 01-08]
pci 0000:00:00.0: bridge window [mem 0xc00000000-0xc5fffffff]
pci 0000:00:00.0: bridge window [mem 0xc60000000-0xc7fffffff 64bit pref]
pci_bus 0000:00: Some PCI device resources are unassigned, try booting with
pci=realloc
Freescale Elo series DMA driver
fsl-elo-dma ffe100300.dma: #0 (fsl,eloplus-dma-channel), irq 28
fsl-elo-dma ffe100300.dma: #1 (fsl,eloplus-dma-channel), irq 29
fsl-elo-dma ffe100300.dma: #2 (fsl,eloplus-dma-channel), irq 30
fsl-elo-dma ffe100300.dma: #3 (fsl,eloplus-dma-channel), irq 31
fsl-elo-dma ffe100300.dma: #4 (fsl,eloplus-dma-channel), irq 76
fsl-elo-dma ffe100300.dma: #5 (fsl,eloplus-dma-channel), irq 77
fsl-elo-dma ffe100300.dma: #6 (fsl,eloplus-dma-channel), irq 78
fsl-elo-dma ffe100300.dma: #7 (fsl,eloplus-dma-channel), irq 79
fsl-elo-dma ffe101300.dma: #0 (fsl,eloplus-dma-channel), irq 32
fsl-elo-dma ffe101300.dma: #1 (fsl,eloplus-dma-channel), irq 33
fsl-elo-dma ffe101300.dma: #2 (fsl,eloplus-dma-channel), irq 34
fsl-elo-dma ffe101300.dma: #3 (fsl,eloplus-dma-channel), irq 35
fsl-elo-dma ffe101300.dma: #4 (fsl,eloplus-dma-channel), irq 80
fsl-elo-dma ffe101300.dma: #5 (fsl,eloplus-dma-channel), irq 81
fsl-elo-dma ffe101300.dma: #6 (fsl,eloplus-dma-channel), irq 82
fsl-elo-dma ffe101300.dma: #7 (fsl,eloplus-dma-channel), irq 83
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti
<giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
bman-fbpr addr 0x00000000fe000000 size 0x1000000
Bman err interrupt handler present
Bman portal (shared) initialised, cpu 0
Bman portal (slave) initialised, cpu 1
Bman portal (slave) initialised, cpu 2
Bman portal (slave) initialised, cpu 3
Bman portals initialised
Qman err interrupt handler present
QMan: Allocated lookup table at 8000000000002000, entry count 131073
Qman portal (shared) initialised, cpu 0
Qman portal (slave) initialised, cpu 1
Qman portal (slave) initialised, cpu 2
Qman portal (slave) initialised, cpu 3
Qman portals initialised
Bman: BPID allocator includes range 32:32
Qman: FQID allocator includes range 256:512
Qman: FQID allocator includes range 32768:32768
Qman: CGRID allocator includes range 0:256
Qman: pool channel allocator includes range 1025:15
No USDPAA memory, no 'fsl,usdpaa-mem' in device-tree
fsl-ifc ffe124000.localbus: Freescale Integrated Flash Controller
fsl-ifc ffe124000.localbus: IFC version 1.3, 8 banks
Switched to clocksource timebase
NET: Registered protocol family 2
TCP established hash table entries: 32768 (order: 6, 262144 bytes)
TCP bind hash table entries: 32768 (order: 7, 524288 bytes)
TCP: Hash tables configured (established 32768 bind 32768)
UDP hash table entries: 2048 (order: 5, 131072 bytes)
UDP-Lite hash table entries: 2048 (order: 5, 131072 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Unpacking initramfs...
Freeing initrd memory: 36756K (c00000002dc1a000 - c00000002ffff000)
futex hash table entries: 1024 (order: 4, 65536 bytes)
HugeTLB registered 4 MB page size, pre-allocated 0 pages
HugeTLB registered 16 MB page size, pre-allocated 0 pages
HugeTLB registered 64 MB page size, pre-allocated 0 pages
HugeTLB registered 256 MB page size, pre-allocated 0 pages
HugeTLB registered 1 GB page size, pre-allocated 0 pages
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
Serial: 8250/16550 driver, 1 ports, IRQ sharing enabled
console [ttyS0] disabled
serial8250.0: ttyS0 at MMIO 0xffe11c500 (irq = 36, base_baud = 15625000) is a
16550A_FSL64
console [ttyS0] enabled
console [ttyS0] enabled
bootconsole [udbg0] disabled
bootconsole [udbg0] disabled
ePAPR hypervisor byte channel driver
loop: module loaded
fef000000.nor: Found 1 x16 devices at 0x0 in 16-bit bank. Manufacturer ID 0x000001
Chip ID 0x002101
Amd/Fujitsu Extended Query Table at 0x0040
Amd/Fujitsu Extended Query version 1.5.
number of CFI chips: 1
14 ofpart partitions found on MTD device fef000000.nor
Creating 14 MTD partitions on "fef000000.nor":
0x000000000000-0x000000bc0000 : "user"
0x000000bc0000-0x000000c00000 : "pubkey_h"
0x000000c00000-0x000000c40000 : "user1"
0x000000c40000-0x000000c80000 : "env"
0x000000c80000-0x000000d40000 : "UBoot-A"
0x000000e80000-0x000000ec0000 : "pubkey_a"
0x000000d80000-0x000000e40000 : "UBoot-B"
0x000000e80000-0x000000ec0000 : "pubkey_b"
0x000000e80000-0x000000ec0000 : "default-boot-id"
0x000000ec0000-0x000000f00000 : "user2"
0x000000f00000-0x000000f40000 : "FMan"
0x000000f40000-0x000001000000 : "U-Boot"
0x000000c00000-0x000000e00000 : "RomBootHigh"
0x000000e00000-0x000001000000 : "RomBootLow"
libphy: Fixed MDIO Bus: probed
libphy: Freescale XGMAC MDIO Bus: probed
libphy: Freescale XGMAC MDIO Bus: probed
libphy: Freescale XGMAC MDIO Bus: probed
libphy: Freescale XGMAC MDIO Bus: probed
libphy: Freescale XGMAC MDIO Bus: probed
libphy: Freescale XGMAC MDIO Bus: probed
Freescale FM module, FMD API version 21.1.0
Freescale FM Ports module
fsl_mac: fsl_mac: FSL FMan MAC API based driver
SetupSgmiiInternalPhy:92 WITH WORKAROUND to disable autoneg for memac for macId 0
fsl_mac ffe4e0000.ethernet: FMan MEMAC
fsl_mac ffe4e0000.ethernet: FMan MAC address: f8:54:af:04:32:00
SetupSgmiiInternalPhy:92 WITH WORKAROUND to disable autoneg for memac for macId 1
fsl_mac ffe4e2000.ethernet: FMan MEMAC
fsl_mac ffe4e2000.ethernet: FMan MAC address: 02:02:0e:00:d0:06
fsl_mac ffe4e4000.ethernet:
of_get_mac_address(/soc@ffe000000/fman@400000/ethernet@e4000) failed
fsl_mac: probe of ffe4e4000.ethernet failed with error -22
fsl_dpa: FSL DPAA Ethernet driver
fsl_dpa: fsl_dpa: Probed interface eth0
fsl_dpa: fsl_dpa: Probed interface eth1
fsl_dpa fsl,dpaa:ethernet@2: dev_get_drvdata(ffe4e4000.ethernet) failed
fsl_dpa: probe of fsl,dpaa:ethernet@2 failed with error -22
fsl_advanced: FSL DPAA Advanced drivers:
fsl_proxy: FSL DPAA Proxy initialization driver
fsl_dpa_shared: FSL DPAA Shared Ethernet driver
fsl_dpa_macless: FSL DPAA MACless Ethernet driver
fsl_oh: FSL FMan Offline Parsing port driver
fsl_oh fsl,dpaa:dpa-fman0-oh@2: Found OH node handle compatible with fsl,dpa-oh
fsl_oh fsl,dpaa:dpa-fman0-oh@2: Allocating 0 ingress frame queues duples
fsl_oh fsl,dpaa:dpa-fman0-oh@2: OH port /soc@ffe000000/fman@400000/port@83000
enabled.
fsl_oh fsl,dpaa:dpa-fman0-oh@2: Default egress frame queue: 105
fsl_oh fsl,dpaa:dpa-fman0-oh@2: Default error frame queue: 104
fsl_oh fsl,dpaa:dpa-fman0-oh@2: Initialized queues:
i2c /dev entries driver
mpc-i2c ffe118000.i2c: timeout 1000000 us
mpc-i2c ffe118100.i2c: timeout 1000000 us
platform caam_qi: Linux CAAM Queue I/F driver initialised
caam ffe300000.crypto: Entropy delay = 3200
caam ffe300000.crypto: Instantiated RNG4 SH0
caam ffe300000.crypto: Instantiated RNG4 SH1
caam ffe300000.crypto: device ID = 0x0a12040000000000 (Era 6)
caam ffe300000.crypto: job rings = 4, qi = 1
caam algorithms registered in /proc/crypto
platform caam_qi: algorithms registered in /proc/crypto
caam_jr ffe301000.jr: registering rng-caam
caam ffe300000.crypto: fsl,sec-v5.0 algorithms registered in /proc/crypto
Freescale USDPAA process driver
fsl-usdpaa: no region found
Freescale USDPAA process IRQ driver
dce_sys_init done!
fsl-pme ffe316000.pme: ver: 0x00100202
Freescale pme2 db driver
Freescale pme2 scan driver
fsl-pme2-scan: device pme_scan registered
ipip: IPv4 over IPv4 tunneling driver
Initializing XFRM netlink socket
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 15
8021q: 802.1Q VLAN Support v1.8
Key type dns_resolver registered
fsl_generic: FSL DPAA Generic Ethernet driver
IP-Config: Complete:
device=eth1, hwaddr=02:02:0e:00:d0:06, ipaddr=192.168.127.41,
mask=255.255.255.0, gw=192.168.127.128
host=hcpm, domain=, nis-domain=(none)
bootserver=192.168.127.128, rootserver=192.168.127.128, rootpath=
Freeing unused kernel memory: 316K (c00000000090e000 - c00000000095d000)
mkdir: can't create directory '/var/log': No such file or directory
/init2: start /sbin/init
INIT: version 2.88 booting
Starting random number generator daemon.
random: dd urandom read with 65 bits of entropy available
Sun Dec 6 05:14:56 UTC 2020
Running postinst /etc/rpm-postinsts/100-sysvinit-inittab...
Running postinst /etc/rpm-postinsts/101-sysconfig-hcpm-iox-app-dnld...
Running postinst /etc/rpm-postinsts/102-sysconfig-hcpm-iox-app-dnld...
Running postinst /etc/rpm-postinsts/103-cryptodev-qoriq-module...
cryptodev: driver 1.8 loaded.
update-rc.d: /etc/init.d/run-postinsts exists during rc.d purge (continuing)
Removing any system startup links for run-postinsts ...
/etc/rcS.d/S99run-postinsts
INIT: Entering runlevel: 5
/etc/init.d/iox-app-dnld start
signature will NOT be checked
wget -r --preserve-permissions -nH -nv --cut-dirs=7
ftp://192.168.127.128:3021/usr/st/opb/linux/release/mio200b/app.tar
2020-12-06 05:14:56 URL:
ftp://192.168.127.128:3021/usr/st/opb/linux/release/mio200b/app.tar [1260] ->
".listing" [1]
2020-12-06 05:15:04 URL:
ftp://192.168.127.128:3021/usr/st/opb/linux/release/mio200b/app.tar [45675194] ->
"app.tar" [1]
FINISHED --2020-12-06 05:15:04--
Total wall clock time: 7.9s
Downloaded: 1 files, 44M in 7.8s (5.56 MB/s)
iox-app-dnld: WGET1_ERR=0
./
./Mio200BBoard.e5500lnx64.Release
tar: ./Mio200BBoard.e5500lnx64.Release: time stamp 2025-02-10 22:16:34 is
131994085.494673795 s in the future
./fpga/
./fpga/hyphy_flex_fw_app.mem
tar: ./fpga/hyphy_flex_fw_app.mem: time stamp 2025-02-10 22:16:38 is
131994089.484343705 s in the future
./fpga/hyphy_jmpaddr.dat
tar: ./fpga/hyphy_jmpaddr.dat: time stamp 2025-02-10 22:16:38 is
131994089.483983065 s in the future
./fpga/g4_fw_app_revb.mem
tar: ./fpga/g4_fw_app_revb.mem: time stamp 2025-02-10 22:16:38 is
131994089.45349721 s in the future
./fpga/MIO200CTR.UMD
tar: ./fpga/MIO200CTR.UMD: time stamp 2025-02-10 22:16:38 is 131994089.437433642 s
in the future
./fpga/HARRIET.UMD
tar: ./fpga/HARRIET.UMD: time stamp 2025-02-10 22:16:38 is 131994089.000724021 s in
the future
./fpga/MIO200SECCTRL.EXO
tar: ./fpga/MIO200SECCTRL.EXO: time stamp 2025-02-10 22:16:38 is
131994088.978189823 s in the future
./fpga/ac400zrqdd_fw.ackit
tar: ./fpga/ac400zrqdd_fw.ackit: time stamp 2025-02-10 22:16:39 is
131994089.907831481 s in the future
./Mio200BITTestList.csv
tar: ./fpga: time stamp 2025-02-10 22:16:39 is 131994089.907459128 s in the future
tar: ./Mio200BITTestList.csv: time stamp 2025-02-10 22:16:38 is 131994088.907288536
s in the future
./Ac400ZrQDDOpticalParams.csv
tar: ./Ac400ZrQDDOpticalParams.csv: time stamp 2025-02-10 22:16:38 is
131994088.905861463 s in the future
./TsensFile.txt
tar: ./TsensFile.txt: time stamp 2025-02-10 22:16:38 is 131994088.905467446 s in
the future
./BcmFiles/
./BcmFiles/DNX-Devices.xml
tar: ./BcmFiles/DNX-Devices.xml: time stamp 2025-02-10 22:16:38 is
131994088.905269526 s in the future
./BcmFiles/jericho/
./BcmFiles/jericho/DebugSignals-ERPP.xml
tar: ./BcmFiles/jericho/DebugSignals-ERPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.905054262 s in the future
./BcmFiles/jericho/SignalStructures.xml
tar: ./BcmFiles/jericho/SignalStructures.xml: time stamp 2025-02-10 22:16:38 is
131994088.903794229 s in the future
./BcmFiles/jericho/DebugSignals-IRPP.xml
tar: ./BcmFiles/jericho/DebugSignals-IRPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.90166645 s in the future
./BcmFiles/jericho/DebugSignals-ETPP.xml
tar: ./BcmFiles/jericho/DebugSignals-ETPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.900889106 s in the future
./BcmFiles/jericho/PP.xml
tar: ./BcmFiles/jericho/PP.xml: time stamp 2025-02-10 22:16:38 is
131994088.900216433 s in the future
./BcmFiles/qax/
tar: ./BcmFiles/jericho: time stamp 2025-02-10 22:16:38 is 131994088.89967336 s in
the future
./BcmFiles/qax/SignalStructures.xml
tar: ./BcmFiles/qax/SignalStructures.xml: time stamp 2025-02-10 22:16:38 is
131994088.898479151 s in the future
./BcmFiles/qax/PP.xml
tar: ./BcmFiles/qax/PP.xml: time stamp 2025-02-10 22:16:38 is 131994088.897822031 s
in the future
./BcmFiles/qax/DebugSignals-ETPP.xml
tar: ./BcmFiles/qax/DebugSignals-ETPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.897152142 s in the future
./BcmFiles/qax/DebugSignals-IRPP.xml
tar: ./BcmFiles/qax/DebugSignals-IRPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.894927052 s in the future
./BcmFiles/qax/DebugSignals-ERPP.xml
tar: ./BcmFiles/qax/DebugSignals-ERPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.893845803 s in the future
./BcmFiles/arad/
tar: ./BcmFiles/qax: time stamp 2025-02-10 22:16:38 is 131994088.893244586 s in the
future
./BcmFiles/arad/PP.xml
tar: ./BcmFiles/arad/PP.xml: time stamp 2025-02-10 22:16:38 is 131994088.892640233
s in the future
./BcmFiles/arad/DebugSignals-ERPP.xml
tar: ./BcmFiles/arad/DebugSignals-ERPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.892084169 s in the future
./BcmFiles/arad/SignalStructures.xml
tar: ./BcmFiles/arad/SignalStructures.xml: time stamp 2025-02-10 22:16:38 is
131994088.890441895 s in the future
./BcmFiles/arad/DebugSignals-IRPP.xml
tar: ./BcmFiles/arad/DebugSignals-IRPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.888527237 s in the future
./BcmFiles/arad/DebugSignals-ETPP.xml
tar: ./BcmFiles/arad/DebugSignals-ETPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.8876209 s in the future
./BcmFiles/NetworkStructures.xml
tar: ./BcmFiles/arad: time stamp 2025-02-10 22:16:38 is 131994088.886101635 s in
the future
tar: ./BcmFiles/NetworkStructures.xml: time stamp 2025-02-10 22:16:38 is
131994088.885608098 s in the future
./BcmFiles/AccessObjects.xml
tar: ./BcmFiles/AccessObjects.xml: time stamp 2025-02-10 22:16:38 is
131994088.884867138 s in the future
./BcmFiles/qax_b0/
./BcmFiles/qax_b0/DebugSignals-ERPP.xml
tar: ./BcmFiles/qax_b0/DebugSignals-ERPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.88333536 s in the future
./BcmFiles/qax_b0/SignalStructures.xml
tar: ./BcmFiles/qax_b0/SignalStructures.xml: time stamp 2025-02-10 22:16:38 is
131994088.882482367 s in the future
./BcmFiles/qax_b0/DebugSignals-IRPP.xml
tar: ./BcmFiles/qax_b0/DebugSignals-IRPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.879813853 s in the future
./BcmFiles/qax_b0/DebugSignals-ETPP.xml
tar: ./BcmFiles/qax_b0/DebugSignals-ETPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.878861372 s in the future
./BcmFiles/qax_b0/PP.xml
tar: ./BcmFiles/qax_b0/PP.xml: time stamp 2025-02-10 22:16:38 is
131994088.878139611 s in the future
./BcmFiles/aradplus/
tar: ./BcmFiles/qax_b0: time stamp 2025-02-10 22:16:38 is 131994088.877664506 s in
the future
./BcmFiles/aradplus/PP.xml
tar: ./BcmFiles/aradplus/PP.xml: time stamp 2025-02-10 22:16:38 is
131994088.877305594 s in the future
./BcmFiles/aradplus/DebugSignals-IRPP.xml
tar: ./BcmFiles/aradplus/DebugSignals-IRPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.876147801 s in the future
./BcmFiles/aradplus/DebugSignals-ETPP.xml
tar: ./BcmFiles/aradplus/DebugSignals-ETPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.875094872 s in the future
./BcmFiles/aradplus/SignalStructures.xml
tar: ./BcmFiles/aradplus/SignalStructures.xml: time stamp 2025-02-10 22:16:38 is
131994088.874070263 s in the future
./BcmFiles/aradplus/DebugSignals-ERPP.xml
tar: ./BcmFiles/aradplus/DebugSignals-ERPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.873554422 s in the future
./BcmFiles/jerichoplus/
tar: ./BcmFiles/aradplus: time stamp 2025-02-10 22:16:38 is 131994088.873312214 s
in the future
./BcmFiles/jerichoplus/DebugSignals-IRPP.xml
tar: ./BcmFiles/jerichoplus/DebugSignals-IRPP.xml: time stamp 2025-02-10 22:16:38
is 131994088.871441588 s in the future
./BcmFiles/jerichoplus/SignalStructures.xml
tar: ./BcmFiles/jerichoplus/SignalStructures.xml: time stamp 2025-02-10 22:16:38 is
131994088.870179347 s in the future
./BcmFiles/jerichoplus/DebugSignals-ETPP.xml
tar: ./BcmFiles/jerichoplus/DebugSignals-ETPP.xml: time stamp 2025-02-10 22:16:38
is 131994088.869789427 s in the future
./BcmFiles/jerichoplus/PP.xml
tar: ./BcmFiles/jerichoplus/PP.xml: time stamp 2025-02-10 22:16:38 is
131994088.86933205 s in the future
./BcmFiles/jerichoplus/DebugSignals-ERPP.xml
tar: ./BcmFiles/jerichoplus/DebugSignals-ERPP.xml: time stamp 2025-02-10 22:16:38
is 131994088.869068562 s in the future
./BcmFiles/qux/
tar: ./BcmFiles/jerichoplus: time stamp 2025-02-10 22:16:38 is 131994088.86889013 s
in the future
./BcmFiles/qux/PP.xml
tar: ./BcmFiles/qux/PP.xml: time stamp 2025-02-10 22:16:38 is 131994088.868083569 s
in the future
./BcmFiles/qux/SignalStructures.xml
tar: ./BcmFiles/qux/SignalStructures.xml: time stamp 2025-02-10 22:16:38 is
131994088.867531056 s in the future
./BcmFiles/qux/DebugSignals-ERPP.xml
tar: ./BcmFiles/qux/DebugSignals-ERPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.866497007 s in the future
./BcmFiles/qux/DebugSignals-ETPP.xml
tar: ./BcmFiles/qux/DebugSignals-ETPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.866094383 s in the future
./BcmFiles/qux/DebugSignals-IRPP.xml
tar: ./BcmFiles/qux/DebugSignals-IRPP.xml: time stamp 2025-02-10 22:16:38 is
131994088.863789485 s in the future
./BcmFiles/config.bcm
tar: ./BcmFiles/qux: time stamp 2025-02-10 22:16:38 is 131994088.863350732 s in the
future
tar: ./BcmFiles/config.bcm: time stamp 2025-02-10 22:16:38 is 131994088.860172617 s
in the future
./BcmFiles/Mio200MeshTopologyFile.json
tar: ./BcmFiles/Mio200MeshTopologyFile.json: time stamp 2025-02-10 22:16:38 is
131994088.859550056 s in the future
./BcmFiles/netserve
tar: ./BcmFiles/netserve: time stamp 2025-02-10 22:16:38 is 131994088.858163943 s
in the future
./startup.sh
tar: ./BcmFiles: time stamp 2025-02-10 22:16:38 is 131994088.857874951 s in the
future
tar: ./startup.sh: time stamp 2025-02-10 22:16:39 is 131994089.857485254 s in the
future
./specificexport.sh
tar: ./specificexport.sh: time stamp 2025-02-10 22:16:39 is 131994089.857212678 s
in the future
./post-download.sh
tar: ./post-download.sh: time stamp 2025-02-10 22:16:39 is 131994089.857012678 s in
the future
./pre-download.sh
tar: ./pre-download.sh: time stamp 2025-02-10 22:16:39 is 131994089.856824262 s in
the future
./rcp_user_install.sh
tar: ./rcp_user_install.sh: time stamp 2025-02-10 22:16:39 is 131994089.856575269 s
in the future
./pre-post-download-actions.sh
tar: ./pre-post-download-actions.sh: time stamp 2025-02-10 22:16:39 is
131994089.856240485 s in the future
./export.sh
tar: ./export.sh: time stamp 2025-02-10 22:16:39 is 131994089.856013477 s in the
future
./staging/
./staging/etc/
./staging/etc/rc.d/
./staging/etc/rc.d/sysdriver.sh
tar: ./staging/etc/rc.d/sysdriver.sh: time stamp 2025-02-10 22:16:39 is
131994089.855575396 s in the future
./staging/etc/rc.d/functions.sh
tar: ./staging/etc/rc.d/functions.sh: time stamp 2025-02-10 22:16:39 is
131994089.854322467 s in the future
./staging/etc/logrotate.d/
tar: ./staging/etc/rc.d: time stamp 2025-02-10 22:16:39 is 131994089.854033155 s in
the future
./staging/etc/logrotate.d/iolog
tar: ./staging/etc/logrotate.d/iolog: time stamp 2025-02-10 22:16:39 is
131994089.853789699 s in the future
./staging/etc/functions.sh
tar: ./staging/etc/logrotate.d: time stamp 2025-02-10 22:16:39 is
131994089.853575458 s in the future
tar: ./staging/etc/functions.sh: time stamp 2025-02-10 22:16:39 is
131994089.853427682 s in the future
./staging/etc/init.d/
./staging/etc/init.d/itf
tar: ./staging/etc/init.d/itf: time stamp 2025-02-10 22:16:39 is
131994089.853094306 s in the future
./staging/etc/init.d/mdio
tar: ./staging/etc/init.d/mdio: time stamp 2025-02-10 22:16:39 is
131994089.852864482 s in the future
./staging/etc/init.d/gpio
tar: ./staging/etc/init.d/gpio: time stamp 2025-02-10 22:16:39 is
131994089.852569889 s in the future
./staging/etc/init.d/fpga_loader
tar: ./staging/etc/init.d/fpga_loader: time stamp 2025-02-10 22:16:39 is
131994089.852365153 s in the future
./staging/etc/init.d/linux-kernel-bde
tar: ./staging/etc/init.d/linux-kernel-bde: time stamp 2025-02-10 22:16:39 is
131994089.852136929 s in the future
./staging/etc/init.d/linux-user-bde
tar: ./staging/etc/init.d/linux-user-bde: time stamp 2025-02-10 22:16:39 is
131994089.851911809 s in the future
./staging/etc/init.d/digi
tar: ./staging/etc/init.d/digi: time stamp 2025-02-10 22:16:39 is
131994089.851602432 s in the future
./staging/etc/init.d/watson
tar: ./staging/etc/init.d/watson: time stamp 2025-02-10 22:16:39 is
131994089.851396448 s in the future
./staging/usr/
tar: ./staging/etc/init.d: time stamp 2025-02-10 22:16:39 is 131994089.851237664 s
in the future
tar: ./staging/etc: time stamp 2025-02-10 22:16:39 is 131994089.851126688 s in the
future
./staging/usr/bin/
./staging/usr/bin/restart
tar: ./staging/usr/bin/restart: time stamp 2025-02-10 22:16:39 is
131994089.849554238 s in the future
./staging/usr/bin/tasks
tar: ./staging/usr/bin/tasks: time stamp 2025-02-10 22:16:39 is 131994089.849195774
s in the future
./staging/usr/bin/dbg
tar: ./staging/usr/bin/dbg: time stamp 2025-02-10 22:16:39 is 131994089.84896883 s
in the future
./staging/usr/bin/pregdb
tar: ./staging/usr/bin/pregdb: time stamp 2025-02-10 22:16:39 is
131994089.848683997 s in the future
./staging/usr/bin/gdbapp
tar: ./staging/usr/bin/gdbapp: time stamp 2025-02-10 22:16:39 is
131994089.848460189 s in the future
./staging/usr/bin/standalone
tar: ./staging/usr/bin/standalone: time stamp 2025-02-10 22:16:39 is
131994089.848270205 s in the future
./staging/usr/bin/runxml
tar: ./staging/usr/bin/runxml: time stamp 2025-02-10 22:16:39 is
131994089.848079133 s in the future
./staging/home/
tar: ./staging/usr/bin: time stamp 2025-02-10 22:16:39 is 131994089.847919709 s in
the future
tar: ./staging/usr: time stamp 2025-02-10 22:16:39 is 131994089.847806429 s in the
future
./staging/home/root/
./staging/home/root/.profile
tar: ./staging/home/root/.profile: time stamp 2025-02-10 22:16:39 is
131994089.847409724 s in the future
./staging/home/root/.gdbinit
tar: ./staging/home/root/.gdbinit: time stamp 2025-02-10 22:16:39 is
131994089.847174108 s in the future
./staging/home/root/.bashrc
tar: ./staging/home/root/.bashrc: time stamp 2025-02-10 22:16:39 is
131994089.846976636 s in the future
./staging/modules/
tar: ./staging/home/root: time stamp 2025-02-10 22:16:39 is 131994089.84682022 s in
the future
tar: ./staging/home: time stamp 2025-02-10 22:16:39 is 131994089.846594299 s in the
future
./staging/modules/linux-kernel-bde.ko
tar: ./staging/modules/linux-kernel-bde.ko: time stamp 2025-02-10 22:16:39 is
131994089.814797404 s in the future
./staging/modules/linux-user-bde.ko
tar: ./staging/modules/linux-user-bde.ko: time stamp 2025-02-10 22:16:39 is
131994089.773134386 s in the future
./staging/modules/fpga_loader.ko
tar: ./staging/modules/fpga_loader.ko: time stamp 2025-02-10 22:16:39 is
131994089.765105866 s in the future
./staging/modules/gpio.ko
tar: ./staging/modules/gpio.ko: time stamp 2025-02-10 22:16:39 is
131994089.75698349 s in the future
./staging/modules/itf.ko
tar: ./staging/modules/itf.ko: time stamp 2025-02-10 22:16:39 is
131994089.743786581 s in the future
./staging/modules/mdio.ko
tar: ./staging/modules/mdio.ko: time stamp 2025-02-10 22:16:39 is
131994089.735586764 s in the future
./staging/modules/digi.ko
tar: ./staging/modules/digi.ko: time stamp 2025-02-10 22:16:39 is
131994089.725421602 s in the future
./staging/modules/watson.ko
tar: ./staging/modules/watson.ko: time stamp 2025-02-10 22:16:39 is
131994089.716572377 s in the future
tar: ./staging/modules: time stamp 2025-02-10 22:16:39 is 131994089.7154798 s in
the future
tar: ./staging: time stamp 2025-02-10 22:16:39 is 131994089.715303576 s in the
future
tar: .: time stamp 2025-02-10 22:16:39 is 131994089.715231768 s in the future
wget -r --level=20 --preserve-permissions -nH -nv --cut-dirs=7
ftp://192.168.127.128:3021/usr/st/opb/linux/release/mio200b/app/*
No such directory 'usr/st/opb/linux/release/mio200b/app'.

iox-app-dnld: WGET2_ERR=8
iox-app-dnld: wget DONE!
post-download: we are in COLD boot case, so don't check MOS version
pre-post-download-actions: Executing post-download in /usr/iox ...
link staging/etc/init.d/watson to /etc/init.d/watson
chkconfig --add watson
link staging/etc/init.d/digi to /etc/init.d/digi
chkconfig --add digi
link staging/etc/init.d/linux-user-bde to /etc/init.d/linux-user-bde
chkconfig --add linux-user-bde
link staging/etc/init.d/linux-kernel-bde to /etc/init.d/linux-kernel-bde
chkconfig --add linux-kernel-bde
link staging/etc/init.d/fpga_loader to /etc/init.d/fpga_loader
chkconfig --add fpga_loader
link staging/etc/init.d/gpio to /etc/init.d/gpio
chkconfig --add gpio
link staging/etc/init.d/mdio to /etc/init.d/mdio
chkconfig --add mdio
link staging/etc/init.d/itf to /etc/init.d/itf
chkconfig --add itf
link staging/etc/functions.sh to /etc/functions.sh
link staging/etc/logrotate.d/iolog to /etc/logrotate.d/iolog
link staging/etc/rc.d/functions.sh to /etc/rc.d/functions.sh
link staging/etc/rc.d/sysdriver.sh to /etc/rc.d/sysdriver.sh
link staging/home/root/.bashrc to /home/root/.bashrc
link staging/home/root/.gdbinit to /home/root/.gdbinit
link staging/home/root/.profile to /home/root/.profile
link staging/modules/watson.ko to /lib/modules/4.1.35-2-hcpm-rt41/extra/watson.ko
link staging/modules/digi.ko to /lib/modules/4.1.35-2-hcpm-rt41/extra/digi.ko
link staging/modules/mdio.ko to /lib/modules/4.1.35-2-hcpm-rt41/extra/mdio.ko
link staging/modules/itf.ko to /lib/modules/4.1.35-2-hcpm-rt41/extra/itf.ko
link staging/modules/gpio.ko to /lib/modules/4.1.35-2-hcpm-rt41/extra/gpio.ko
link staging/modules/fpga_loader.ko to
/lib/modules/4.1.35-2-hcpm-rt41/extra/fpga_loader.ko
link staging/modules/linux-user-bde.ko to
/lib/modules/4.1.35-2-hcpm-rt41/extra/linux-user-bde.ko
link staging/modules/linux-kernel-bde.ko to
/lib/modules/4.1.35-2-hcpm-rt41/extra/linux-kernel-bde.ko
link staging/usr/bin/runxml to /usr/bin/runxml
link staging/usr/bin/standalone to /usr/bin/standalone
link staging/usr/bin/gdbapp to /usr/bin/gdbapp
link staging/usr/bin/pregdb to /usr/bin/pregdb
link staging/usr/bin/dbg to /usr/bin/dbg
link staging/usr/bin/tasks to /usr/bin/tasks
link staging/usr/bin/restart to /usr/bin/restart
removed '/etc/rc0.d/K53linux-user-bde'
removed '/etc/rc0.d/K55linux-kernel-bde'
removed '/etc/rc1.d/K53linux-user-bde'
removed '/etc/rc1.d/K55linux-kernel-bde'
removed '/etc/rc2.d/K53linux-user-bde'
removed '/etc/rc2.d/K55linux-kernel-bde'
removed '/etc/rc4.d/K53linux-user-bde'
removed '/etc/rc4.d/K55linux-kernel-bde'
removed '/etc/rc5.d/S45linux-kernel-bde'
removed '/etc/rc5.d/S47linux-user-bde'
removed '/etc/rc6.d/K53linux-user-bde'
removed '/etc/rc6.d/K55linux-kernel-bde'
pre-post-download-actions: Executing post-download finished.
post-download: calling /usr/iox/rcp_user_install.sh ...
post-download: /usr/iox/rcp_user_install.sh finished.
Starting OpenBSD Secure Shell server: sshd
done.
S19itf: start itf ...
params: device=itf, cdev=itf
itf device_init: dev=251 0 numMinors=40021
itf device_init: device loaded successfully.
S19itf: start finished.
Starting ntpd: done
Starting system log daemon...0
Starting kernel log daemon...0
Starting HPA's tftpd: in.tftpd-hpa
.
Starting internet superserver: xinetd.
S40gpio: start gpio ...
params: device=gpio, cdev=misc, flags=
gpio INFO: gpio_module_init(): entry
GPIO module version: v0.0.5
GPIO module device: name = gpio, misc minor = 54
gpio INFO: gpio_module_init(): done
S40gpio: start finished.
S41mdio: start mdio ...
params: device=mdio, cdev=mdio_cdev, flags=busname=fsl,fman-memac-mdio
mdioaddr=0xfc000
mdio_cdev::mdio_module_init(): entry
mdio_cdev::find_mdio_bus(): found node compatible with 'fsl,fman-memac-mdio' at
0xc0000000fffe4738: name='mdio', full_name='/soc@ffe000000/fman@400000/mdio@e1000'
mdio_cdev::find_mdio_bus(): found node compatible with 'fsl,fman-memac-mdio' at
0xc0000000fffe51a0: name='mdio', full_name='/soc@ffe000000/fman@400000/mdio@e3000'
mdio_cdev::find_mdio_bus(): found node compatible with 'fsl,fman-memac-mdio' at
0xc0000000fffe5ba0: name='mdio', full_name='/soc@ffe000000/fman@400000/mdio@e5000'
mdio_cdev::find_mdio_bus(): found node compatible with 'fsl,fman-memac-mdio' at
0xc0000000fffe6668: name='mdio', full_name='/soc@ffe000000/fman@400000/mdio@fc000'
mdio_cdev::find_mdio_bus(): found the right MDIO bus0: name='Freescale XGMAC MDIO
Bus', id='ffe4fc000'
MDIO module version: v0.0.1
MDIO module device: name = mdio_cdev, major = 250, minor = 0
mdio_cdev::mdio_module_init(): done
S41mdio: start finished.
S45fpga_loader: start fpga_loader ...
params: device=fpga_loader, cdev=fpga_loader, flags=
FPGA Loader module version: v0.0.4
FPGA Loader device: name = fpga_loader, major = 249, minor = 0
S45fpga_loader: start finished.
S48digi: start digi ...
params: device=digi, cdev=misc, flags=int_type=0
DIGI module version: v0.0.4
DIGI module device: name = digi, misc minor = 53
S48digi: start finished.
S48watson: start watson ...
params: device=watson, cdev=misc, flags=int_type=0
S48watson: start finished.
/etc/rc5.d/S60iox-app-run start
Starting procman: done
* starting FTP Server: vsftpd... Executing procman
done.
Starting crond: OK
Starting tcf-agent: OK

Poky (Yocto Project Reference Distro) 2.0 hcpm /dev/ttyS0

hcpm login: /usr/bin/procman: Hello Mio200B!!!

INIT: Switching to runlevel: 4
========= initiate specific variables =========
/etc/init.d/iox-app-dnld start
signature will NOT be checked
Starting /usr/iox/Mio200BBoard.e5500lnx64.Release ...

>>> RamBoot init START <<<

Init TimeBase rate : 31250000 Hz

Create empty SafeMem : /usr/SafeMem/
Create zero BoardMode: /usr/SafeMem/BoardMode.bin
Reboot Type : cold
Board Mode : 0x00000000
CPU Reset Reason : power

-- U-Boot Version Information --

U-Boot Version : hcpm v4.0.12+
U-Boot Creation Date : Jul/11/2019 19.06.05
U-Boot Running Image : safe, copy A

-- BSP Version Information --

MOS version 9.5MY16 - build of Sun Dec 6 07:08:38 IST 2020
Linux version 4.1.35-2-hcpm-rt41 (apinteg2@gen11) (gcc version 5.2.0 (GCC) ) #1 SMP
PREEMPT Sun Dec 6 06:53:10 IST 2020

-- RamBoot Version Information --

RamBoot Target : HCPM-based IO Card
RamBoot Build : e5500_linux64
RamBoot Version : 000.016

-- Kernel Modules --
Module Size Used by Tainted: G
watson 9097 0
digi 21098 0
fpga_loader 11459 0
mdio 9321 0
gpio 8574 0
itf 55026 0
cryptodev 66555 0

-- PCIe Devices --
00:00.0 PCI bridge: Freescale Semiconductor Inc Device 0824 (rev 11)
01:00.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:01.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:04.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:05.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:06.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:08.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:09.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
06:00.0 Ethernet controller: Broadcom Corporation Device 8679 (rev 11)
06:00.1 Ethernet controller: Broadcom Corporation Device 8679 (rev 11)
random: nonblocking pool is initialized

Init GPIO Driver using '/dev/gpio' device

GPIO: GA bit layout >> GPIO#392: port 3 (GPIO_D), pin 8, data 0
GPIO: IDPROM WriteProtect >> GPIO#406: port 3 (GPIO_D), pin 22, data 1
GPIO: L2 Switch Reset >> GPIO#401: port 3 (GPIO_D), pin 17, data 1
GPIO: PCIe Switch Reset (on CPU-JIG only) >>GPIO#388: port 3 (GPIO_D), pin 4, data
0
GPIO: Control-FPGA Reset >> GPIO#398: port 3 (GPIO_D), pin 14, data 1
GPIO: Control-FPGA NConfig >> GPIO#396: port 3 (GPIO_D), pin 12, data 1
GPIO: Control-FPGA ConfDone >> GPIO#397: port 3 (GPIO_D), pin 13, data 1
GPIO: Control-FPGA Clock >> GPIO#395: port 3 (GPIO_D), pin 11, data 1
GPIO: Control-FPGA Data >> GPIO#394: port 3 (GPIO_D), pin 10, data 1
GPIO: NTA Latch Enable >> GPIO#400: port 3 (GPIO_D), pin 16, data 0
GPIO: NTA Output Enable >> GPIO#407: port 3 (GPIO_D), pin 23, data 1

Init I2C Driver (NumBusses = 2)

Init IO-Expander 0

I/O Expander 0 parameters:

I2C Bus 2, Dev 0xe8
Port width: 2 bytes
Registers:
Input Data - 0x0507
Output Data - 0x0500
Polarity - 0x0000
Config - 0xffff

Config LED's
Init LED's

Init ID-PROM Driver

Checking Main Board ID PROM ... OK.
Checking CPU Board ID PROM ... OK.

Showing CPU Board ID PROM:

Fixed Params:
Equipment Type : 34251 (0x85cb)
Serial Number : 503948004
Hw Rev/Version : B09
Mech. Assembly : P
Hw Option : 013
Ver. Major/Minor : 00000000
Fixed Checksum1 : 0x4760
Fixed Checksum2 : 0xb89f
3rd IdProm Type : 0
Flexible params:
MAC Address : f8:54:af:04:32:00
DDR Size : 4096MB
Reserved1 : 0x0000
Reserved2 : 0x0000
Card Description : HCPM
Full Serial Numb : 5503948004
Flex. Checksum1 : 0x3e16
Flex. Checksum2 : 0xc1e9

Showing Main Board ID PROM:

Fixed Params:
Equipment Type : 35412 (0x8a54)
Serial Number : 503943317
Hw Rev/Version : A00
Mech. Assembly : A
Hw Option : 013
Ver. Major/Minor : 00010001
 Fixed Checksum1 : 0x3983
Fixed Checksum2 : 0xc67c
3rd IdProm Type : 0
Flexible params:
Psat param : 0
FIPS support : no (0x00)
Reserved2 : 0x0000
Card Description : MIO200B
Full Serial Numb : 5503943317
Flex. Checksum1 : 0x7cb7
Flex. Checksum2 : 0x8348

Slot Number : u4 (GA 5)

GA bit layout: LSB_0 (5-bits)
Card is in : chassis
CPU card : HCPM
Main card : MIO200B

FIPS support: disabled

Setup external IP interface eth0
Operation mode is : Chassis
Internal IP address: 192.168.127.41/24
Peer RCP IP address: 192.168.127.128
External (debug) IP address: 192.168.152.228/23
Default Gateway IP : 192.168.153.254

Init MDIO Driver using '/dev/mdio' device

Init M98DX106 Driver
-----------------------------------------------------------------------------
m98dx106 ports counters
-----------------------------------------------------------------------------
is port enabled | RX Good Frames | TX Good Frames
-------------------------------|----------------------|----------------------
Port 0: 1 | 0 | 0
Port 1: 1 | 115295 | 86934
Port 2: 1 | 0 | 0
Port 3: 0 | 0 | 0
Port 4: 0 | 0 | 0
Port 5: 1 | 1 | 0
Port 6: 1 | 86934 | 115294
Port 7: 0 | 0 | 0
Port 8: 0 | 0 | 0
Port 9: 0 | 0 | 0
-----------------------------------------------------------------------------

Ethernet Switch reset ... done.

Init Ethernet Switch: 98DX106 - 10 ports managed (ID 0xD3D3 Rev 0x0)
Setup Ethernet Switch ports:
port 0 (to CODM )(SGMII, Autoneg 100BT Full)
port 1 (to RCP-A)(1000Base-X, Fixed 1GB)
port 2 (to RCP-B)(1000Base-X, Fixed 1GB)
port 5 (to mEMAC1 'debug VLAN') (SGMII, Fixed 1GB)
port 6 (to mEMAC2 'backplane VLAN')(SGMII, Fixed 1GB)
m98dx106: VLAN ID 4091, MAC learning disable, SetPvid yes
m98dx106: VLAN ID 4092, MAC learning disable, SetPvid yes
m98dx106: VID + MAC are used for FDB lookup and learning

>>> RamBoot init END <<<

=======================================================
========= DISABLED Multi Threading DISABLED ===========
======= -- calculated APP Semaphore DISABLED -- ======
=======================================================

=======================================================
=== DISABLED PerActPf With Tick Dispatcher DISABLED ===
=======================================================
============= HOME Directory is /usr/iox ==============

=======================================================
======= -- LOCAL_FILE_XFER DISABLED -- ======
=======================================================

=======================================================

range 0: 0 0x00000000 0x0000000f 0xef000000 0x01000000

range 1: 3 0x00000000 0x0000000f 0xe0000000 0x01000000

Memory Map: ChipSelect = [3] PhyBaseAddress = [0xfe0000000] MappedBaseAddress =

[0x3fffa0af7000]

range 0: 0 0x00000000 0x0000000f 0xef000000 0x01000000

range 1: 3 0x00000000 0x0000000f 0xe0000000 0x01000000

range 2: 4 0x00000000 0x0000000f 0xe1000000 0x01000000

Memory Map: ChipSelect = [4] PhyBaseAddress = [0xfe1000000] MappedBaseAddress =

[0x3fff9b000000]

range 0: 0 0x00000000 0x0000000f 0xef000000 0x01000000

range 1: 3 0x00000000 0x0000000f 0xe0000000 0x01000000

Memory Map: ChipSelect = [3] PhyBaseAddress = [0xfe0000000] MappedBaseAddress =

[0x3fff9a000000]

range 0: 0 0x00000000 0x0000000f 0xef000000 0x01000000

range 1: 3 0x00000000 0x0000000f 0xe0000000 0x01000000

range 2: 4 0x00000000 0x0000000f 0xe1000000 0x01000000

Memory Map: ChipSelect = [4] PhyBaseAddress = [0xfe1000000] MappedBaseAddress =

[0x3fff99000000]
== -- calculated with DEVICES Semaphore Disabled -- ==
=======================================================

trace-specification: *=all=enabled

PrintAll:148 printed-total=0 out-of=0

PrintAll:139 element[0]=* mask=all
PrintAll:148 printed-total=1 out-of=1
RamBoot: addDebugMenu 'SysInfo'
RamBoot: addDebugMenu 'Misc'
RamBoot: addDebugMenu 'gpio'
RamBoot: addDebugMenu 'i2cBus'
RamBoot: addDebugMenu 'eeprom'
RamBoot: addDebugMenu 'm98dx106'
MIO200 IDPROM HANDLER Created!!! 0x9c01c6e0

########### IdpromHandlerPf::_ReadEepromI2Cprom idprom actual-type read 35412

####################
########### IdpromHandlerPf::_ReadEepromI2Cprom idprom actual-type read 34251
####################

BoardResources::RegisterTaskRecoveryWrappers: adding task: InCom Task with ID:

32771 to Recoverable Threads container

@@@ romBootVersion hcpm v4.0.12+ romCreationDate Jul/11/2019 19.06.05 @@@@@@@

@@@ _BuildStatusMessage: FwVersion 4.0.12 @@@@@@@

**** card type is 35412 **** BM from file = 0 ****

*** InitTaskLinuxProc - Sending a message to RCP:

PP_MCP_AUTONOMOUS_STATUS_REPORT_MID ***

InitTaskLinuxProc Received Msg = f40

Received Run Msg, BM=0x20006

InitTaskLinuxProc finished
Node name: UMDNode name: FileNameFound: Tag: FileName. Value:
HARRIET_TOP_r42_170625
Node name: InnerFileFormatFound: Tag: InnerFileFormat. Value: rbf
Node name: HwComponentFound: Tag: HwComponent. Value: my_proj
Node name: DescriptionFound: Tag: Description. Value: image_ts_17_6_22_17_27
Node name: BranchFound: Tag: Branch. Value: 0x0
Node name: RevisionFound: Tag: Revision. Value: 0x2a
Node name: TimeStampFound: Tag: TimeStamp. Value: 17:6:22:17:27
Node name: MinimalBranchCompatibilityFound: Tag: MinimalBranchCompatibility. Value:
0x0
Node name: MinimalRevisionCompatibilityFound: Tag: MinimalRevisionCompatibility.
Value: 0x0
Header file "fpga/HARRIET.hdr" created successfully
Binary file "fpga/HARRIET.rbf" created successfully
Node name: UMDNode name: FileNameFound: Tag: FileName. Value: mio200bctr
Node name: InnerFileFormatFound: Tag: InnerFileFormat. Value: RBF
Node name: HwComponentFound: Tag: HwComponent. Value: Cyclone 4
Node name: DescriptionFound: Tag: Description. Value: MIO200B Control
Node name: BranchFound: Tag: Branch. Value: 0x0
Node name: RevisionFound: Tag: Revision. Value: 0xDB03
Node name: TimeStampFound: Tag: TimeStamp. Value: 22:11:02:20:37
Node name: MinimalBranchCompatibilityFound: Tag: MinimalBranchCompatibility. Value:
0x0
Node name: MinimalRevisionCompatibilityFound: Tag: MinimalRevisionCompatibility.
Value: 0x0
Header file "fpga/MIO200CTR.hdr" created successfully
Binary file "fpga/MIO200CTR.RBF" created successfully
ALTERAPATH = /usr/iox/fpga

set specific values of DTACK to Mio200

sched: RT throttling activated
Loading MainBoard Altera Skipped, Already done in uBoot.
Starting load process of secondary FPGA
Start Loading second Ctrl FPGA with data_mask 0x1 ...

LoadInitialization :: [Set Altera Reset]

LoadCompletion :: [Release Altera Reset]

AlteraPfPkg.cpp: S_t_a_t_u_s_> MIO200SECCTRL Altera (MIO200SECCTRL.EXO) loading -
Pass
end loading first finger
set Harriet STI to 16-bit Serializer mode
Start Loading Harriet with data_mask 0xffff ...
Read error from file: "fpga/HARRIET.rbf.gz"

LoadInitialization :: [Set Altera Reset]

...................................................................................
...................................................................................
....................................................
got to the end of file
itf MapFpga: ioremap of 0xfe0000000 / 0x1000 succeeded
itf ConnectTreeToCpu: irq_create_mapping for irq 5
itf ConnectTreeToCpu: set_irq_type virq = 17, tree=0 (hwirq=5) irqType=0x8
irqFlag=0x80

LoadCompletion :: [Release Altera Reset]

AlteraPfPkg.cpp: S_t_a_t_u_s_> HARRIET Altera (HARRIET.rbf) loading - Pass
Finished loading Harriet.
Hw Preperation Script Performed.
Mio200BoardInitPf::InitL2Switch: IsInWarm = 0
Mio200BoardInitPf::InitL2Switch: IsInWarm = 0
Actual MRU value set: 1600
Actual MRU value set: 1600

MarvellDx106L2SwitchDevice::SetCascadingPort() a_portNum = 3, a_targetDeviceId = 2

cascadingMask = 0x7ffffff, cascadeHeaderRegVal = 0x8000000, cascadingBitField = 0x0
WriteRegister - CascadingHeaderInsertionConfigReg::RegAddr = 0x7800004,
cascadeHeaderRegVal = 0x8000008, cascadingMask = 0x7ffffff, Position = 0x0,
cascadingBitField = 0x8
portNumMask = 0xfe, regAddress = 0x1a40024, DeviceMapTableEntryReg::RegAddr =
0x1a40004, a_targetDeviceId = 0x2, DeviceMapTableEntryReg::Step = 0x10
deviceMapRegVal before = 0x0
WriteRegister() regAddress = 0x1a40024, deviceMapRegVal = 0x6, portNumMask = 0xfe,
DeviceMapTableEntryReg::PortNumber.Position = 0x1, a_portNum = 3

regAddress = 0x1a40024

MarvellDx106L2SwitchDevice::SetCascadingPort() a_portNum = 0, a_targetDeviceId = 16

cascadingMask = 0x7ffffff, cascadeHeaderRegVal = 0x8000000, cascadingBitField = 0x0
WriteRegister - CascadingHeaderInsertionConfigReg::RegAddr = 0x7800004,
cascadeHeaderRegVal = 0x8000001, cascadingMask = 0x7ffffff, Position = 0x0,
cascadingBitField = 0x1
portNumMask = 0xfe, regAddress = 0x1a40104, DeviceMapTableEntryReg::RegAddr =
0x1a40004, a_targetDeviceId = 0x10, DeviceMapTableEntryReg::Step = 0x10
deviceMapRegVal before = 0x0
WriteRegister() regAddress = 0x1a40104, deviceMapRegVal = 0x0, portNumMask = 0xfe,
DeviceMapTableEntryReg::PortNumber.Position = 0x1, a_portNum = 0

regAddress = 0x1a40104
m_ConfFilesDevice = /usr/iox/rd:/
m_ConfFileNamePrefix = /usr/iox/rd:/conf_files/conf_file
m_ConfFilesLocation = /usr/iox/rd:/conf_files
m_PreviousConfFileName = /usr/iox/rd:/conf_files/conf_file_prev.dat
m_CurrentConfFileName = /usr/iox/rd:/conf_files/conf_file_curr.dat
Read error from file: "fpga/MIO200CTR.rbf.gz"
Node name: UMDNode name: FileNameFound: Tag: FileName. Value: mio200bctr
Node name: InnerFileFormatFound: Tag: InnerFileFormat. Value: RBF
Node name: HwComponentFound: Tag: HwComponent. Value: Cyclone 4
Node name: DescriptionFound: Tag: Description. Value: MIO200B Control
Node name: BranchFound: Tag: Branch. Value: 0x0
Node name: RevisionFound: Tag: Revision. Value: 0xDB03
Node name: TimeStampFound: Tag: TimeStamp. Value: 22:11:02:20:37
Node name: MinimalBranchCompatibilityFound: Tag: MinimalBranchCompatibility. Value:
0x0
Node name: MinimalRevisionCompatibilityFound: Tag: MinimalRevisionCompatibility.
Value: 0x0
Read error from file: "fpga/HARRIET.rbf.gz"
Node name: UMDNode name: FileNameFound: Tag: FileName. Value:
HARRIET_TOP_r42_170625
Node name: InnerFileFormatFound: Tag: InnerFileFormat. Value: rbf
Node name: HwComponentFound: Tag: HwComponent. Value: my_proj
Node name: DescriptionFound: Tag: Description. Value: image_ts_17_6_22_17_27
Node name: BranchFound: Tag: Branch. Value: 0x0
Node name: RevisionFound: Tag: Revision. Value: 0x2a
Node name: TimeStampFound: Tag: TimeStamp. Value: 17:6:22:17:27
Node name: MinimalBranchCompatibilityFound: Tag: MinimalBranchCompatibility. Value:
0x0
Node name: MinimalRevisionCompatibilityFound: Tag: MinimalRevisionCompatibility.
Value: 0x0
SafeMemoryMngPf::SaveToSafeMem: Creating new safe memory record for key = 1330:1
(class id , unique class id) a_dataSize = 23515992

Log either does not exist, or is basically invalid. Error=e03

LbNfsDrvInit: mounting if not on same processor /mnt/logdir to /S/var/opb/ RCP
file system.
LbNfsDrvInit: Mounting nfs /mnt/logdir to 192.168.127.128:/S/var/opb/ succeeded
LbNfsDrvInit: NFS logging was initialized successfully

InterruptsContainerPf::GetInstance: Interrupt container Instance created !

(Instance Address: 0x3fff5a68b770 )
IRQ5 Interrupt Tree created !
ItfManagerPf::ClearTree _treeId = 0
ItfInterfaceKernelPf::_DeleteDevFilesForTree: dirname = .
ItfInterfaceKernelPf::_DeleteDevFilesForTree: dirname = ..
Interrupt->CreateAndConnect: mknod: major = 251, minor = 1, fname =
'/dev/itf_dev/itf-CtrlFpgaIrq5:0:0'
Interrupt->CreateAndConnect: mknod: major = 251, minor = 2, fname =
'/dev/itf_dev/itf-CtrlFpgaIrq5:e:3'
Interrupt->CreateAndConnect: mknod: major = 251, minor = 3, fname =
'/dev/itf_dev/itf-CtrlFpgaIrq5:e:b'
IRQ5 Interrupt Tree configuration ended ! TreeSize = 3, FpgaBaseAddr =
0x00000000e0000000 , IRQ# = 5
Interrupt socket CtrlFpgaIrq5 created ! Interrupts In Socket = 2, SocketAddr =
0x3fff5a64c720
Debug Int: Interrupt added to socket. InterruptID = 1, MASK_OFFSET = 14,
BIT_NUM = 11
RcpFpgaIfc Int: Interrupt added to socket. InterruptID = 0, MASK_OFFSET = 14,
BIT_NUM = 3
RcpFpgaIfcInterruptHandler registered socket to CtrlFpgaIrq5 Interrupts.
InterruptsSocketPf::_StartWorkerThread: Listener(Worker) Thread=32772 created by
ThreadId=2713280896 !
Thread Name: xc interrupt Task, Priority= 87, StackSize= 131072, InterruptSocket
this= 0x3fff5a64c720
InterruptsSocketPf::InterruptWorkerThread: New Interrupt Worker Thread Created !!!
(ThreadId=2694193536, a_pIntSocketObj=0x3fffa2725318)

InterruptStateControllerPf::_IntConnect: Interrupt on device /dev/itf_dev/itf-

CtrlFpgaIrq5:e:3 connected with FD 29.
Select exist because of change in FD=_ctrlPipeGetFd (application req) :
Async watson interrupt 'CtrlFpgaIrq5' connected.

InterruptStateControllerPf::_IntConnect: Interrupt on device /dev/itf_dev/itf-

CtrlFpgaIrq5:e:b connected with FD 30.
Select exist because of change in FD=_ctrlPipeGetFd (application req) :
Async debug interrupt 'CtrlFpgaIrq5' connected.
Select exist because of change in FD=_ctrlPipeGetFd (application req) :
Select exist because of change in FD=_ctrlPipeGetFd (application req) :
RCP FPGA IFC Interrupt enabled and ready !

**** HarrietOffsetPf: CreateInstance 0x5a659840

[INFO][00:00:00.52729][Io2IoRxPf.h/Io2IoRxPf:40]:

###################################################
################## IO2IOc V1.1.1 ##################
###################################################

[INFO][00:00:00.53798][RxImpPf.cpp/RxImpPf:23]:

###################################################
########## IO2IOc Rx Started Successfuly ##########
###################################################

**** Mio200HarrietInstallDataPf::Instance 0x5a6b66d0

**** Mio200I2cInstallDataPf: CreateInstance 0x5a6ba420

**** Mio200BcmFicInstallDataPf: CreateInstance 0x5a6ab970

(filename = Mio200BBITTestList.csv)

***SetTempSensorThresholds::Starting TEMPSENSOR FILE parse***

Main_cold: Cold Threshold = 40, Hot Threshold= 43, Alarm Clear Threshold = 53,
Alarm set Threshold = 56
Main_hot: Cold Threshold = 61, Hot Threshold= 64, Alarm Clear Threshold = 70, Alarm
set Threshold = 73
Digi: Cold Threshold = 70, Hot Threshold= 73, Alarm Clear Threshold = 77, Alarm set
Threshold = 80
HyPhy: Cold Threshold = 67, Hot Threshold= 70, Alarm Clear Threshold = 91, Alarm
set Threshold = 94
Harriet: Cold Threshold = 67, Hot Threshold= 70, Alarm Clear Threshold = 87, Alarm
set Threshold = 90
Jericho: Cold Threshold = 74, Hot Threshold= 77, Alarm Clear Threshold = 81, Alarm
set Threshold = 84
HCPM: Cold Threshold = 76, Hot Threshold= 79, Alarm Clear Threshold = 97, Alarm set
Threshold = 100
*** Set Specific Temp Thresholds from file DONE ***
RegisterSpecificCallbackHandler: Registered callback. pHandlerClass=0x3fff5a6acca8
lag >> Lag Manager Instance Created !
CreateTasks: Name = Recovery Task; Index = 12; Serial = 50; Id = 0x8005
<< RAMBOOT >> wdtSetStarvationTimeout() not supported for Linux !
CreateTasks: Name = Timers Task; Index = 13; Serial = 3; Id = 0x8006
EthernetDispatcherLinux.cpp:373 I ReceivePackets: Start receiving incoming
packets...

CreateTasks: Name = EthDrv Task; Index = 14; Serial = 14; Id = 0x8007

GccPppManagerLinux.cpp:374 I PppStartPoint: PPP Started.

Starting PPP with 20 channels maximum.

CreateTasks: Name = PPP Task; Index = 15; Serial = 15; Id = 0x8008
CreateTasks: Name = Hexec Task; Index = 16; Serial = 1; Id = 0x8009

BoardResources::RegisterTaskRecoveryWrappers: adding task: Hexec Task with ID:

32777 to Recoverable Threads container
CreateTasks: Name = File Xfer Task; Index = 17; Serial = 4; Id = 0x800a
CreateTasks: Name = Service Task; Index = 18; Serial = 9; Id = 0x800b
CreateTasks: Name = SpDispatcher Task; Index = 19; Serial = 17; Id = 0x800c
OAM Mutex created: 9
CreateTasks: Name = OAM Task; Index = 20; Serial = 18; Id = 0x800d
CreateTasks: Name = LACP Task; Index = 21; Serial = 19; Id = 0x800e
DebugTelnetServerPf::InitDebugTelnetServer start listening on port 1123
CreateTasks: Name = Debug Task; Index = 22; Serial = 16; Id = 0x800f

BoardResources::RegisterTaskRecoveryWrappers: adding task: Debug Task with ID:

32783 to Recoverable Threads container
SwErrControllerPf: Enabling SWERRs
******************** Working with BINARY config files *********************

[INFO][14:12:27.11851][DiscoveryImpPf.cpp/DiscoveryImpPf:37]:

##########################################################
########## IO2IOc Discovery Started Successfuly ##########
############### Detected My Slot Number: 4 ###############
##########################################################

-- U-Boot Version Information --

U-Boot Version : hcpm v4.0.12+
U-Boot Creation Date : Jul/11/2019 19.06.05
U-Boot Running Image : safe, copy A

-- BSP Version Information --

MOS version
******IoBlackBox Logging disabled *****
!!! Mio200FactoryPf::CreateHolder creating TfpZTLEqptHolderPf for
Level0[0]TfpZTLEqptHolderPf::TfpZTLEqptHolderPf!!! Mio200FactoryPf::CreateHolder
creating TfpZTLEqptHolderPf for Level0[1]TfpZTLEqptHolderPf::TfpZTLEqptHolderPf!!!
Mio200FactoryPf::CreateHolder creating TfpZTLEqptHolderPf for
Level0[2]TfpZTLEqptHolderPf::TfpZTLEqptHolderPf!!! Mio200FactoryPf::CreateHolder
creating TfpZTLEqptHolderPf for Level0[3]TfpZTLEqptHolderPf::TfpZTLEqptHolderPf!!!
Mio200FactoryPf::CreateHolder creating TfpZTLEqptHolderPf for
Level0[4]TfpZTLEqptHolderPf::TfpZTLEqptHolderPf!!! Mio200FactoryPf::CreateHolder
creating TfpZTLEqptHolderPf for Level0[5]TfpZTLEqptHolderPf::TfpZTLEqptHolderPf!!!
Mio200FactoryPf::CreateHolder creating TfpZTLEqptHolderPf for
Level0[6]TfpZTLEqptHolderPf::TfpZTLEqptHolderPf!!! Mio200FactoryPf::CreateHolder
creating TfpZTLEqptHolderPf for Level0[7]TfpZTLEqptHolderPf::TfpZTLEqptHolderPf!!!
Mio200FactoryPf::CreateHolder creating TfpZTLEqptHolderPf for
Level0[8]TfpZTLEqptHolderPf::TfpZTLEqptHolderPf!!! Mio200FactoryPf::CreateHolder
creating TfpZTLEqptHolderPf for Level0[9]TfpZTLEqptHolderPf::TfpZTLEqptHolderPf!!!
Mio200FactoryPf::CreateHolder creating TfpZTLEqptHolderPf for
Level0[10]TfpZTLEqptHolderPf::TfpZTLEqptHolderPf!!! Mio200FactoryPf::CreateHolder
creating TfpZTLEqptHolderPf for Level0[11]TfpZTLEqptHolderPf::TfpZTLEqptHolderPf!!!
Mio200FactoryPf::CreateHolder creating TfpZTLEqptHolderPf for
Level0[12]TfpZTLEqptHolderPf::TfpZTLEqptHolderPfMio200BoardEqptPf::CreateSubHolders
- Creating ASIC holder for EDC. ObjectId 1501:
0:7d:ffff:ffff:ffff:ffff:ffff:ffff:14

Mio200BoardEqptPf::CreateSubHolders - Creating ASIC holder for EDC. ObjectId

1501: 0:7d:ffff:ffff:ffff:ffff:ffff:ffff:15

Mio200BoardEqptPf::CreateSubHolders - Creating ASIC holder for EDC. ObjectId

1501: 0:7d:ffff:ffff:ffff:ffff:ffff:ffff:16

Mio200BoardEqptPf::CreateSubHolders - Creating ASIC holder for Analog Switch.

ObjectId 1501: 0:7d:ffff:ffff:ffff:ffff:ffff:ffff:17

Mio200BoardEqptPf::CreateSubHolders - Creating ASIC holder for Analog Switch.

ObjectId 1501: 0:7d:ffff:ffff:ffff:ffff:ffff:ffff:18

Mio200BoardEqptPf::CreateSubHolders - Creating ASIC holder for Analog Switch.

ObjectId 1501: 0:7d:ffff:ffff:ffff:ffff:ffff:ffff:19

Mio200BoardEqptPf::CreateSubHolders - Creating ASIC holder for Analog Switch.

ObjectId 1501: 0:7d:ffff:ffff:ffff:ffff:ffff:ffff:1a

Mio200BoardEqptPf::CreateSubHolders - Creating ASIC holder for Analog Switch.

ObjectId 1501: 0:7d:ffff:ffff:ffff:ffff:ffff:ffff:1b

Mio200BoardEqptPf::CreateSubHolders - Creating ASIC holder for Analog Switch.

ObjectId 1501: 0:7d:ffff:ffff:ffff:ffff:ffff:ffff:1c

Mio200BoardEqptPf::CreateSubHolders - Creating ASIC holder for Analog Switch.

ObjectId 1501: 0:7d:ffff:ffff:ffff:ffff:ffff:ffff:1d

Mio200BoardEqptPf::CreateSubHolders - Creating ASIC holder for Analog Switch.

ObjectId 1501: 0:7d:ffff:ffff:ffff:ffff:ffff:ffff:1e
Mio200BoardEqptPf::CreateSubHolders - Creating ASIC holder for Harriet. ObjectId
1501: 0:7d:ffff:ffff:ffff:ffff:ffff:ffff:13

Set Is99XX to true

Set Is99XX to true
Set Is99XX to true
Set Is99XX to true
Set Is99XX to true
Set Is99XX to true
Set Is99XX to true
Set Is99XX to true
Set Is99XX to true
Set Is99XX to true
Set Is99XX to true
Set Is99XX to true
Set Is99XX to true
Mio200BoardEqptPf::CreateSubHolders - Creating ASIC holder for Gcc. ObjectId
1501: 0:7d:ffff:ffff:ffff:ffff:ffff:ffff:35

EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1500

0:126:65535:65535:65535:65535:65535:65535:65535
General Block Install:
BilboCtrl Block Install:
StiCtrl Block Install:
SapCtrl Block install:

GCC FPGA install finished

Base Addresses
=================
Holder 0: ClassId 1501, Level0 65535, BaseAddress 0x3fff9a000000
Holder 1: ClassId 1501, Level0 13, BaseAddress 0x3fff9a000026
Holder 2: ClassId 1501, Level0 15, BaseAddress 0x3fff9a000030
Holder 3: ClassId 1501, Level0 18, BaseAddress 0x1234
Holder 4: ClassId 1501, Level0 16, BaseAddress 0x1234
Holder 5: Class9.5MY16 - build of Sun Dec 6 07:08:38 IST 2020
Id 1501, Level0 17, BaseAddress 0x1234
Holder 6: ClassId 1501, Level0 20, BaseAddress 0x3fff9a010100
Holder 7: ClassId 1501, Level0 21, BaseAddress 0x3fff9a010110
Holder 8: ClassId 1501, Level0 22, BaseAddress 0x3fff9a010120
Holder 9: ClassId 1501, Level0 23, BaseAddress 0x3fff9a010028
Holder 10: ClassId 1501, Level0 24, BaseAddress 0x3fff9a01002a
Holder 11: ClassId 1501, Level0 25, BaseAddress 0x3fff9a01002c
Holder 12: ClassId 1501, Level0 26, BaseAddress 0x3fff9a01002e
Holder 13: ClassId 1501, Level0 27, BaseAddress 0x3fff9a010030
Holder 14: ClassId 1501, Level0 28, BaseAddress 0x3fff9a010032
Holder 15: ClassId 1501, Level0 29, BaseAddress 0x3fff9a010034
Holder 16: ClassId 1501, Level0 30, BaseAddress 0x3fff9a010036
Holder 17: ClassId 1501, Level0 19, BaseAddress 0x3fff99000000
Holder 18: ClassId 1500, Level0 0, BaseAddress 0x3fff9a004000
Holder 19: ClassId 1500, Level0 1, BaseAddress 0x3fff9a010400
Holder 20: ClassId 1500, Level0 2, BaseAddress 0x3fff9a010800
Holder 21: ClassId 1500, Level0 3, BaseAddress 0x3fff9a010c00
Holder 22: ClassId 1500, Level0 4, BaseAddress 0x3fff9a011000
Holder 23: ClassId 1500, Level0 5, BaseAddress 0x3fff9a011400
Holder 24: ClassId 1500, Level0 6, BaseAddress 0x3fff9a011800
Holder 25: ClassId 1500, Level0 7, BaseAddress 0x3fff9a011c00
Holder 26: ClassId 1500, Level0 8, BaseAddress 0x3fff9a012000
Holder 27: ClassId 1500, Level0 9, BaseAddress 0x3fff9a012400
Holder 28: ClassId 1500, Level0 10, BaseAddress 0x3fff9a012800
Holder 29: ClassId 1500, Level0 11, BaseAddress 0x3fff9a012c00
Holder 30: ClassId 1500, Level0 12, BaseAddress 0x3fff9a013000
Holder 31: ClassId 1501, Level0 32, BaseAddress 0x3fff9a004022
Holder 32: ClassId 1501, Level0 33, BaseAddress 0x3fff9a010422
Holder 33: ClassId 1501, Level0 34, BaseAddress 0x3fff9a010822
Holder 34: ClassId 1501, Level0 35, BaseAddress 0x3fff9a010c22
Holder 35: ClassId 1501, Level0 36, BaseAddress 0x3fff9a011022
Holder 36: ClassId 1501, Level0 37, BaseAddress 0x3fff9a011422
Holder 37: ClassId 1501, Level0 38, BaseAddress 0x3fff9a011822
Holder 38: ClassId 1501, Level0 39, BaseAddress 0x3fff9a011c22
Holder 39: ClassId 1501, Level0 40, BaseAddress 0x3fff9a012022
Holder 40: ClassId 1501, Level0 41, BaseAddress 0x3fff9a012422
Holder 41: ClassId 1501, Level0 42, BaseAddress 0x3fff9a012822
Holder 42: ClassId 1501, Level0 43, BaseAddress 0x3fff9a012c22
Holder 43: ClassId 1501, Level0 44, BaseAddress 0x3fff9a013022
Holder 44: ClassId 1501, Level0 45, BaseAddress 0x1234
Holder 45: ClassId 1501, Level0 46, BaseAddress 0x1234
Holder 46: ClassId 1501, Level0 47, BaseAddress 0x1234
Holder 47: ClassId 1501, Level0 48, BaseAddress 0x1234
Holder 48: ClassId 1501, Level0 49, BaseAddress 0x1234
Holder 49: ClassId 1501, Level0 50, BaseAddress 0x1234
Holder 50: ClassId 1501, Level0 51, BaseAddress 0x1234
Holder 51: ClassId 1501, Level0 52, BaseAddress 0x3fff9a002000
Holder 52: ClassId 1501, Level0 53, BaseAddress 0x3fff99040000EqptPf::Unlock -
a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:65535:65535:65535:65535:65535:65535

****** Mio200I2cInstallDataPf::GetInstall - for I2c BusId=0EqptPf::Unlock -

a_pUnlockingEqptObjId.ObjectId: 1501 0:125:65535:13:65535:65535:65535:65535:65535
Linux version 4.1.35-2-hcpm-rt41 (apinteg2@gen11) (gcc version 5.2.0 (GCC) ) #1 SMP
PREEMPT Sun Dec 6 06:53:10 IST 2020

-- RamBoot Version Information --

RamBoot Target : HCPM-based IO Card
RamBoot Build : e5500_linux64
RamBoot Version : 000.016

Application Version : 13.1.1.0.+

Application Creation Date : Feb 10 2025, 20:11:19
Build Date: Feb 10 2025, 20:12:06 GMT
P4 Change: 423018 on 2025/02/10 by smordechayov@smordechayov:w7_main-apollo-next
P4 Client: apl:Aio-maNext-CM-ora10

Opened Files:

OpenSSL Version: OpenSSL 1.0.2k-fips 26 Jan 2017

Mio200 init is finished

EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:15:65535:65535:65535:65535:65535

start delay of 1 sec. wait for PLL clock to stable (needed for Digi).

Running PCIe rescan...

pcieport 0000:00:00.0: BAR 7: no space for [io size 0x3000]
pcieport 0000:00:00.0: BAR 7: failed to assign [io size 0x3000]
pcieport 0000:00:00.0: BAR 7: no space for [io size 0x1000]
pcieport 0000:00:00.0: BAR 7: failed to assign [io size 0x1000]
pcieport 0000:01:00.0: BAR 7: no space for [io size 0x3000]
pcieport 0000:01:00.0: BAR 7: failed to assign [io size 0x3000]
pcieport 0000:01:00.0: BAR 7: no space for [io size 0x1000]
pcieport 0000:01:00.0: BAR 7: failed to assign [io size 0x1000]
pcieport 0000:02:01.0: BAR 7: no space for [io size 0x1000]
pcieport 0000:02:01.0: BAR 7: failed to assign [io size 0x1000]
pcieport 0000:02:05.0: BAR 7: no space for [io size 0x1000]
pcieport 0000:02:05.0: BAR 7: failed to assign [io size 0x1000]
pcieport 0000:02:09.0: BAR 7: no space for [io size 0x1000]
pcieport 0000:02:09.0: BAR 7: failed to assign [io size 0x1000]
pcieport 0000:02:09.0: BAR 7: no space for [io size 0x1000]
pcieport 0000:02:09.0: BAR 7: failed to assign [io size 0x1000]
pcieport 0000:02:05.0: BAR 7: no space for [io size 0x1000]
pcieport 0000:02:05.0: BAR 7: failed to assign [io size 0x1000]
pcieport 0000:02:01.0: BAR 7: no space for [io size 0x1000]
pcieport 0000:02:01.0: BAR 7: failed to assign [io size 0x1000]
pci 0000:07:00.0: BAR 0: assigned [mem 0xc30000000-0xc31ffffff 64bit]
pci 0000:08:00.0: BAR 0: assigned [mem 0xc40000000-0xc4fffffff]
pci 0000:08:00.0: BAR 2: no space for [mem size 0x00100000]
pci 0000:08:00.0: BAR 2: failed to assign [mem size 0x00100000]
pci 0000:08:00.0: BAR 6: assigned [mem 0xc62400000-0xc6240ffff pref]
pci 0000:08:00.0: BAR 4: no space for [io size 0x0100]
pci 0000:08:00.0: BAR 4: failed to assign [io size 0x0100]
DIGI_KO INFO: digi: digi_probe: 184 Called for "0000:07:00.0", 07:00.0
digi_num_devs=0
digi_pci_drv 0000:07:00.0: enabling device (0000 -> 0002)
DIGI_KO INFO: digi: digi_probe: 224 Device 0, bar=0, start=0xc30000000,
end=0xc31ffffff, len=0x02000000, flags=0x00140204
DIGI_KO INFO: digi: digi_probe: 224 Device 0, bar=2, start=0x000000000,
end=0x000000000, len=0x00000000, flags=0x00000000
DIGI_KO INFO: digi: digi_probe: 224 Device 0, bar=4, start=0x000000000,
end=0x000000000, len=0x00000000, flags=0x00000000
DIGI_KO INFO: digi: digi_probe: 184 Called for "0000:08:00.0", 08:00.0
digi_num_devs=1
digi_pci_drv 0000:08:00.0: enabling device (0000 -> 0002)
DIGI_KO INFO: digi: digi_probe: 224 Device 1, bar=0, start=0xc40000000,
end=0xc4fffffff, len=0x10000000, flags=0x00040200
DIGI_KO INFO: digi: digi_probe: 224 Device 1, bar=2, start=0x000000000,
end=0x000000000, len=0x00000000, flags=0x00000000
DIGI_KO INFO: digi: digi_probe: 224 Device 1, bar=4, start=0x000000000,
end=0x000000000, len=0x00000000, flags=0x00000000
00:00.0 PCI bridge: Freescale Semiconductor Inc Device 0824 (rev 11)
01:00.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:01.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:04.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:05.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:06.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:08.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:09.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
06:00.0 Ethernet controller: Broadcom Corporation Device 8679 (rev 11)
06:00.1 Ethernet controller: Broadcom Corporation Device 8679 (rev 11)
07:00.0 Unassigned class [ff00]: PMC-Sierra Inc. Device 5990 (rev 01)
08:00.0 Non-VGA unclassified device: PMC-Sierra Inc. Device 5400 (rev 01)

PCI-E List1:::::::::::::::::::::::
List End:::::::::::::::::::::::::
pcieport 0000:00:00.0: BAR 7: no space for [io size 0x3000]
pcieport 0000:00:00.0: BAR 7: failed to assign [io size 0x3000]
pcieport 0000:00:00.0: BAR 7: no space for [io size 0x3000]
pcieport 0000:00:00.0: BAR 7: failed to assign [io size 0x3000]
pcieport 0000:01:00.0: BAR 7: no space for [io size 0x3000]
pcieport 0000:01:00.0: BAR 7: failed to assign [io size 0x3000]
pcieport 0000:01:00.0: BAR 7: no space for [io size 0x3000]
pcieport 0000:01:00.0: BAR 7: failed to assign [io size 0x3000]
pcieport 0000:02:01.0: BAR 7: no space for [io size 0x1000]
pcieport 0000:02:01.0: BAR 7: failed to assign [io size 0x1000]
pcieport 0000:02:05.0: BAR 7: no space for [io size 0x1000]
pcieport 0000:02:05.0: BAR 7: failed to assign [io size 0x1000]
pcieport 0000:02:09.0: BAR 7: no space for [io size 0x1000]
pcieport 0000:02:09.0: BAR 7: failed to assign [io size 0x1000]
pcieport 0000:02:09.0: BAR 7: no space for [io size 0x1000]
pcieport 0000:02:09.0: BAR 7: failed to assign [io size 0x1000]
pcieport 0000:02:05.0: BAR 7: no space for [io size 0x1000]
pcieport 0000:02:05.0: BAR 7: failed to assign [io size 0x1000]
pcieport 0000:02:01.0: BAR 7: no space for [io size 0x1000]
pcieport 0000:02:01.0: BAR 7: failed to assign [io size 0x1000]
linux_kernel_bde: module license 'Proprietary' taints kernel.
Disabling lock debugging due to kernel taint
linux-kernel-bde 0000:06:00.0: enabling device (0000 -> 0002)
INFO: linux-kernel-bde: 0.bar 2: phys=0xC60000000, len=0x00800000,
virt=0x8000080093D00000
INFO: linux-kernel-bde: 1.bar 0: phys=0xC61000000, len=0x00008000,
virt=0x8000080081990000
alloc_size 1000000, size 1000000 _alloc_mpool, 589

00:00.0 PCI bridge: Freescale Semiconductor Inc Device 0824 (rev 11)
01:00.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:01.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:04.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:05.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:06.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:08.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:09.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
06:00.0 Ethernet controller: Broadcom Corporation Device 8679 (rev 11)
06:00.1 Ethernet controller: Broadcom Corporation Device 8679 (rev 11)
07:00.0 Unassigned class [ff00]: PMC-Sierra Inc. Device 5990 (rev 01)
08:00.0 Non-VGA unclassified device: PMC-Sierra Inc. Device 5400 (rev 01)

PCI-E List2:::::::::::::::::::::::
List End:::::::::::::::::::::::::

************************************ PCIE ********************************

HyPhy/Digi PCI Scan #1
pcieGetDigiDevice: DIGI DEVICE: num_devs=2
----------------------------------------------
pcieGetDigiDevice: dev 0: bar=0, phys_lo=0x30000000, phys_hi=0x0000000c,
len=0x02000000
pcieGetDigiDevice: offset=0xc30000000
pcieGetDigiDevice: size=0x2000000
pcieGetDigiDevice: phys_addr=0xc30000000
pcieGetDigiDevice: gap=0x0
pcieGetDigiDevice: virt_addr=0x3fff49000000, virt_addr+gap=0x3fff49000000

Memory Map: PhyBaseAddress = [0xc30000000] MappedBaseAddress = [0x3fff49000000]

Size = [0x2000000]

pcieGetDigiDevice: DIGI_SET_DEV_VADDR virt_addr=0x3fff49000000 0x3fff49000000 dev=0

d0=0x49000000 d1=0x3fff
-----------------------------------
pcieGetDigiDevice: dev 1: bar=0, phys_lo=0x40000000, phys_hi=0x0000000c,
len=0x10000000
pcieGetDigiDevice: offset=0xc40000000
pcieGetDigiDevice: size=0x10000000
pcieGetDigiDevice: phys_addr=0xc40000000
pcieGetDigiDevice: gap=0x0
pcieGetDigiDevice: virt_addr=0x3fff28000000, virt_addr+gap=0x3fff28000000

Memory Map: PhyBaseAddress = [0xc40000000] MappedBaseAddress = [0x3fff28000000]

Size = [0x10000000]

pcieGetDigiDevice: DIGI_SET_DEV_VADDR virt_addr=0x3fff28000000 0x3fff28000000 dev=1

d0=0x28000000 d1=0x3fff
-----------------------------------
Loading BCM Kernel Objects...linux-kernel-bde: start linux_kernel_bde ...
params: device=linux-kernel-bde, cdev=linux-kernel-bde, flags=
linux-kernel-bde: start finished.
linux-user-bde: start linux_user_bde ...
params: device=linux-user-bde, cdev=linux-user-bde, flags=
linux-user-bde: start finished.
DMA pool size: 16777216
00:00.0 PCI bridge: Freescale Semiconductor Inc Device 0824 (rev 11)
01:00.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:01.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:04.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:05.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:06.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:08.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
02:09.0 PCI bridge: PLX Technology, Inc. PEX 8624 24-lane, 6-Port PCI Express Gen 2
(5.0 GT/s) Switch [ExpressLane] (rev bb)
06:00.0 Ethernet controller: Broadcom Corporation Device 8679 (rev 11)
06:00.1 Ethernet controller: Broadcom Corporation Device 8679 (rev 11)
07:00.0 Unassigned class [ff00]: PMC-Sierra Inc. Device 5990 (rev 01)
08:00.0 Non-VGA unclassified device: PMC-Sierra Inc. Device 5400 (rev 01)
-----------------------------------
 *****_NumOfJericho = 1

Memory Map: PhyBaseAddress = [0xc60000000] MappedBaseAddress = [0x3fff5c6f2000]

Size = [0x40000]

Memory Map: PhyBaseAddress = [0x59000000] MappedBaseAddress = [0x3fff48000000] Size

= [0x1000000]

*****_pcieGetJerichoDevice 0: Virtual Address[0x0x3fff5c6f2000]

BaseAddress[0x5c6f2000] devID[0x8679] revID[17] size[262144]******
-----------------------------------

****** m_NumOfPcieDevicesDiscovered 3 *********

PCI-E List:::::::::::::::::::::::
List End:::::::::::::::::::::::::
Adding entry, classID = 1316
Object = 1316: 0:7d:ffff:ffff:ffff:ffff:ffff:ffff:12

Adding entry, classID = 8060

Object = 8060: 0:7d:ffff:ffff:ffff:ffff:ffff:ffff:12

Bcm Fic Device Created!!! Bcm Fic address is 0x5C6F2000

EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:18:65535:65535:65535:65535:65535
BcmFicEqptPf::HwInit - Operation Watch Dog request to Start was sent!
INFO: <virtual void BcmFicDeviceImplementorPf::ColdInit():337> : ColdInit
Started

INFO: <eRetCode BcmFicDeviceImplementorPf::_InitializeInstallMembers():3706> :

Device Id from Install - 34425
INFO: <eRetCode BcmFicDeviceImplementorPf::_InitializeInstallMembers():3709> :
Rev Id from Install - 17
INFO: <eRetCode BcmFicDeviceImplementorPf::_InitializeInstallMembers():3712> :
Unit Id from Install - 0
INFO: <eRetCode BcmFicDeviceImplementorPf::_InitializeInstallMembers():3715> :
Number of cores from Install - 2
INFO: <eRetCode BcmFicDeviceImplementorPf::_InitializeInstallMembers():3718> :
Module Id from Install - 8
INFO: <eRetCode BcmFicDeviceImplementorPf::_InitializeInstallMembers():3721> :
Device Mode from Install - 1
INFO: <eRetCode BcmFicDeviceImplementorPf::_InitializeInstallMembers():3725> :
Device Data Mode Supported!
INFO: <eRetCode BcmFicDeviceImplementorPf::_InitializeInstallMembers():3726> :
Number of Remote Modules Available - 8!
INFO: <eRetCode BcmFicDeviceImplementorPf::_BcmTopologyFileParser():4455> : The
path for Json file is /usr/iox/BcmFiles/Mio200MeshTopologyFile.json

INFO: <eRetCode BcmFicDeviceImplementorPf::_CommonInit():3759> : Common Init

Started
INFO: <eRetCode BcmFicDeviceImplementorPf::_InitializeBcmFic():10694> :
Pronlonging WD Timeout to 100 seconds before Bcm Fic Install

<< RAMBOOT >> wdtSetWatchdogTimeout() not supported for Linux !

INFO: <bool BcmFicDeviceImplementorPf::_IsConfigBcmSet():10644> : New config.bcm
Path = /usr/iox/BcmFiles/config.bcm

INFO: <bool BcmFicDeviceImplementorPf::_IsConfigBcmSet():10657> :

BCMFIC Install Called
INFO: <bool BcmFicDeviceImplementorPf::_IsConfigBcmSet():10658> :
Config.bcm Title expected: #Mio200BBrd

INFO: <bool BcmFicDeviceImplementorPf::_IsConfigBcmSet():10662> :

Config.bcm Title actual: #Mio200BBrd

INFO: <eRetCode BcmFicDeviceImplementorPf::_Install():4172> :

BCMFIC Install Started

@@@_HandleOperationWatchDogStart
@@@Time in Ms [900000]
!!! Service Task: Operation Watch Dog Requested by: BcmFiqEqpt Cold Init of Device
!!! Service Task: Operation Watch Dog Started for Request: BcmFiqEqpt Cold Init of
Device
disabling interlaken port(0) LLFC via calender
disabling interlaken port(1) LLFC via calender

Poky (Yocto Project Reference Distro) 2.0 hcpm /dev/ttyS0

hcpm login: root

Password:
Login incorrect

hcpm login: root

Password:
root@hcpm:~# dbg
INFO: <eRetCode BcmFicDeviceImplementorPf::_Install():4384> :
BCMFIC install finished Succesfully!
Rc=0
INFO: <eRetCode BcmFicDeviceImplementorPf::_InitializeBcmFic():10699> : Setting
Back WD Timeout to default value: 100

<< RAMBOOT >> wdtSetWatchdogTimeout() not supported for Linux !

INFO: <bool BcmFicEgressBlockPf::_IsBandwidthPoolEnabled():1176> : !!! BCM BW
POOL is enabled !!!

INFO: <eRetCode BcmFicDeviceImplementorPf::_CommonInit():3862> : Common Init

Ended Succesfully!

INFO: <eRetCode BcmFicDeviceImplementorPf::_ConfigureDdrTunning():625> : Number

Of DDR tunning tries(5)(5)
cmd_arad_ddr_phy_tune(): shmoo_type=-1, Stat=0, Plot=0, ext_vref_range=0, Action=1,
ci_pbm=0x00000000000000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000000000000000ff
cmd_arad_ddr_phy_tune(): DRC_COMBO28. drc_ndx=0
cmd_arad_ddr_phy_tune(): DRC_COMBO28. drc_ndx=1
(null)

(null)

(null) cmd_arad_ddr_phy_tune(): DRC_COMBO28. drc_ndx=2

cmd_arad_ddr_phy_tune(): DRC_COMBO28. drc_ndx=3
cmd_arad_ddr_phy_tune(): DRC_COMBO28. drc_ndx=4
(null)
(null)

(null) (null) (null) (null) (null) (null) (null)

ll) (null) (null) (null) l) (null) (null) (null) (null) (null) (null) (null) (null)

(null) cmd_arad_ddr_phy_tune(): DRC_COMBO28. drc_ndx=5

cmd_arad_ddr_phy_tune(): DRC_COMBO28. drc_ndx=6
(null) (null) (null) (null) (null) DIGI_KO INFO: digi: digi_mmap_reserved: 569
Called for digi_dev_num=0, digi_dev_ptr=0x80000000002f83b8
DIGI_KO INFO: digi: digi_mmap_reserved: 571 requested vma: start=0x3fff3deb3000
end=0x3fff3e2b3000 offset=0x0 size=0x400000
DIGI_KO INFO: digi: digi_mmap_reserved: 597 Device Tree Probing
DIGI_KO INFO: digi: digi_mmap_reserved: 599 FDT digi_node=0x (null)
DIGI_KO INFO: digi: digi_mmap_reserved: 601 FDT digi_node not found, go to regular
dma allocation
DIGI_KO INFO: digi: digi_mmap: 729 Called for digi_dev_num=0,
digi_dev_ptr=0x80000000002f83b8
DIGI_KO INFO: digi: digi_mmap: 748 DMA memory allocation, requested size: 0x400000
bytes
DIGI_KO INFO: digi: digi_mmap: 752 DMA memory allocation mode: LAZY
DIGI_KO INFO: digi: digi_mmap: 775 dma_set_mask_and_coherent(31 bits addressing)
failed
DIGI_KO INFO: digi: digi_mmap: 778 dma_set_mask_and_coherent(32 bits addressing) OK
DIGI_KO INFO: digi: digi_mmap: 801 allocated_buffer kvaddr=0xc00000004b000000
dmaddr=0x000000004b000000 cpaddr=0x000000004b000000 bytes=4194304
DIGI_KO INFO: digi: digi_mmap: 814 start=0x3fff3deb3000 end=0x3fff3e2b3000
offset=0x0 size=0x400000
QsfpDD_D-ff00[3935]: unhandled signal 11 at 0000000000000878 nip 00000000119b93c4
lr 00000000119b08e0 code 30001
/usr/iox/Mio200BBoard.e5500lnx64.Release exited!!!

(null) cmd_arad_ddr_phy_tune(): DRC_COMBO28. drc_ndx=7

INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 1 is
L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 1 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 2 is
L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 2 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 3 is
L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 3 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 4 is
L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 4 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 5 is
L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 5 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 6 is
L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 6 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 7 is
L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 7 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 8 is
L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 8 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 9 is
L1 Port, using BW pool !!!
[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 9 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 10
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 10 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 11
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 11 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 12
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 12 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 13
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 13 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 14
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 14 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 15
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 15 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 16
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 16 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 17
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 17 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 18
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 18 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 19
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 19 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 20
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 20 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 21
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 21 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 22
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 22 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 23
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 23 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 24
is L1 Port, using BW pool !!!
[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 24 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 25
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 25 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 26
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 26 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 27
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 27 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 28
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 28 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 29
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 29 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 30
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 30 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 31
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 31 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 32
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 32 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 33
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 33 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 34
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 34 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 35
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 35 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 36
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 36 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 37
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 37 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 38
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 38 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 39
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 39 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 40
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 40 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 41
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 41 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 42
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 42 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 43
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 43 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 44
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 44 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 45
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 45 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 46
is L1 Port, using BW pool !!!
[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 46 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 47
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 47 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 48
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 48 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 49
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 49 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 50
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 50 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 51
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 51 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 52
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 52 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 53
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 53 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 54
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 54 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 55
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 55 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 56
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 56 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 57
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 57 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 58
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 58 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 59
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 59 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 60
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 60 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 61
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 61 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 62
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 62 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 63
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 63 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 64
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 64 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 65
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 65 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 66
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 66 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 67
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 67 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 68
is L1 Port, using BW pool !!!
[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 68 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 69
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 69 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 70
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 70 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 71
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 71 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 72
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 72 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 73
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 73 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 74
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 74 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 75
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 75 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 76
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 76 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 77
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 77 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 78
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 78 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 79
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 79 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 80
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 80 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 81
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 81 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 82
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 82 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 83
is L1 Port, using BW pool !!!
[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 83 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 84
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 84 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 85
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 85 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 86
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 86 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 87
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 87 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 88
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 88 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 89
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 89 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 90
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 90 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 91
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 91 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 92
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 92 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 93
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 93 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 94
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 94 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 95
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 95 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 96
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 96 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 97
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 97 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 98
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 98 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 99
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 99 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 100
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 100 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 101
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 101 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 102
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 102 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 103
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 103 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 104
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 104 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 105
is L1 Port, using BW pool !!!
[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 105 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 106
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 106 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 107
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 107 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 108
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 108 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 109
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 109 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 110
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 110 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 111
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 111 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 112
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 112 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 113
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 113 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 114
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 114 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 115
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 115 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 116
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 116 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 117
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 117 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 118
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 118 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 119
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 119 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 120
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 120 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 121
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 121 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 122
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 122 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 123
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 123 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 124
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 124 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 125
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 125 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 126
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 126 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 127
is L1 Port, using BW pool !!!
[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 127 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 128
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 128 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 129
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 129 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 130
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 130 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 131
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 131 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 132
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 132 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 133
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 133 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 134
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 134 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 135
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 135 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 136
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 136 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 137
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 137 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 138
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 138 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 139
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 139 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 140
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 140 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 141
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 141 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 142
is L1 Port, using BW pool !!!
[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 142 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 143
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 143 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 144
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 144 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 145
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 145 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 146
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 146 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 147
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 147 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 148
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 148 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 149
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 149 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 150
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 150 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 151
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 151 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 152
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 152 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 153
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 153 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 154
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 154 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 155
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 155 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 156
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 156 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 157
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 157 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 158
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 158 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 159
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 159 BW =
10485760
INFO: <void BcmFicEgressBlockPf::_SetLayerPort(tBcmFicPortType):1194> : !!! 160
is L1 Port, using BW pool !!!

[INFO][../../opb_io/SrcRoot/comps/BcmFicPfComp/BcmFicUtilsPfPkg/src/
IBandwidthAllocationPool.cpp:69 inside <void
IBandwidthAllocationPool::_SetPortBandwidth(uint16_t, size_t)>]: Port = 160 BW =
10485760
INFO: <eRetCode PolicerServicePf::_IPGCompensationSet(eBcmFicDeviceType):946> :
_IPGCompensationSet is not supported in Jericho!!!!

unit 0 preselector ID -2147479551 is already in use

Entry exists
INFO: <eRetCode
FieldProcessorServicePf::_CreatePreselectorSet(bcm_field_group_config_t*,
eBcmFicPmfPreselectors*, int, bcm_field_presel_t):1888> : The PreSelector is
already exist because of a cascade DB, ID= 0x80001001
unit 0 preselector ID -2147479551 is already in use
Entry exists
INFO: <eRetCode
FieldProcessorServicePf::_CreatePreselectorSet(bcm_field_group_config_t*,
eBcmFicPmfPreselectors*, int, bcm_field_presel_t):1888> : The PreSelector is
already exist because of a cascade DB, ID= 0x80001001
unit 0 preselector ID -2147479551 is already in use
Entry exists
INFO: <eRetCode
FieldProcessorServicePf::_CreatePreselectorSet(bcm_field_group_config_t*,
eBcmFicPmfPreselectors*, int, bcm_field_presel_t):1888> : The PreSelector is
already exist because of a cascade DB, ID= 0x80001001
INFO: <eRetCode BcmFicDeviceImplementorPf::_InitCpuPort():13573> : Cpu init for
core 1 is not supported yet
INFO: <eRetCode BcmFicDeviceImplementorPf::_CreateTrapForL2CPPacket():5586> :
Trapping for core 1 is not supported yet
INFO: <virtual void BcmFicDeviceImplementorPf::ColdInit():561> : ColdInit Done
Succesfully!
INFO: <virtual void BcmFicDeviceImplementorPf::ColdInit():573> : BcmFic
Initialization Done!
Initialization Result = 1

BcmFicEqptPf::HwInit - Operation Watch Dog request to Stop was sent!

@@@_HandleOperationWatchDogStop

Creating DigiG4Device succeeded

EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:16:65535:65535:65535:65535:65535
GetBoardConfig !!!!
Mio200DigiInstallDataPf::GetDevInfo - MIO200B
customer_sys_handle_create: (+handle) cust_sys = 0x3fff51dd2720
pmc_mem_ctxt_create: (+ctxt) ctxt_ptr = 0x3fff51dfcde0, buf_size = 2704696
customer_mmap: (+shared) shared memory created.
*** Ohp/Rcp/Gcc Infs. are initialized ***
Di-Rcp configuration for Digi -16777212:
-----------------------
Dest addr: 0x99 0x88 0x77 0x66 0x55 0x44
Src addr: 0xff 0xee 0xdd 0xcc 0xbb 0xaa
Eth type: 45056
Discard empty PDU: false
board_cfg.dev_info.card_type[DIGIG4_SLICE_1] 0
*** Ohp_en is ON. OHP are initialized in OhpInit***
digi >> DIGI_COPI1_ILKN0 Sifd Ilkn set FcMask:0x3ff , EnMask:0x42
digi >> DIGI_COPI1_ILKN1 Sifd Ilkn set FcMask:0x3ff , EnMask:0x0
Starting Update of Base Adresses in HyPhy Blocks. Base Address----->0x28000000

Creating HyPhy20FlexDevice succeeded

EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:17:65535:65535:65535:65535:65535
Taking EDC out of reset 0x14

Creating EdcDevice succeeded

EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:20:65535:65535:65535:65535:65535
MdioDevicePf::Init - Base address 0x9a010200 , Clause - 45 , Rate - 7
Taking EDC out of reset 0x14

Creating EdcDevice succeeded

EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:21:65535:65535:65535:65535:65535
MdioDevicePf::Init - Base address 0x9a010200 , Clause - 45 , Rate - 7
Taking EDC out of reset 0x14

Creating EdcDevice succeeded

EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:22:65535:65535:65535:65535:65535
MdioDevicePf::Init - Base address 0x9a010200 , Clause - 45 , Rate - 7
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:23:65535:65535:65535:65535:65535
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:24:65535:65535:65535:65535:65535
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:25:65535:65535:65535:65535:65535
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:26:65535:65535:65535:65535:65535
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:27:65535:65535:65535:65535:65535
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:28:65535:65535:65535:65535:65535
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:29:65535:65535:65535:65535:65535
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:30:65535:65535:65535:65535:65535
Harriet Device Created!!! FPGA address is 0x99000000
Harriet Device Object address is 0x53239590
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:19:65535:65535:65535:65535:65535
HarrietDevicePf - Init m_NumOfProtectionChannels 512
Top Init:
DigiIf[0] Init:
DigiIf[1] Init:
DigiIf[2] Init:
DigiIf[3] Init:
PhyMacSgmii[0] Init:
PhyMacSgmii[1] Init:
PhyMacSgmii[2] Init:
PhyMacSgmii[3] Init:
PhyMacSgmii[4] Init:
PhyMacSgmii[5] Init:
PhyMacSgmii[6] Init:
PhyMacSgmii[7] Init:
PhyMacSgmii[8] Init:
PhyMacSgmii[9] Init:
PhyMacSgmii[10] Init:
PhyMacSgmii[11] Init:
PhyMacSgmii[12] Init:
PhyMacSgmii[13] Init:
PhyMacSgmii[14] Init:
PhyMacSgmii[15] Init:
PhyMacSgmii[16] Init:
PhyMacSgmii[17] Init:
PhyMacSgmii[18] Init:
PhyMacSgmii[19] Init:
PhyMacSgmii[20] Init:
PhyMacSgmii[21] Init:
PhyMacSgmii[22] Init:
PhyMacSgmii[23] Init:
PhyMacSgmii[24] Init:
PhyMacSgmii[25] Init:
IlknBridgeTop Init:
IlknBridgeCore Init:
Sti Init:
Csel Init:
Protection Init:
PhyMac[0] Init:
PhyMac[1] Init:
PhyMac[2] Init:
PhyMac[3] Init:
PhyMac[4] Init:
PhyMac[5] Init:
PhyMac[6] Init:
PhyMac[7] Init:
PhyMac[8] Init:
PhyMac[9] Init:
PhyMac[10] Init:
PhyMac[11] Init:
PhyMac[12] Init:
PhyMac[13] Init:
PhyMac[14] Init:
PhyMac[15] Init:
PhyMac[16] Init:
PhyMac[17] Init:
PhyMac[18] Init:
PhyMac[19] Init:
PhyMac[20] Init:
PhyMac[21] Init:
PhyMac[22] Init:
PhyMac[23] Init:
PhyMac[24] Init:
PhyMac[25] Init:
Node name: UMDNode name: FileNameFound: Tag: FileName. Value:
HARRIET_TOP_r42_170625
Node name: InnerFileFormatFound: Tag: InnerFileFormat. Value: rbf
Node name: HwComponentFound: Tag: HwComponent. Value: my_proj
Node name: DescriptionFound: Tag: Description. Value: image_ts_17_6_22_17_27
Node name: BranchFound: Tag: Branch. Value: 0x0
Node name: RevisionFound: Tag: Revision. Value: 0x2a
Node name: TimeStampFound: Tag: TimeStamp. Value: 17:6:22:17:27
Node name: MinimalBranchCompatibilityFound: Tag: MinimalBranchCompatibility. Value:
0x0
Node name: MinimalRevisionCompatibilityFound: Tag: MinimalRevisionCompatibility.
Value: 0x0
GetVersionAndRevision Revision from header(42)
GetVersionAndRevision Version from header (0)
GetVersionAndRevision Revision from register (42)
GetVersionAndRevision Version from register (0)
HarrietDevicePf - ColdInit slot number (7)
HarrietTopBlockPf::PowerUpSequence A
Top install:
Csel install:
4 DigiIf install:
DigiIf[0] install:
DigiIf[1] install:
DigiIf[2] install:
DigiIf[3] install:
26 PHY_MAC install:
PHY_MAC[0] install:
PHY_MAC[1] install:
PHY_MAC[2] install:
PHY_MAC[3] install:
PHY_MAC[4] install:
PHY_MAC[5] install:
PHY_MAC[6] install:
PHY_MAC[7] install:
PHY_MAC[8] install:
PHY_MAC[9] install:
PHY_MAC[10] install:
PHY_MAC[11] install:
PHY_MAC[12] install:
PHY_MAC[13] install:
PHY_MAC[14] install:
PHY_MAC[15] install:
PHY_MAC[16] install:
PHY_MAC[17] install:
PHY_MAC[18] install:
PHY_MAC[19] install:
PHY_MAC[20] install:
PHY_MAC[21] install:
PHY_MAC[22] install:
PHY_MAC[23] install:
PHY_MAC[24] install:
PHY_MAC[25] install:
26 PHY_MAC_SGNII install:
PHY_MAC_SGMII[0] install:
PHY_MAC_SGMII[1] install:
PHY_MAC_SGMII[2] install:
PHY_MAC_SGMII[3] install:
PHY_MAC_SGMII[4] install:
PHY_MAC_SGMII[5] install:
PHY_MAC_SGMII[6] install:
PHY_MAC_SGMII[7] install:
PHY_MAC_SGMII[8] install:
PHY_MAC_SGMII[9] install:
PHY_MAC_SGMII[10] install:
PHY_MAC_SGMII[11] install:
PHY_MAC_SGMII[12] install:
PHY_MAC_SGMII[13] install:
PHY_MAC_SGMII[14] install:
PHY_MAC_SGMII[15] install:
PHY_MAC_SGMII[16] install:
PHY_MAC_SGMII[17] install:
PHY_MAC_SGMII[18] install:
PHY_MAC_SGMII[19] install:
PHY_MAC_SGMII[20] install:
PHY_MAC_SGMII[21] install:
PHY_MAC_SGMII[22] install:
PHY_MAC_SGMII[23] install:
PHY_MAC_SGMII[24] install:
PHY_MAC_SGMII[25] install:
Protection install:
IlknBridgeCore install:

HARRIET install finished

HarrietIlknBridgeTopBlockPf::PowerUpSequence A
HarrietDigiIfBlockPf::PowerUpSequence (DIGI_IF_3)
HarrietDevicePf::ColdInit: UPDTE_TRANSMIT_EN_V = 0SafeMemoryMngPf::SaveToSafeMem:
Creating new safe memory record for key = 8059:65 (class id , unique class id)
a_dataSize = 4
SafeMemoryMngPf::_DeallocateSafeMem: Safe memory allocations freed.
SafeMemoryMngPf::SaveToSafeMem: Creating new safe memory record for key = 8059:64
(class id , unique class id) a_dataSize = 4
SafeMemoryMngPf::_DeallocateSafeMem: Safe memory allocations freed.

Start Force To Ais Clock

GPLL is stabled there is no problem !!!!

End Force To Ais Clock

lag >> <lag:n/a,port:n/a> Is rcp fpga interface ready = no
HarrietDevicePf::GetBITId m_VersionFromRegister 0 m_VersionFromHeader 0
m_RevisionFromRegister 42 m_RevisionFromHeader 42
VirtualTfpEqptTPf::VirtualTfpEqptTPf, obj= 1266:
0:7e:ffff:ffff:ffff:ffff:ffff:ffff:0
VirtualTfpZTLEqptPf::this.ID = 1266: 0:7e:ffff:ffff:ffff:ffff:ffff:ffff:0
VirtualTfpEqptTPf::VirtualTfpEqptTPf, obj= 1266:
0:7e:ffff:ffff:ffff:ffff:ffff:ffff:1
VirtualTfpZTLEqptPf::this.ID = 1266: 0:7e:ffff:ffff:ffff:ffff:ffff:ffff:1
VirtualTfpEqptTPf::VirtualTfpEqptTPf, obj= 1266:
0:7e:ffff:ffff:ffff:ffff:ffff:ffff:2
VirtualTfpZTLEqptPf::this.ID = 1266: 0:7e:ffff:ffff:ffff:ffff:ffff:ffff:2
VirtualTfpEqptTPf::VirtualTfpEqptTPf, obj= 1266:
0:7e:ffff:ffff:ffff:ffff:ffff:ffff:3
VirtualTfpZTLEqptPf::this.ID = 1266: 0:7e:ffff:ffff:ffff:ffff:ffff:ffff:3
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:32:65535:65535:65535:65535:65535
Mio200BLaserDeviceInstallDataTPf::GetLaserManagerDefaultVal() Level0=32
StandardLaserQsfpDeviceTPf<t_BusType>::_UpdateLaserState Update FPGA
Mio200BLaserDeviceInstallDataTPf::GetLaserManagerDefaultVal() Level0=32
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:33:65535:65535:65535:65535:65535
Mio200BLaserDeviceInstallDataTPf::GetLaserManagerDefaultVal() Level0=33
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:34:65535:65535:65535:65535:65535
Mio200BLaserDeviceInstallDataTPf::GetLaserManagerDefaultVal() Level0=34
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:35:65535:65535:65535:65535:65535
Mio200BLaserDeviceInstallDataTPf::GetLaserManagerDefaultVal() Level0=35
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:36:65535:65535:65535:65535:65535
Mio200BLaserDeviceInstallDataTPf::GetLaserManagerDefaultVal() Level0=36
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:37:65535:65535:65535:65535:65535
Mio200BLaserDeviceInstallDataTPf::GetLaserManagerDefaultVal() Level0=37
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:38:65535:65535:65535:65535:65535
Mio200BLaserDeviceInstallDataTPf::GetLaserManagerDefaultVal() Level0=38
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:39:65535:65535:65535:65535:65535
Mio200BLaserDeviceInstallDataTPf::GetLaserManagerDefaultVal() Level0=39
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:40:65535:65535:65535:65535:65535
Mio200BLaserDeviceInstallDataTPf::GetLaserManagerDefaultVal() Level0=40
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:41:65535:65535:65535:65535:65535
Mio200BLaserDeviceInstallDataTPf::GetLaserManagerDefaultVal() Level0=41
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:42:65535:65535:65535:65535:65535
Mio200BLaserDeviceInstallDataTPf::GetLaserManagerDefaultVal() Level0=42
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:43:65535:65535:65535:65535:65535
Mio200BLaserDeviceInstallDataTPf::GetLaserManagerDefaultVal() Level0=43
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:44:65535:65535:65535:65535:65535
Mio200BLaserDeviceInstallDataTPf::GetLaserManagerDefaultVal() Level0=44
TempSensor created with 1 internal temp sensors
Registering to TempSensorManager for 1285:
0:7d:ffff:ffff:ffff:ffff:ffff:ffff:2d
: EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:45:65535:65535:65535:65535:65535
TempSensor created with 1 internal temp sensors
Registering to TempSensorManager for 1285:
0:7d:ffff:ffff:ffff:ffff:ffff:ffff:2e
: EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:46:65535:65535:65535:65535:65535
TempSensor created with 1 internal temp sensors
Registering to TempSensorManager for 1285:
0:7d:ffff:ffff:ffff:ffff:ffff:ffff:2f
: EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:47:65535:65535:65535:65535:65535
TempSensor created with 1 internal temp sensors
Registering to TempSensorManager for 1285:
0:7d:ffff:ffff:ffff:ffff:ffff:ffff:30
: EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:48:65535:65535:65535:65535:65535
TempSensor created with 1 internal temp sensors
Registering to TempSensorManager for 1285:
0:7d:ffff:ffff:ffff:ffff:ffff:ffff:31
: EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:49:65535:65535:65535:65535:65535
TempSensor created with 1 internal temp sensors
Registering to TempSensorManager for 1285:
0:7d:ffff:ffff:ffff:ffff:ffff:ffff:32
: EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:50:65535:65535:65535:65535:65535
TempSensor created with 1 internal temp sensors
Registering to TempSensorManager for 1285:
0:7d:ffff:ffff:ffff:ffff:ffff:ffff:33
: EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:51:65535:65535:65535:65535:65535
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:52:65535:65535:65535:65535:65535
EqptPf::Unlock - a_pUnlockingEqptObjId.ObjectId: 1501
0:125:65535:53:65535:65535:65535:65535:65535
Gcc Switch install:
Int Tree install:
Hdlc Ohp install:
Switch Debug install:

GCC FPGA install finished

EthernetDispatcherLinux.cpp:54 I EthernetDispatcherLinux: Set ifconfig eth1
up ...

*** End of Configuration Transaction ***

Synchronizer : Waiting to start Pm/Fault collection!
Hw Post Install Script Performed.
VirtualTfpEqptTPf::SetTfpType TfpType=17 RestartType=0, obj= 1266:
0:7e:ffff:ffff:ffff:ffff:ffff:ffff:0
StandardQsfpDevicePf::StandardQsfpDevicePf m_HandlerCount = 0, m_MngrLane = 0,
m_LaneTxStat = 255, m_GrpMngrNum = 0
QsfpDDDeviceTPf CTOR, m_MngrLane =0 obj= 8009:
0:7e:ffff:ffff:ffff:ffff:ffff:ffff:ff00
,
QsfpDDDeviceTPf::UpdateTrsAndTrsLaneBaseAddress Trs Lane Handling not supported
QsfpDDDeviceTPf::QsfpDDDeviceTPf m_HandlerCount = 0, m_MngrLane = 0, m_LaneTxStat =
255, m_GrpMngrNum = 0, maxNumofLanes= 8, obj= 8009:
0:7e:ffff:ffff:ffff:ffff:ffff:ffff:ff00
QsfpZTLDDDevicePf::QsfpZTLDDDevicePf m_HandlerCount = 0, m_MngrLane = 0,
m_LaneTxStat = 255, m_GrpMngrNum = 0, maxNumofLanes= 8
VirtualTfpZTLEqptPf::_CreateQsfpDDDevice: DEVICE CREATED, TfpType= 17, device.ID=
8009: 0:7e:ffff:ffff:ffff:ffff:ffff:ffff:ff00
, MaxLane=8, HermesI2cOffset=200
No input for Block Install - using all defaults.
QsfpDDDeviceTPf::_Install GrpNum 0 m_IsFanOutXcvr 0
QsfpDDDevicePf::Install - Install performed!!
QsfpDDZTLDevicePf::SetHotSwap m_HandlerCount = 0, m_GrpMngrNum = 0, m_MngrLane = 0,
a_IsPower = true, this = 0x532608c0, this.ID = 8009:
0:7e:ffff:ffff:ffff:ffff:ffff:ffff:ff00
QsfpDDZTLDevicePf::SetHotSwap - powering on xcvr for m_GrpMngrNum=0
QsfpDDZTLDevicePf::SetHotSwap, m_GrpMngrNum=0, power = 1, LaneNum = 0, time =
479227
QsfpDDDevicePf::TemperatureThreadMain - Thread Started for device level-0 = 65280.
VirtualTfpEqptTPf::SetTfpType TfpType=0 RestartType=0, obj= 1266:
0:7e:ffff:ffff:ffff:ffff:ffff:ffff:1
No input for Block Install - using all defaults.
VirtualTfpEqptTPf::SetTfpType TfpType=0 RestartType=0, obj= 1266:
0:7e:ffff:ffff:ffff:ffff:ffff:ffff:2
No input for Block Install - using all defaults.
VirtualTfpEqptTPf::SetTfpType TfpType=0 RestartType=0, obj= 1266:
0:7e:ffff:ffff:ffff:ffff:ffff:ffff:3
No input for Block Install - using all defaults.
Mio200BoardEqptPf::DoBackgroundActivities - BIT detected! count 1, waiting for
stabilization...
exceptionHandler: exception caught!
Exception Type : b - Segmentation fault
Program Counter: 119b93c4
Status register: 8002d000
ErrorAddress : 878
InstructionCode: 119b93c4

Task Id : f5f ()
SwVersion : 0.0
Time Stamp : 10/9/2000 14:15:0:6

Backtrace: 0x11408490 getMyBacktrace -0x897fe28

/usr/iox/Mio200BBoard.e5500lnx64.Release() [0x114bf0b4]
0x3fffa2720478 __kernel_sigtramp_rt64 +0
0x119b93c4 QsfpMgmtInterfacePf::GetBitTempStatus(unsigned short) -0x8478f4c
0x1165fd98 void std::this_thread::sleep_for<long, std::ratio<1l, 1000l>
>(std::chrono::duration<long, std::ratio<1l, 1000l> > const&) -0x876f710
0x119b08e0 QsfpDDDevicePf::TemperatureThreadMain() -0x8480518
0x119b5f30 void std::_Mem_fn_base<void (QsfpDDDevicePf::*)(), true>::operator()<,
void>(QsfpDDDevicePf*) const -0x847c2d8
0x119b5e08 void std::_Bind_simple<std::_Mem_fn<void (QsfpDDDevicePf::*)()>
(QsfpDDDevicePf*)>::_M_invoke<0ul>(std::_Index_tuple<0ul>) -0x847c3d0
0x119b5bd8 std::_Bind_simple<std::_Mem_fn<void (QsfpDDDevicePf::*)()>
(QsfpDDDevicePf*)>::operator()() -0x847c558
0x119b5afc std::thread::_Impl<std::_Bind_simple<std::_Mem_fn<void
(QsfpDDDevicePf::*)()> (QsfpDDDevicePf*)> >::_M_run() -0x847c5ec
0x3fffa224b994 +0x10c994
0x3fffa26f4b20 +0xbb20
0x3fffa1faa3a4 clone -0x9b6bc

cp: omitting directory '/usr/iox/ftproot/Report/varlog'

root@hcpm:~#
root@hcpm:~# dbg
2000/09/10 14:16:50 socat[3950] E connect(5, AF=2 127.0.0.1:1123, 16): Connection
refused
root@hcpm:~#