Spring 2025, PAF-IAST, Haripur, Pakistan

Advanced FPGA-based System

Design

Dr. Zahid Ullah

Associate Professor & Chairman (E&CE, FEST)

HEC Approved PhD Supervisor

Dept. of Electrical and Computer Engineering (E&CE)
Faculty of Engineering, Sciences, and Technology
(FEST)

Week # 1 (Feb. 3-8)

 Introduction about me
• Education
– Ph.D. in Electronic Engineering (2014), City University of Hong Kong
– M.S. in Electronic, Electrical, Control, and Instrumentation Engineering
(2010), Hanyang University, South Korea
– B.Sc. (Hons.) in Computer Systems Engineering (2006), UET Peshawar

• Specialization in FPGA-based CAM/TCAM Design

• Trained in Austrian partner universities
• Teaching experience in PAF-IAST, Haripur, CECOS University
Peshawar, CityU of HK, FAST Peshawar, Peshawar College of
Engineering, and UET Mardan
• Manager QEC, PAF-IAST, Haripur (May 2020 – Nov 2020)

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 Introduction about me
• Postgraduate Advisor, Associate Professor, and Chairman, Dept.
of EE, CECOS University Peshawar
• Supervised 3 PhD students.
• Supervised more than 20 MS students
• Email: zahid.ullah@fecid.paf-iast.edu.pk

• Office: Academic Block A2, A2-206

• Counselling hours: Appointment may be taken through email
• Google Scholar profile:
https://scholar.google.co.kr/citations?user=BE4cjcsAAAAJ&hl=en

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Please introduce yourself.

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 Advanced FPGA-based System Design
Course Description/Objectives
• HDL (hardware description language) and FPGAs (field-
programmable gate array) allow designers to quickly develop
and simulate a digital circuit, realize it on a prototyping device,
and verify operation of the physical implementation.
• FPGAs have become a major implementation technology for
digital systems because of several reasons such as its
reconfigure-ability, massive hardware parallelism, high clock
rate, and rapid prototyping capability.
• HDLs are used for modeling a digital system.
• Verilog HDL will be used in this course for describing digital
systems.
• This course will advance the student's understanding of Verilog
HDL and FPGA design flow.

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 Advanced FPGA-based System Design
Recommended readings
1. Advanced Digital Design with the Verilog HDL by
Michael D. Ciletti.
2. FPGA Prototyping by Verilog Examples by Pong P. Chu
3. Fundamental of Digital Logic with Verilog Design by
Stephen Brown and Zvonko Vranesic
4. Verilog HDL: A Guide to Digital Design and Synthesis,
Second Edition by Samir Palnitkar
5. Verilog Quick start 3rd Edition – A practical guide to
simulation and synthesis in Verilog by James M. Lee
6. Research papers/patents/ other related materials will be
provided

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 Advanced FPGA-based System Design
Evaluation
1. Project (report, demonstration, presentation) 5 x 3 = 15 marks
2. Assignment (3) 10 marks
3. Quizzes (3) 10
4. Mid Term 25 marks
5. Final Exam 40 marks

Note:
1. Select a project and then discuss with me. Every student has to
choose a project relevant to the course.
2. Mid Term Exam will be held in 7th/8th week.

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 Outline
• Design Methodology-An introduction
• IC Technology Options
• Design Using Verilog HDL
• Why to use HDL?
• Common Abstraction Levels in Verilog
• What is the difference between RTL and
behavioral models?

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Design Methodology-An introduction
• Objective of a design process is that design should be
correct and should meet requirements.
• Designers follow a design flow (on next slide), which has
certain steps that will be taken to design, verify,
synthesize, and test a system.
• Design flow involves several activities, from specification
and design entry to place-and-route and timing closure of
the system.
• Although the design flow appears to be linear, however; in
practice it is not. Various steps might be revisited as
design errors are discovered. For example, if problem in
meeting timing requirements.

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Design Methodology-An introduction
• Design Specification
• Design Partition
• Design Entry
• Design Integration and Verification
• Presynthesis Sign-Off
• Synthesis and Technology Mapping
• Placement and Routing
• Design Sign-off
• Design Validation (post PnR simulation)
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Design Methodology-An introduction
• Design Specification
❖ The design flow begins with a written specification for
the design.
❖ The specification document can be a very elaborative
statement of functionality, timing, area, power
consumption, testing, latency, and speed.
❖ Flow charts can be used to describe the sequence of
different processes (modules) in the design.
❖ The design priority could be power consumption,
latency, or speed.
❖ Should we go for high speed design? If yes, what other
parameters (such as area, latency) can be
compromised?
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Design Methodology-An introduction
• Design Partition
❖ Large circuits are partitioned into different modules of
different functionalities.
❖ The process by which a complex design is partitioned
into smaller and simpler functional units is called
hierarchical design.
❖ Hardware description language (HDL) supports
hierarchical design with mixed levels of abstraction by
providing a common framework for partitioning,
synthesizing, and verifying large, complex systems.
❖ The partitioned architecture consists of functional
units (modules) that are simpler than the whole, and
each is described by an HDL-based model.
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Design Methodology-An introduction
• Design Entry
❖ It means composing a language-based description of
the design and storing it in an electronic format in a
computer. (It is coding of a design in a computer
language.)
❖ Designs are described by HDL, like Verilog HDL,
which is used to write a behavioral description and
synthesize a gate-level realization of a large circuit that
it does do develop the gate-level realization by manual
entry.
❖ The ease of writing and changing Verilog descriptions
encourages architectural exploration.
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Design Methodology-An introduction
• Design Entry
❖ Moreover, a synthesize tool itself will find alternative
realizations of the same functionality generate reports
describing the attributes (for example power
consumption, area, latency, and speed) of the design.
❖ Synthesis tool creates an optimal internal
representation of a circuit before mapping the
description into the target technology (FPGA).
❖ HDL-based designs are easier to debug. A behavioral
description encapsulating complex functionality hides
underlying gate-level detail; thus, making the
debugging easier.
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Design Methodology-An introduction
• Design Entry
❖ HDL-based designs incorporate documentation within
the design by using descriptive names, by including
comments to clarify intent, and by specifying explicitly
the architectural relationships.
❖ Simulation of language-based model specifies the
functionality of the design.
❖ Behavioral modeling is the predominant descriptive
style, which enables the design of massive chips.
❖ Behavioral modeling describes the functionality of a
design by specifying what the design will do, not how
to build it in hardware. It specifies the input-output
model of a design and suppresses details about
physical, gate-level, implementation.
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Design Methodology-An introduction
• Design Entry
❖ Behavioral modeling encourages designers to
▪ Rapidly create a behavior prototype of a design (without
binding it to hardware details).
▪ Verify its functionality.
▪ Use a synthesis tool to optimize and map the design into a
selected physical technology.
❖ Verilog HDL accommodates mixed level of abstraction
so that portions of the design that are implemented at
the gate level (structurally) can be integrated and
simulated concurrently with other parts of the design
that are represented by behavioral description.
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Design Methodology-An introduction
• Design Entry
❖ The functionality of a design is verified by simulation.
❖ The design flow goes back to Step 3 until the functionality
of the design has been verified.
❖ The verification process is threefold:
▪ Development of test plan.
• What functionality needs to be verified?
▪ Development of testbench based on the test plan.
• Testbench is a Verilog module in which the unit under
test (UUT), the design, has been instantiated, together
with pattern generators that are to be applied to the inputs
of the model during simulation.
▪ Execution of the test.
• The testbench is exercised according to the test plan and
the response is verified against the original specifications
for the design.
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Design Methodology-An introduction
• Design Integration and Verification
❖ After each of the functional subunits of a partitioned
design have been verified to have correct functionality,
the architecture needs to be integrated and verified to
have correct functionality.
❖ Verification needs the development of a new testbench
for the overall architecture.
❖ This step in the design flow is very important and must
be executed thoroughly to ensure that the design that is
being signed off for synthesis is correct.

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Design Methodology-An introduction
• Presynthesis Sign-Off
❖ A demonstration of full functionality is to be provided
by the testbench, and any discrepancies between the
functionality of the Verilog behavior model and the
design specification must be resolved.
❖ Sign-off occurs after all functional errors have been
eliminated.

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Design Methodology-An introduction
• Gate-Level Synthesis and Technology
Mapping
❖ After the design has been signed off for synthesis, a
synthesis tool is used to create an optimal Boolean
description (gate-level netlist) and compose it in an
available technology.
❖ Synthesis tool removes redundant logic and seeks to
reduce area of the design.
❖ The netlist is then used to configure a target FPGA.

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Design Methodology-An introduction
• Gate-Level Synthesis and Technology
Mapping
❖ A gate-level netlist is a description of the circuit in
terms of gates and connections between them.
❖ Logic synthesis tools ensure that the gate-level netlist
meets timing, area, and power specifications.
❖ The gate-level netlist is input to an Automatic Place
and Route tool, which physically places the netlist
elements (placement) and connects them through wires
(routing).

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Design Methodology-An introduction
• Placement and Routing
❖ The placement and routing step arranges the synthesized
design on the FPGA chip and connects their signal paths.
• Design Sign-off
❖ Final sign-off occurs after all the design constraints have
been met and timing closure has been achieved.
• Design Validation (post PnR simulation)
❖ At this stage, design validation compares the response of the
implemented design to the response of the behavior model.
❖ Same testbench needs to be used to verify both models.
❖ Behavioral verification and post PnR verification must
provide the same output for the same testbench to ensure
that the design is correct.

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Design Methodology-An introduction
• Behavioral synthesis tools can create RTL (synthesizable
Verilog code) descriptions from a behavioral or
algorithmic description of the circuit.
• Designers will simply implement the algorithm in an HDL
at a very abstract level.
• EDA (Electronic Design Automation) tools will help the
designer convert the behavioral description to a final IC
chip.

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 IC Technology Options
• Physical realization of an architecture can be achieved by
ASIC (application-specific integrated circuited) or by
FPGA (field-programmable gate array).
• FPGAs have configurable architecture.
• Write and synthesize a Verilog description into a working
physical model by implementing it on FPGA.

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Digital Design Using Verilog HDL

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 Hardware Description Language
• When designs are of just a few gates; thus, it is possible to
verify them on paper. What about complex designs?

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 Hardware Description Language
• As designs grow larger and more complex, designers need
to use gate-level models, which are described in a
Hardware Description Language (HDL) to help with
verification before fabrication.

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 Hardware Description Language
• What about this design or
larger than this?
– Behavior description in
Verilog.
– Simulation for verification
using Verilog
– Designers can explore
designs using description in
Verilog.

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 Hardware Description Language
• HDL allows designers to talk about what the
hardware should do without actually designing the
hardware itself, or in other words HDLs allow
designers to separate behavior from
implementation at various levels of abstraction.

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 Hardware Description Language
• HDL allows designers to talk about what the
hardware should do without actually designing the
hardware itself, or in other words HDLs allow
designers to separate behavior from
implementation at various levels of abstraction.
▪ Designers can develop an executable functional
behavior.
▪ Designers can make decisions about performance,
power consumption, and area earlier in the design
process.
▪ Designers can create tools, which automatically
manipulate the design for verification, synthesis, and
optimization.

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 Why Verilog?
• About Verilog HDL, which we will use in this course.
– C-like syntax .
– Built-in types and logic representations.
– Design is composed of modules.
– Gate-level, dataflow, and behavioral modeling.
– Easy to learn and use.
– Most of us are familiar with C-like syntax
– Using hierarchical building blocks complexity of a design
can be easily managed.
– It is well-suited for both verification and synthesis.

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 An Example of coding in Verilog
• A Verilog module includes a module name and an
interface in the form of a port list.
– Must specify direction and bit-width for each port.

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 An Example of coding in Verilog
• Let’s have a look of the Verilog code of the following
circuit.

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 An Example of coding in Verilog
• Verilog coding example

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 An Example of coding in Verilog
• Verilog coding example

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Common Abstraction Levels in Verilog
• 3 Common Abstraction Levels in Verilog

▪ Behavior: Module’s high-level algorithm

is implemented with little concern for the
actual hardware.

▪ Dataflow: Module is implemented by

specifying how data flows between
registers. It is related to RTL (Register
Transfer Level), which is a synthesizable
code of the design.

▪ Gate-Level: Module is implemented in

terms of concrete logic gates (AND, OR,
NOT) and their interconnections.

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Common Abstraction Levels in Verilog
• 3 Common Abstraction Levels in Verilog
▪ The process of automatically generating a gate-level model from
either a dataflow or a behavioral model is called Logic
Synthesis.

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 RTL and behavioral models?
• What is the difference between RTL and behavioral
models?
▪ The term behavioral model is used for non-
synthesizable models, which is used for simulation
(functionality verification).
▪ The term RTL is used for the synthesizable models.
(The code which can be synthesized is called RTL
code).

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 Summary
• Design Methodology-An introduction
• IC Technology Options
• Design Using Verilog HDL
• Why to use HDL?
• Example of coding a circuit in Verilog
• Common Abstraction Levels in Verilog
• What is the difference between RTL and behavioral
models?

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