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Gaurav Bhole.

Gaurav Milind Bhole is a B.Tech student in Electronic and Telecommunication Engineering at Vishwakarma Institute of Technology, Pune, with a CGPA of 8.54. He has completed various projects and workshops, including a major project on a Pseudo Random Number Generator and research papers on an Advanced Security System and a Blind Text Reader. Gaurav possesses technical skills in Verilog and C, with experience in tools like Intel Quartus Prime and Raspberry Pi.

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Abuzer Shaikh
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31 views1 page

Gaurav Bhole.

Gaurav Milind Bhole is a B.Tech student in Electronic and Telecommunication Engineering at Vishwakarma Institute of Technology, Pune, with a CGPA of 8.54. He has completed various projects and workshops, including a major project on a Pseudo Random Number Generator and research papers on an Advanced Security System and a Blind Text Reader. Gaurav possesses technical skills in Verilog and C, with experience in tools like Intel Quartus Prime and Raspberry Pi.

Uploaded by

Abuzer Shaikh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Gaurav Milind Bhole +91-7666269023

Bachelor of Technology gaurav.bhole21@vit.edu


in Electronic and Telecommunication Engineering GitHub
Vishwakarma Institute of Technology, Pune, Maharashtra LinkedIn
Summary
B.Tech student at VIT Pune, skilled in Network Theory, Digital Electronics, Analog Electronics & Control System.
Passionate about Hardware systems and ready to contribute to real-world projects.

Education
Degree Institute Board / University CGPA/Percentage Year
B.Tech E&TC Vishwakarma Institute of Technology, Pune SPPU 8.54 2021-2025
Senior Secondary Pune Vidyarthi Griha‘s Dr. Kakasaheb Deodhar HSC 82.50% 2021
English School
Matriculation Horizon Academy ICSE 91.80% 2019

Training/Workshop
OpenROAD for Low-cost ASIC Design for Rapid Innovation. 17 - 24 Jan 2024
by IIT Guwahati in collaboration with the Ministry of Electronics and Information Technology
• This workshop focused on mastering the Verilog to GDS conversion process, covering essential aspects of RTL design,Static
Timing Analysis(STA),synthesis with Yosys, and utilizing tools like OpenROAD and KLayout.
• The workshop provided hands-on experience in physical design, routing, and performing rigorous physical verification using
industry-standard tools.

Projects
• Design and Analysis of Pseudo Random Number Generator July 2024 - Process
Major Project on Digital Design
– Aim: The project involves designing an 8-bit Pseudo Random Number Generator (PRNG) using reversible logic gates like
Fredkin, Toffoli, and Peres. The generated random number is converted to BCD and displayed on a 7-segment display,
highlighting the benefits of reversible logic of reducing power dissipation and delay.
• Design of Double Precision Floating Point Comparator March 2024 - May 2024
Course Project on Digital Design and Verilog
– Aim: Designed according to IEEE 754 standards, the double_precision_comparator module is designed to compare 64-bit
double-precision floating-point integers, considering equality and relative magnitude comparisons. Meticulously designed
the double_precision_comparator module to handle diverse scenarios, including parsing exponent and fraction components,
and addressing exceptions like Not a Number, positive/negative zero, and infinity.
• Advance Security System Aug 2022 - Dec 2022
Research Paper Published in IEEE 8th I2CT, 07th-09th April 2023, Co sponsored by IEEE Bombay section Research Paper
– Aim: This project uses RFID and Keypad technologies with NodeMCU(ESP8266) to lock/unlock doors. It sends email
notifications using SMTP protocol to the owner when the serial number does not matches with the number upload in
code,or when three unsuccessful keypad attempts occur.
• Blind Text Reader and Currency Detector Using Raspberry Pi Jan 2023 - Jun 2023
Research Paper Published in IEEE 7th ICCUBEA, 18th-19th August 2023, Co sponsored by IEEE Pune section Research Paper
– Aim: Create a text reader for the visually impaired on Raspberry Pi. Utilize a camera module for capturing text and
banknote images. Employ OCR to extract and convert text to speech. Implement image processing and machine learning to
detect and recognize banknote values. Showcase technology’s role in enhancing accessibility and independence for visually
impaired individuals.

Technical Skills
• Programming Languages: Verilog & C.
• Tools and Frameworks: Proteus, Oscilloscopes, Nvidia Jetson Nano(Linux) & RaspberryPi 4 Model B
• Tools: Intel Quartus Prime lite, OpenROAD, ModelSim& Xilinx Vivado

Certifications and Achievement


• NPTEL, Hardware Modeling Using Verilog by IIT Kharagpur
• TES-46, SSB-Screened-off by Join Indian Army
• Software Training & Personality Development, Wisdom Eye in association with faculties from IIT Kharagpur

Positions of Responsibility
• IOT Coordinator,Microsoft Learn Student Club, VIT Pune July. 2023 - Present
• Operation and Venue Coordinator,Computer Society of India Club, VIT Pune Sept. 2022 - Aug. 2023
• Head Boy,of Horizon Academy, Nashik July. 2018 - May. 2018

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