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ManoMachine Handout2

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0% found this document useful (0 votes)
12 views

ManoMachine Handout2

Uploaded by

amirreza13831
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Basic Computer Organization & Design 3

THE BASIC COMPUTER

• The Basic Computer has two components, a processor and


memory
• The memory has 4096 words in it
– 4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long

CPU RAM
0

15 0

4095

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 6 Instruction codes

ADDRESSING MODES
• The address field of an instruction can represent either
– Direct address: the address in memory of the data to use (the address of the
operand), or
– Indirect address: the address in memory of the address in memory of the data
to use
Direct addressing Indirect addressing

22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand
1350 Operand

+ +
AC AC

• Effective Address (EA)


– The address, that can be directly used without modification to access an
operand for a computation-type instruction, or as the target address for a
branch-type instruction
Computer Organization Computer Architectures Lab
Basic Computer Organization & Design 9 Registers

BASIC COMPUTER REGISTERS


Registers in the Basic Computer

11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 12 Registers

COMMON BUS SYSTEM

Read
INPR
Memory Write
S2 S1 S0 Reg
4096 x 16
ALU 0 0 0 x
Address E 0 0 1 AR
0 1 0 PC
0 1 1 DR
AC 1 0 0 AC
1 0 1 IR
L I C
1 1 0 TR
1 1 1 Mem
L I C L

L I C DR IR L I C

PC TR

AR OUTR LD

L I C

7 1 2 3 4 5 6

16-bit Common Bus


S0 S1 S2

Computer Organization Computer Architectures Lab


Basic Computer Organization & Design 14 Instructions

BASIC COMPUTER INSTRUCTIONS

• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~ 110)


15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)


15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)


15 12 11 0
1 1 1 1 I/O operation

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 15 Instructions

BASIC COMPUTER INSTRUCTIONS


Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC


CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC


OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off

Computer Organization Computer Architectures Lab


Basic Computer Organization & Design 19 Timing and control

TIMING SIGNALS
- Generated by 4-bit sequence counter and 4u16 decoder
- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .


Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC m
T0 0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 20

INSTRUCTION CYCLE

• In Basic Computer, a machine instruction is executed in the


following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an
indirect address
4. Execute the instruction

• After an instruction is executed, the cycle starts again at


step 1, for the next instruction

• Note: Every different processor has its own (different)


instruction cycle

Computer Organization Computer Architectures Lab

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