ManoMachine Handout2
ManoMachine Handout2
CPU RAM
0
15 0
4095
ADDRESSING MODES
• The address field of an instruction can represent either
– Direct address: the address in memory of the data to use (the address of the
operand), or
– Indirect address: the address in memory of the address in memory of the data
to use
Direct addressing Indirect addressing
300 1350
457 Operand
1350 Operand
+ +
AC AC
11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC
List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
Computer Organization Computer Architectures Lab
Read
INPR
Memory Write
S2 S1 S0 Reg
4096 x 16
ALU 0 0 0 x
Address E 0 0 1 AR
0 1 0 PC
0 1 1 DR
AC 1 0 0 AC
1 0 1 IR
L I C
1 1 0 TR
1 1 1 Mem
L I C L
L I C DR IR L I C
PC TR
AR OUTR LD
L I C
7 1 2 3 4 5 6
TIMING SIGNALS
- Generated by 4-bit sequence counter and 4u16 decoder
- The SC can be incremented or cleared.
T0
T1
T2
T3
T4
D3
CLR
SC
INSTRUCTION CYCLE