Lecture 8a

EE-215 Electronic Devices and Circuits

Dr. Muhammad Anis Chaudhary

Biasing in MOS Amplifier Circuits

Biasing in MOS Amplifier Circuits

Biasing in MOS Amplifier Circuits

Biasing in MOS Amplifier Circuits

• we have already determined

• In the design of a MOS amplifier circuit,

– it is essential to establish an appropriate dc operating point (or Q point or bias point) for the
MOSFET
– This step is known as biasing or bias design

• An appropriate bias point or dc operating point is characterized by

– a stable and predictable dc drain current ID and

– by a dc drain-to-source voltage VDS that ensures operation in the saturation region for all
expected input signal levels

Biasing in MOS Amplifier Circuits

Biasing by Fixing VGS

Biasing in MOS Amplifier Circuits

Biasing by Fixing VGS

• The simplest way to bias a MOSFET is to fix its gate-to-source voltage, VGS

– to the value that is required for the desired ID

• This voltage can be easily derived from the power-supply VDD

– by using an appropriate voltage divider

• however, this way of biasing a MOSFET is not a good approach

– because practically there are always some variations in Vt , Cox among the devices of same
type

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 1 of 26
 • As ID = 12 µnCox WL (VGS −Vt )2

– if Vt , Cox of two devices is different

– =⇒ ID will be different for the same value of VGS

Biasing in MOS Amplifier Circuits

Biasing by Fixing VGS

• also, Vt and µn are temperature dependent, and if we fix the value of VGS ,

– the drain current ID will become very temperature dependent

• thus for the fixed value of VGS , the resultant spread

– in the value of drain current can be substantial

– (∵ of change in Vt , Cox , µn among the devices of same type)

Biasing in MOS Amplifier Circuits

Biasing by Fixing VG and Connecting a Resistance in the Source

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 2 of 26
Biasing in MOS Amplifier Circuits
Biasing by Fixing VG and Connecting a Resistance in the Source

• An effective biasing technique for discrete MOSFET circuits,

– consists of fixing the dc voltage at the gate VG

– and connecting a resistance in the source lead

• By KVL , VG = VGS + ID RS =⇒ ID = VG −V
RS
GS

• from this relation, if VG is much greater than VGS

– =⇒ ID will be mostly determined by VG and RS

• even when VG is not much larger than VGS , resistor RS

– provides a negative feedback which acts to stabilize the value of the bias current ID

Biasing in MOS Amplifier Circuits

Biasing by Fixing VG and Connecting a Resistance in the Source

• VG = VGS + ID RS =⇒ ID = VG −V
RS
GS

• even when VG is not much larger than VGS , resistor RS

– provides a negative feedback which acts to stabilize the value of the bias current ID

• negative feedback here, means that if ID increases for any reason,

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 3 of 26
 – the equation (VG = VGS + ID RS ) indicates that since VG is a constant,
– VGS will have to decrease. this in turn results in a decrease in ID

• Thus the purpose of RS is to keep ID as constant as possible

Biasing in MOS Amplifier Circuits

Biasing by Fixing VG and Connecting a Resistance in the Source

• here iD − vGS characteristics for two devices that represent the extremes of a batch of MOSFETs,
are shown

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 4 of 26
 • The straight line, (superimposed on the device characteristics), represents the constraint imposed
by the bias circuit

– i.e. VG = VGS + ID RS

Biasing in MOS Amplifier Circuits

Biasing by Fixing VG and Connecting a Resistance in the Source

• The intersection of this straight line (VG = VGS + ID RS ) with the iD − vGS characteristic curve

– provides the coordinates (ID ,VGS ) of the bias point.

Biasing in MOS Amplifier Circuits

Biasing by Fixing VG and Connecting a Resistance in the Source

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 5 of 26
 • note that compared to the case of fixed VGS (left fig),

• here (right fig) the variation in ID is much smaller

Biasing in MOS Amplifier Circuits

Biasing by Fixing VG and Connecting a Resistance in the Source

• Note that the variation in ID decreases as VG and RS are made larger

• (i.e. the bias line is less steep when VG and RS are larger)

Biasing in MOS Amplifier Circuits

Biasing by Fixing VG and Connecting a Resistance in the Source

• Two possible practical discrete implementations of this bias scheme are shown in fig

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 6 of 26
 •

Biasing in MOS Amplifier Circuits

Biasing by Fixing VG and Connecting a Resistance in the Source

• here just one power supply VDD is required

• VG is derived using a voltage divider (RG1 , RG2 )

• As IG = 0 , RG1 and RG2 can be selected to be very large (usually in Mega ohms range)

• this allows the MOSFET to present a large Rin to the signal source

– that can be connected to the gate through a coupling capacitor

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 7 of 26
 •

Biasing in MOS Amplifier Circuits

Biasing by Fixing VG and Connecting a Resistance in the Source

• here capacitor CC1 blocks dc and thus enables us to couple

– the signal vsig to the amplifier input without disturbing the MOSFET bias point

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 8 of 26
Biasing in MOS Amplifier Circuits
Biasing by Fixing VG and Connecting a Resistance in the Source

• The value of CC1 should be selected large enough to

– approximate a short circuit at all signal frequencies of interest

Biasing in MOS Amplifier Circuits

Biasing by Fixing VG and Connecting a Resistance in the Source

• if two power supplies are available, a relatively simpler biasing scheme can be used

• as gate current is zero =⇒ VG = 0

• by KVL, VG = VGS + ID RS + (−VSS )

– 0 = VGS + ID RS −VSS =⇒ VSS = VGS + ID RS

• Note that this relation is of the same form as the relation for the previous circuit (VG = VGS + ID RS ),
if VG is replaced by VSS

• Note that RG establishes a dc ground at the gate

– and presents a high input resistance to a signal source

– which may be connected to the gate through a coupling capacitor

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 9 of 26
Biasing in MOS Amplifier Circuits
Example 5.12

• It is required to design the circuit of Fig. 5.52(c) to establish a dc drain current ID = 0.5mA.
The MOSFET is specified to have Vt = 1V and kn′ (W ⁄L) = 1mA/V 2 . For simplicity, neglect the
channel-length modulation effect (i.e., assume λ = 0). Use a power-supply VDD = 15V . Calculate
the percentage change in the value of ID obtained when the MOSFET is replaced with another unit
having the same kn′ (W ⁄L) but Vt = 1.5V .

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 10 of 26
Biasing in MOS Amplifier Circuits
Example 5.12

• As a rule of thumb, this biasing circuit can be designed by

– selecting RD and RS to provide one-third of the VDD

– as a voltage drop across each of the
– RD , the transistor (i.e. VDS ) and RS

• i.e. ID RD = VDS = ID RS = 31 VDD = 5V

– =⇒ VD = 10V , VS = 5V

• here 1st two conditions (ID RD = VDS = 13 VDD ) will ensure enough signal swing

• 3rd condition (ID RS = 13 VDD ) will ensure bias point stability

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 11 of 26
Biasing in MOS Amplifier Circuits
Example 5.12

• here ID = 0.5mA , VDD = 15V , Vt = 1V , kn′ (W ⁄L) = 1mA/V 2 , λ = 0

• as ID RD = ID RS = 5V , ID = 0.5mA
5 5
– =⇒ RD = RS = ID = 0.5m = 10kΩ

• to determine VGS

– ID = 0.5mA = 21 kn′ WL (VGS −Vt )2

– 0.5mA = 12 (1m) (VGS − 1)2
√
– 1 = (VGS − 1)2 =⇒ (VGS − 1) = 1 = ±1
– (VGS − 1) = 1 ∵ VOV cannot be -ve if ID = 0.5mA
– VGS = 2V

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 12 of 26
Biasing in MOS Amplifier Circuits
Example 5.12

• here ID = 0.5mA , VDD = 15V , Vt = 1V , kn′ (W ⁄L) = 1mA/V 2 , λ = 0

• VGS = 2V

– =⇒ VG −VS = 2V = VG − 5V ∵VS = 5V
– VG − 5 = 2 =⇒ VG = 7V

• now to determine RG1 and RG2

– for IRG1 = IRG2 = 1µA

VG 7
– =⇒ RG2 = IRG2 = 1µ = 7MΩ

• also by ohms law

– VDD = IRG1 (RG1 + RG2 )

– 15 = 1µ (RG1 + 7M)
– RG1 + 7M = 15M =⇒ RG1 = 8MΩ

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 13 of 26
Biasing in MOS Amplifier Circuits
Example 5.12

• here ID = 0.5mA , VDD = 15V , Vt = 1V , kn′ (W ⁄L) = 1mA/V 2 , λ = 0

• Note that the dc voltage at the drain is +10V and VDD = +15V

– =⇒ maximum +ve signal swing = 15 − 10 = 5V

• for maximum -ve signal swing

– VDS ≥ VGS −Vt = 2 − 1 = 1V

– VDS ≥ 1V
– here VDS = 5V
– =⇒ maximum -ve signal swing is -4V (i.e. down to VGS −Vt = 1V )

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 14 of 26
Biasing in MOS Amplifier Circuits
Example 5.12

• if now the MOSFET is replaced with another having Vt = 1.5V , kn′ (W ⁄L) = 1mA/V 2 , λ = 0

• the new ID is

– ID = 21 kn′ (W ⁄L) (VGS −Vt )2

– ID = 21 (1m) (VGS − 1.5)2 = 0.5m (VGS − 1.5)2

• As VG = VGS + ID RS

– =⇒ 7 = VGS + ID (10k)
7−VGS
– or ID = 10k

• eliminating ID from the above two equations

– ID = 0.5m (VGS − 1.5)2 = 7−VGS

10k
– (VGS − 1.5)2 = 7−VGS
5

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 15 of 26
Biasing in MOS Amplifier Circuits
Example 5.12

• (VGS − 1.5)2 = 7−VGS

5

2 + (1.5)2 − 2 (V ) (1.5) =
– VGS 7−VGS
GS 5
2 + 2.25 − 3V 7−VGS
– VGS GS = 5
2 + 11.25 − 15V
– 5VGS GS = 7 −VGS
2 + 4.25 − 14V
– 5VGS GS = 0
2 − 14V + 4.25 = 0
– 5VGS GS

√ √
−b± b2 −4ac 14± 142 −4(5)(4.25)
• =⇒ VGS = 2a = 2(5)
√
14± 111
– VGS = 10 = 2.4536 , 0.34643
– As Vt = 1.5V and as ID is not zero =⇒ VGS can not be equal to 0.34643V
– =⇒ VGS = 2.4536V

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 16 of 26
 7−VGS 7−2.4536
• As ID = 10k =⇒ ID = 10k = 0.45464mA

Biasing in MOS Amplifier Circuits

Example 5.12

• ID = 0.5mA when initially Vt = 1V

• and ID = 0.45464mA when Vt = 1.5V
• =⇒

– the change in ID is
– ∆ID = 0.45464m − 0.5m = −0.04536mA

• thus the %age change is

∆ID −0.04536m
– ID × 100 = 0.5m × 100 = −9.072%

Biasing in MOS Amplifier Circuits

Exercise 5.33

• Consider the MOSFET in Example 5.12 when fixed-VGS bias is used. Find the required value of
VGS to establish a dc bias current ID = 0.5mA. Recall that the device parameters are Vt = 1V ,
kn′ (W ⁄L) = 1mA/V 2 , and λ = 0. What is the percentage change in ID obtained when the transistor
is replaced with another having Vt = 1.5V ?

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 17 of 26
Biasing in MOS Amplifier Circuits
Exercise 5.33

• here ID = 0.5mA

– ID = 0.5m = 21 kn′ WL (VGS −Vt )2 =⇒ 0.5m = 21 (1m) (VGS −Vt )2

– 1 = (VGS −Vt )2 =⇒ VGS −Vt = 1 or VGS = 1 + 1 = 2V

• Now if Vt = 1.5V

– ID = 21 kn′ WL (VGS −Vt )2 = 21 (1m) (VGS − 1.5)2

– As VGS is fixed to 2V
– =⇒ ID = 12 (1m) (2 − 1.5)2 = 0.125mA

• ∆ID = 0.125m − 0.5m = −0.375mA

∆ID −0.375m
• and ID in percentage= 0.5m × 100 = −75%

Biasing in MOS Amplifier Circuits

Biasing Using a Drain-to-Gate Feedback Resistor

Biasing in MOS Amplifier Circuits

Biasing Using a Drain-to-Gate Feedback Resistor

• Another effective discrete-circuit biasing arrangement is possible by

– connecting a feedback resistor between the drain and the gate

• here the resistance RG (typically in mega ohms range) forces

– the dc voltage at the gate to be equal to that at the drain (∵IG = 0)

– =⇒ VG = VD or VGS = VDS

• by KVL

– VDD = ID RD +VDS
– VDD = ID RD +VGS ∵VGS = VDS
– or VDD = VGS + ID RD

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 18 of 26
 •

Biasing in MOS Amplifier Circuits

Biasing Using a Drain-to-Gate Feedback Resistor

• VDD = VGS + ID RD

– which is identical in form to the one obtained for the “biasing by fixing VG and connecting RS
in the source”

• VDD = VGS + ID RD

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 19 of 26
 •

• VG = VGS + ID RS

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 20 of 26
Biasing in MOS Amplifier Circuits
Biasing Using a Drain-to-Gate Feedback Resistor

• VDD = VGS + ID RD

• thus, if ID for some reason changes, say increases, then

– the above equation indicate that VGS must decrease.

– This decrease in VGS in turn causes a decrease in ID

• thus the negative feedback provided by RG works to keep

– the value of ID as constant as possible

Biasing in MOS Amplifier Circuits

Biasing Using a Drain-to-Gate Feedback Resistor

• to use this circuit as a CS amplifier, the input voltage

– signal can be applied to the gate via a coupling capacitor,

– so as not to disturb the dc bias condition

• the amplified output signal at the drain can be coupled to another part

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 21 of 26
 – of the circuit again via a coupling capacitor

Biasing in MOS Amplifier Circuits

Biasing Using a Constant-Current Source

Biasing in MOS Amplifier Circuits

Biasing Using a Constant-Current Source

• Another effective way for biasing a MOSFET is shown in fig and it utilizes a constant-current
source

• here RG (usually in mega ohms range) establishes a dc ground

– at the gate and presents a large resistance to an input signal source

– that can be coupled to the gate via a coupling capacitor

• resistor RD establishes an appropriate dc voltage at the drain

– to allow for the required signal swing while ensuring

– that the transistor always remains in the saturation region

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 22 of 26
 •

Biasing in MOS Amplifier Circuits

Biasing Using a Constant-Current Source

• the current source I is implemented by the current mirror circuit shown in fig b

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 23 of 26
Biasing in MOS Amplifier Circuits
Biasing Using a Constant-Current Source

• for the current mirror, the drain of Q1 is shorted to its gate

• =⇒ Q1 is operating in the saturation region

– As for saturation VDS ≥ VGS −Vt

– here VDS = VGS =⇒ 0 ≥ −Vt which is true

• neglecting the channel length modulation i.e. λ = 0

– =⇒ ID1 = 12 kn′ WL 1 (VGS −Vt )2

• here the drain current ID1 is supplied by VDD through R

– As gate current is zero =⇒ ID1 = IREF

Biasing in MOS Amplifier Circuits

Biasing Using a Constant-Current Source

• By KVL

– VDD = IREF R +VGS + (−VSS )

– or (VDD +VSS ) = VGS + IREF R where IREF = ID1

• Note that this equation is of the same form as the one in the previous biasing schemes

– =⇒ the drain current will not change much if Q1 is replaced by another transistor of same
type

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 24 of 26
 (VDD +VSS )−VGS
• IREF = ID1 = R

Biasing in MOS Amplifier Circuits

Biasing Using a Constant-Current Source
• now the transistor Q2 has the same VGS as Q1
• thus if we assume that Q2 is in saturation

– =⇒ I = ID2 = 12 kn′ WL 2 (VGS −Vt )2

– or ID2 / WL 2 = 21 kn′ (VGS −Vt )2

2
• as VGS , Vt and kn′ are the same for Q1 and Q2 , and as ID1 = 21 kn′ W


L 1 (VGS −Vt )

– =⇒ ID1 / WL 1 = 12 kn′ (VGS −Vt )2

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 25 of 26
 W
= 21 kn′ (VGS −Vt )2 = ID1 / W



• =⇒ ID2 / L 2 L 1

W W



– or ID2 / L 2 = ID1 / L 1

Biasing in MOS Amplifier Circuits

Biasing Using a Constant-Current Source

• or ID2 / WL 2 = ID1 / WL 1

• As ID2 = I and ID1 = IREF

– =⇒ I/ WL 2 = IREF / W



L 1

• =⇒
W


I = IREF WL
2
L 1

• thus I is related to IREF by the ratio of the aspect ratios of Q1 and Q2

• This circuit is known as a current mirror, and is very popular in the design of IC MOS amplifiers

EE-215 Electronic Devices and Circuits, Dr. M Anis Ch, Lecture 8a Page 26 of 26