RTL Design Guidelines

Udit Kumar, PhD, IIT Delhi.

15+ years experience, Author
https://www.linkedin.com/in/udit-kumar-phd-iit-delhi

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Disclaimer
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Outline
⚫ Need for Design Guidelines?
⚫ Guidelines for
 Naming
 Reset and Clocks
 Best coding practices
 Coding style to avoid unwanted Latches
 Multiple always blocks VS FSM
⚫ Generic FSM Design
⚫ Block/Interface integration and organization
⚫ Rules to avoid Simulation shoot-through
Importance of Design Guidelines
⚫ Faster design development
⚫ Less bugs
⚫ Optimized design
⚫ Helps in debugging
⚫ Helps in understanding the
code by other person.

©The VLSI Handbook: Design Principles,

Industry and Career Perspectives
Naming
File name: flop.v
⚫ The module name must match the
// Functionality of D flip flop without reset filename.
module #(parameter WIDTH=8) flop
(clk, din, dout) ; ⚫ There must be module high level
input clk; description on top of the file.
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout; ⚫ There should be one and only one
module per source code file.
always @ (posedge clk) begin
dout <= din; ⚫ Make port connections explicit
end
endmodule during instantiation.
⚫ Parameters should be in all CAPITAL
LETTERS, Keep default value of
parameters
⚫ Add appropriate comment in the
code.
Reset
⚫ Async reset is good when we want to control design reset
externally and want reset immediately. Majority of design
using Async reset.
⚫ Sync reset is part of data path and generally internally
generated signals. This is used on need basis.
⚫ For area optimization in the data path, there are flops without
async or sync reset.
⚫ Async reset should be used as active low or high?
 Usage of active low async reset is higher.
 Active low async reset is helpful to save power, and better noise
immunity, better control to bring whole design into reset state.
rst_n rst_n
soft_reset
din
dout dout
din

clk clk
Clock Dividers and Soft reset

soft_reset

soft_reset

No Clock for reset

Reset Synchronizer
⚫ A reset synchronizer synchronizes
the de-assertion of reset with
respect to the clock domain.

rst_n

clk

http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf
Clock
⚫ Use one edge of the clock in the whole design.
⚫ Avoid combination logic on the clock path.
⚫ Avoid convergence and divergence in the clock path clock
must be last element if there are convergence.
⚫ Only use specially designed module in the clock path. e.g. Mux
in the clock path must be glitch free mux.
⚫ Keep clock generation or reset generation in one module in
whole design.
 Register Initialization
module flop (clk, din, dout) ; module flop (clk, din, dout) ; module flop (clk, din, rst_n, dout) ;
input clk; input clk; input clk, rst_n;
input din; input din; input din;
output dout; output dout; output dout;

reg dout=0; reg dout; reg dout;

always @ (posedge clk) begin initial begin always @ (posedge clk or negedge
dout <= din; dout=1’b0; rst_n) begin
end end if (!rst_n) begin
endmodule dout <= 1’b0;
always @ (posedge clk) begin end else begin
dout <= din; dout <= din;
end end
endmodule end
endmodule

rst_n

Mismatch between
simulation and synthesis Expected: Post Synthesis
Blocking Vs non blocking usage
// Implement a functionality of mux
module #(parameter WIDTH=8) mux
(D0, D1, sel, dout) ;
⚫ Use blocking assignment for
input sel;
input [WIDTH-1:0] D0, D1; combinational logic.
output [WIDTH-1:0] dout;
⚫ Use non-blocking assignment
always @ ( D0 or D1 or sel) begin
if (sel) for sequential logic.
dout = D0;
else
end
dout = D1; ⚫ Do not use non-blocking
Blocking
endmodule assignment for signal being
used further as clock.
// Implement a functionality of D flip flop  Issue explained later in the
module #(parameter WIDTH=8) flop
(clk, din, dout) ; slides.
input clk;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;

always @ (posedge clk) begin

dout <= din;
end
endmodule Non Blocking
Multiple assignment for same variable
module flop (clk, rst_n, din, dout) ; module flop (clk, din, rst_n, dout) ;
input clk; input clk, rst_n;
input rst_n; input din;
input din; output dout;
output dout;
reg dout;

reg dout; always @ (posedge clk or negedge

rst_n) begin
always @ (negedge rst_n) begin if (!rst_n) begin
if (!rst_n) begin dout <= 1’b0;
dout <= 1’b0; end else begin
end dout <= din;
end end
end
always @ (posedge clk) begin endmodule
dout <= din;
end
endmodule

Avoid multiple assignments to the same variable except for array

 Avoid unwanted Latches
⚫ Avoid unwanted latches.
⚫ It is Good to use Latches on Clock gating, DFT (Lock up latch)
etc.

module flop (in1, in2, in3, sel, dout) ; module flop (in1, in2, in3, sel, dout) ; module flop (clk, sel, din, dout) ;
input in1, in2, in3, sel; input in1, in2, in3, sel; input clk, sel, din;
output dout; output dout; output dout;
reg dout; reg dout;
reg dout;
always @ (in1 or in2 or sel) always @ (in1 or in2 or sel)
if (sel) dout = in2; always @ (posedge clk) begin
dout = in1; if (sel) if (sel) begin
end dout = in1; dout <= din;
endmodule end end
endmodule
end
endmodule
Miscellaneous
⚫ Avoid Combinational Output
⚫ Avoid overflow/underflow in addition/subtraction.
⚫ Variable assignment/comparison must be done to variable of
same width.
⚫ Do no use full case and parallel case synthesis directive to
avoid simulation and synthesis mismatch.
⚫ Do not use case equality (===) or case inequality (!==), not
synthesizable.
⚫ There should be no gate or behavioral code instantiated at
the chip top level or core top level
⚫ Do not instantiate gate/cells in the RTL code.
Multiple always block Vs FSM
⚫ In each file, do not have large number of always blocks.
⚫ Many times, We tend to write sequence of activities as part of
different always blocks, that create difficulty in code
understanding, especially by others.

always@ always@ always@ always@ always@

⚫ A Simple rule, Large number of lines means higher chance of

bugs and reduced readability (difficult during debug)
1. always @ (posedge clk or negedge rst_n) 1. always @ (posedge clk or negedge rst_n) begin
2. begin 2. if (!rst_n) begin
3. if (!rst_n) 3. dout <= 1’b0;
4. begin 4. end else begin
5. dout <= 1’b0; 5. dout <= din;
6. end
7. else 6. end
8. begin 7. end
9. dout <= din;
10. end
11. end
FSM Design
⚫ A synthesizable FSM can be coded many ways.
⚫ Three most common used methods
 Three always block
 Two always block
 One always block
⚫ The easiest method to understand and implement is the two-
always block state machine
 Always block 1: Used for combinational logic
 Always block 2: Used for sequential logic
⚫ Any kind of FSM Mealy or moore can be implemented using
two always block.
 FSM Design: Two always blocks
module fsm (rst_n, clk, in, valid, counts) ;
input in;
output valid; 0
output [7:0] counts; state0
reg dout;
typedef enum {state0, state1, state2} fsm_state; Define the states 0,1 1
fsm_state curr_state, next_state; Define the 2 states varaible
reg [7:0] curr_cnt, next_cnt;
0
2 variable for all logic needing
reg valid;
to store the value
1
state2 state1
assign counts = curr_cnt; 1
always @ (*) begin // or use always_comb Combinational always block
next_state = curr_state; Assign current register value as next
next_cnt = curr_cnt;
valid = 1’b0; Assign default value for variable not needing sequential output
case (curr_state)
state0: begin
end
state1: begin Design Logic
end
state2: begin
end
end
always @ (posedge clk or negedge rst_n) begin Sequential always block
if (!rst_n) begin
curr_state <= state0;
next_cnt <= 8’b0; Reset default value
end else begin
curr_state <= next_state;
curr_cnt <= next_cnt; Store values into registers
end
end
endmodule
 FSM Design: Two always blocks
module fsm (rst_n, clk, in, ctrl) ;
input in;
output valid; 0
output [7:0] counts; state0
reg dout; 0,1 1
typedef enum {state0, state1, state2} fsm_state;
fsm_state curr_state, next_state; 0
reg [7:0] curr_cnt, next_cnt; 1
state2 state1
reg valid;
1
always_comb
next_state = curr_state;
next_cnt = curr_cnt + 1;
valid = 1’b0;
case (curr_state)
state0: begin
if (in)
next_state = state1; always @ (posedge clk or negedge rst_n) begin
end if (!rst_n) begin
state1: begin
if (in) curr_state <= state0;
next_state = state2; next_cnt <= 8’b0;
else end else begin
next_state = state0; curr_state <= next_state;
end curr_cnt <= next_cnt;
state2: begin end
next_state = state0;
valid = 1’b1;
end
end
 The CDC Path
⚫ When clocks are asynchronous, the signals that interface
between are called clock domain crossing paths.
Asynchronous Path,
No SETUP/HOLD Checks

SETUP/
SETUP/ HOLD
HOLD

C1 C2

⚫ Within each domain, setup & hold time checks ensure proper
functioning of the design.
⚫ No timing check exists on CDC Paths.
Clock crossing: Minimum Solution
⚫ A synchronizer is a device that samples the asynchronous
signal and output a signal that is synchronized to a destination
clock domain.
Asynchronous signal synchronizer
AW AS
AW
C1

Clk
Synchronized signal

Clk

AW

AS

Synchronizing cell should come from special cell library.

Assignment:
How to calculate number of Synchronizer flop for given frequency.
Use System Verilog Features: struct, interface

⚫ To share multiple related signals between the blocks, use struct or interfaces.
⚫ This can also be helpful when your signal list is changing over time, individual
signal taking will be an effort, whereas this can be simplified by adding one extra
element into the struct.
Block 2
Sub block

Block 1

typedef struct packed {

typedef struct packed {
logic req;
logic err1;
logic [7:0] data;
logic err2;
logic ack;
..
..
} error_struct
} reg_struct
Blocks Organization

<struct>.<reg_name>

Configuration space Core (RTL)

TX

Configuration registers

RX

<struct>.<err_name>
What is Shoot-thru?
⚫ When any signal jumps over an extra register within one
clock cycle.
 E.g. Input “din” crosses 2 register within one clock cycle.

dint
din dout
D D

In silicon => gate delay.

clk cint In simulator => events

Shoot-thru:
(events in data path ) <= (events in clock path)
How Simulation Shoot-thru occurs?

dint dout
din
D D
Reason : Extra Delta
delay in Clock Path
clk cint

din 0>1 clk 0>1

dint 0>1 cint 0>1

dout 0>1

clk
cint
din
dint Consequence : dout
same as din within
dout single clock
Will Verilog coding rules help?
25

⚫ Can blocking assignment in // Input data sampling

always @ (posedge clk, negedge rst_n) begin
combination blocks and non- if (rst_n==1’b0)
blocking in sequential avoid else
dint <= din;

simulation shoot-thru? dint <= din;

end
 Not, always….
// Capture data on divided
dint dout clock
din
D D always @ (posedge cint, negedge rst_n) begin
if (rst_n==1’b0)
dout <= 1’b0;
else
dout <= dint;
end
clk cdiv cint
// Clock generation
always @ (posedge clk, negedge rst_n) begin
if (rst_n==1’b0)
cint <= 1’b0;
Extra Delta-delay in Clock Path else
cint <= !cint;
end
Non-blocking assignments consume delta delay
26
So, How to detect shoot-thru issues?
⚫ By using an improved simulator?
 NO, as root cause of problem is that RTL Simulation has no
notion of timing delay & Hold checks.

⚫ By doing Gate level simulation?

 Yes but it is very costly.

⚫ By using robust RTL coding rules?

 Yes this is easy and efficient (see subsequent slides)
Rule 1 - Force scheduling of data
27
⚫ Force physical time delay in sequential data paths i.e.
 Sequential data assignment is delayed in ‘physical time’,
instead of ‘delta’ time.

Verilog VHDL
dint<= din after 1
dint <= #1 din ;
ns;
dint
dout
din
D D

clk cint

This ensures there is extra delay in data.

28
Rule 2 - No ‘physical delay’ in clock path

after 1ns ⚫ Delay on clock paths

dint dout
din
D D competes with delay on
Data path

clk cint

after 1ns ⚫ Clock vs Data scheduling

still un-reliable

This ensures a minimum delay on clock path.

Rule1 + Rule2 ensure that data is updated after
clock → no risk of shoot-thru
Link for other presentations
⚫ HDL Design using Verilog:
https://www.linkedin.com/feed/update/urn:li:activity:690110117
3491798016
⚫ Clock domain crossing:
https://www.linkedin.com/feed/update/urn:li:activity:688833351
1925866496
⚫ VLSI Design Flows and Open source tools:
 https://www.linkedin.com/feed/update/urn:li:activity:6886886690
405924864
⚫ https://www.sites.google.com/view/learnvlsi/webinar
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