PIC16F822/883/884/886/887

12.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities:
SYNCHRONOUS • Full-duplex asynchronous transmit and receive
ASYNCHRONOUS RECEIVER • Two-character input buffer
TRANSMITTER (EUSART) • One-character output buffer
• Programmable 8-bit or 9-bit character length
The Enhanced Universal Synchronous Asynchronous
• Address detection in 9-bit mode
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock • Input buffer overrun error detection
generators, shift registers and data buffers necessary • Received character framing error detection
to perform an input or output serial data transfer • Half-duplex synchronous master
independent of device program execution. The • Half-duplex synchronous slave
EUSART, also known as a Serial Communications • Programmable clock polarity in synchronous
Interface (SCI), can be configured as a full-duplex modes
asynchronous system or half-duplex synchronous
system. Full-Duplex mode is useful for The EUSART module implements the following
communications with peripheral systems, such as CRT additional features, making it ideally suited for use in
terminals and personal computers. Half-Duplex Local Interconnect Network (LIN) bus systems:
Synchronous mode is intended for communications • Automatic detection and calibration of the baud rate
with peripheral devices, such as A/D or D/A integrated • Wake-up on Break reception
circuits, serial EEPROMs or other microcontrollers.
• 13-bit Break character transmit
These devices typically do not have internal clocks for
baud rate generation and require the external clock Block diagrams of the EUSART transmitter and
signal provided by a master synchronous device. receiver are shown in Figure 12-1 and Figure 12-2.

FIGURE 12-1: EUSART TRANSMIT BLOCK DIAGRAM

Data Bus
TXIE
Interrupt
TXREG Register TXIF
8
MSb LSb TX/CK pin
(8) 0 Pin Buffer
• • • and Control
Transmit Shift Register (TSR)

TXEN

TRMT SPEN
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D
SYNC 1 X 0 0 0
SPBRGH SPBRG BRGH X 1 1 0 0
BRG16 X 1 0 1 0

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FIGURE 12-2: EUSART RECEIVE BLOCK DIAGRAM

SPEN CREN OERR RCIDL

RX/DT pin MSb RSR Register LSb

Pin Buffer Data
and Control Recovery
Stop (8) 7 ••• 1 0 Start

Baud Rate Generator FOSC RX9

÷n

BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPBRGH SPBRG BRGH X 1 1 0 0 FIFO
FERR RX9D RCREG Register
BRG16 X 1 0 1 0
8
Data Bus

RCIF Interrupt
RCIE

The operation of the EUSART module is controlled

through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCTL)
These registers are detailed in Register 12-1,
Register 12-2 and Register 12-3, respectively.

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12.1 EUSART Asynchronous Mode
The EUSART transmits and receives data using the Note 1: When the SPEN bit is set the RX/DT I/O pin
standard non-return-to-zero (NRZ) format. NRZ is is automatically configured as an input,
implemented with two levels: a VOH mark state which regardless of the state of the corresponding
represents a ‘1’ data bit, and a VOL space state which TRIS bit and whether or not the EUSART
represents a ‘0’ data bit. NRZ refers to the fact that receiver is enabled. The RX/DT pin data
consecutively transmitted data bits of the same value can be read via a normal PORT read but
stay at the output level of that bit without returning to a PORT latch data output is precluded.
neutral level between each bit transmission. An NRZ 2: The TXIF transmitter interrupt flag is set
transmission port idles in the mark state. Each character when the TXEN enable bit is set.
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or 12.1.1.2 Transmitting Data
more Stop bits. The Start bit is always a space and the
A transmission is initiated by writing a character to the
Stop bits are always marks. The most common data
TXREG register. If this is the first character, or the
format is 8 bits. Each transmitted bit persists for a period
previous character has been completely flushed from
of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud
the TSR, the data in the TXREG is immediately
Rate Generator is used to derive standard baud rate
transferred to the TSR register. If the TSR still contains
frequencies from the system oscillator. See Table 12-5
all or part of a previous character, the new character
for examples of baud rate configurations.
data is held in the TXREG until the Stop bit of the
The EUSART transmits and receives the LSb first. The previous character has been transmitted. The pending
EUSART’s transmitter and receiver are functionally character in the TXREG is then transferred to the TSR
independent, but share the same data format and baud in one TCY immediately following the Stop bit
rate. Parity is not supported by the hardware, but can transmission. The transmission of the Start bit, data bits
be implemented in software and stored as the ninth and Stop bit sequence commences immediately
data bit. following the transfer of the data to the TSR from the
TXREG.
12.1.1 EUSART ASYNCHRONOUS
TRANSMITTER 12.1.1.3 Transmit Interrupt Flag
The EUSART transmitter block diagram is shown in The TXIF interrupt flag bit of the PIR1 register is set
Figure 12-1. The heart of the transmitter is the serial whenever the EUSART transmitter is enabled and no
Transmit Shift Register (TSR), which is not directly character is being held for transmission in the TXREG.
accessible by software. The TSR obtains its data from In other words, the TXIF bit is only clear when the TSR
the transmit buffer, which is the TXREG register. is busy with a character and a new character has been
queued for transmission in the TXREG. The TXIF flag bit
12.1.1.1 Enabling the Transmitter is not cleared immediately upon writing TXREG. TXIF
The EUSART transmitter is enabled for asynchronous becomes valid in the second instruction cycle following
operations by configuring the following three control the write execution. Polling TXIF immediately following
bits: the TXREG write will return invalid results. The TXIF bit
is read-only, it cannot be set or cleared by software.
• TXEN = 1
The TXIF interrupt can be enabled by setting the TXIE
• SYNC = 0
interrupt enable bit of the PIE1 register. However, the
• SPEN = 1 TXIF flag bit will be set whenever the TXREG is empty,
All other EUSART control bits are assumed to be in regardless of the state of TXIE enable bit.
their default state. To use interrupts when transmitting data, set the TXIE
Setting the TXEN bit of the TXSTA register enables the bit only when there is more data to send. Clear the
transmitter circuitry of the EUSART. Clearing the SYNC TXIE interrupt enable bit upon writing the last character
bit of the TXSTA register configures the EUSART for of the transmission to the TXREG.
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and automatically
configures the TX/CK I/O pin as an output. If the TX/CK
pin is shared with an analog peripheral the analog I/O
function must be disabled by clearing the corresponding
ANSEL bit.

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12.1.1.4 TSR Status 12.1.1.6 Asynchronous Transmission Set-up:
The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH, SPBRG register pair and
status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired
TRMT bit is set when the TSR register is empty and is baud rate (see Section 12.3 “EUSART Baud
cleared when a character is transferred to the TSR Rate Generator (BRG)”).
register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing
until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit.
No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9 con-
poll this bit to determine the TSR status. trol bit. A set ninth data bit will indicate that the 8
Note: The TSR register is not mapped in data Least Significant data bits are an address when
memory, so it is not available to the user. the receiver is set for address detection.
4. Enable the transmission by setting the TXEN
12.1.1.5 Transmitting 9-Bit Characters control bit. This will cause the TXIF interrupt bit
The EUSART supports 9-bit character transmissions. to be set.
When the TX9 bit of the TXSTA register is set the 5. If interrupts are desired, set the TXIE interrupt
EUSART will shift 9 bits out for each character transmit- enable bit. An interrupt will occur immediately
ted. The TX9D bit of the TXSTA register is the ninth, provided that the GIE and PEIE bits of the
and Most Significant, data bit. When transmitting 9-bit INTCON register are also set.
data, the TX9D data bit must be written before writing 6. If 9-bit transmission is selected, the ninth bit
the 8 Least Significant bits into the TXREG. All nine bits should be loaded into the TX9D data bit.
of data will be transferred to the TSR shift register 7. Load 8-bit data into the TXREG register. This
immediately after the TXREG is written. will start the transmission.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 12.1.2.7 “Address
Detection” for more information on the Address mode.

FIGURE 12-3: ASYNCHRONOUS TRANSMISSION

Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC4/C2OUT/TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)

Word 1
TRMT bit Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)

FIGURE 12-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)

Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
RC4/C2OUT/TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit 1 TCY Word 1 Word 2
(Interrupt Reg. Flag)
1 TCY
TRMT bit Word 1 Word 2
(Transmit Shift Transmit Shift Reg.
Reg. Empty Flag) Transmit Shift Reg.

Note: This timing diagram shows two consecutive transmissions.

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TABLE 12-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission.

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12.1.2 EUSART ASYNCHRONOUS 12.1.2.2 Receiving Data
RECEIVER The receiver data recovery circuit initiates character
The Asynchronous mode would typically be used in reception on the falling edge of the first bit. The first bit,
RS-232 systems. The receiver block diagram is shown also known as the Start bit, is always a zero. The data
in Figure 12-2. The data is received on the RX/DT pin recovery circuit counts one-half bit time to the center of
and drives the data recovery block. The data recovery the Start bit and verifies that the bit is still a zero. If it is
block is actually a high-speed shifter operating at 16 not a zero then the data recovery circuit aborts
times the baud rate, whereas the serial Receive Shift character reception, without generating an error, and
Register (RSR) operates at the bit rate. When all 8 or 9 resumes looking for the falling edge of the Start bit. If
bits of the character have been shifted in, they are the Start bit zero verification succeeds then the data
immediately transferred to a two character First-In- recovery circuit counts a full bit time to the center of the
First-Out (FIFO) memory. The FIFO buffering allows next bit. The bit is then sampled by a majority detect
reception of two complete characters and the start of a circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
third character before software must start servicing the This repeats until all data bits have been sampled and
EUSART receiver. The FIFO and RSR registers are not shifted into the RSR. One final bit time is measured and
directly accessible by software. Access to the received the level sampled. This is the Stop bit, which is always
data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
12.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this
The EUSART receiver is enabled for asynchronous character. See Section 12.1.2.4 “Receive Framing
operation by configuring the following three control bits: Error” for more information on framing errors.

• CREN = 1 Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
• SYNC = 0
to the EUSART receive FIFO and the RCIF interrupt
• SPEN = 1 flag bit of the PIR1 register is set. The top character in
All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the
their default state. RCREG register.
Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional
receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun
of the TXSTA register configures the EUSART for condition is cleared. See Section 12.1.2.5
asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more
RCSTA register enables the EUSART and automatically information on overrun errors.
configures the RX/DT I/O pin as an input. If the RX/DT
pin is shared with an analog peripheral the analog I/O 12.1.2.3 Receive Interrupts
function must be disabled by clearing the corresponding The RCIF interrupt flag bit of the PIR1 register is set
ANSEL bit. whenever the EUSART receiver is enabled and there is
Note: When the SPEN bit is set the TX/CK I/O an unread character in the receive FIFO. The RCIF
pin is automatically configured as an interrupt flag bit is read-only, it cannot be set or cleared
output, regardless of the state of the by software.
corresponding TRIS bit and whether or not RCIF interrupts are enabled by setting the following
the EUSART transmitter is enabled. The bits:
PORT latch is disconnected from the
• RCIE interrupt enable bit of the PIE1 register
output driver so it is not possible to use the
TX/CK pin as a general purpose output. • PEIE peripheral interrupt enable bit of the
INTCON register
• GIE global interrupt enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.

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12.1.2.4 Receive Framing Error 12.1.2.7 Address Detection
Each character in the receive FIFO buffer has a A special Address Detection mode is available for use
corresponding framing error Status bit. A framing error when multiple receivers share the same transmission
indicates that a Stop bit was not seen at the expected line, such as in RS-485 systems. Address detection is
time. The framing error status is accessed via the enabled by setting the ADDEN bit of the RCSTA
FERR bit of the RCSTA register. The FERR bit register.
represents the status of the top unread character in the Address detection requires 9-bit character reception.
receive FIFO. Therefore, the FERR bit must be read When address detection is enabled, only characters
before reading the RCREG. with the ninth data bit set will be transferred to the
The FERR bit is read-only and only applies to the top receive FIFO buffer, thereby setting the RCIF interrupt
unread character in the receive FIFO. A framing error bit. All other characters will be ignored.
(FERR = 1) does not preclude reception of additional Upon receiving an address character, user software
characters. It is not necessary to clear the FERR bit. determines if the address matches its own. Upon
Reading the next character from the FIFO buffer will address match, user software must disable address
advance the FIFO to the next character and the next detection by clearing the ADDEN bit before the next
corresponding framing error. Stop bit occurs. When user software detects the end of
The FERR bit can be forced clear by clearing the SPEN the message, determined by the message protocol
bit of the RCSTA register which resets the EUSART. used, software places the receiver back into the
Clearing the CREN bit of the RCSTA register does not Address Detection mode by setting the ADDEN bit.
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note: If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.

12.1.2.5 Receive Overrun Error

The receive FIFO buffer can hold two characters. An
overrun error will be generated If a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is set.
The characters already in the FIFO buffer can be read
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.

12.1.2.6 Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9 bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.

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12.1.2.8 Asynchronous Reception Set-up: 12.1.2.9 9-bit Address Detection Mode Set-up
1. Initialize the SPBRGH, SPBRG register pair and This mode would typically be used in RS-485 systems.
the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address
desired baud rate (see Section 12.3 “EUSART Detect Enable:
Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH, SPBRG register pair and
2. Enable the serial port by setting the SPEN bit. the BRGH and BRG16 bits to achieve the
The SYNC bit must be clear for asynchronous desired baud rate (see Section 12.3 “EUSART
operation. Baud Rate Generator (BRG)”).
3. If interrupts are desired, set the RCIE interrupt 2. Enable the serial port by setting the SPEN bit.
enable bit and set the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous
INTCON register. operation.
4. If 9-bit reception is desired, set the RX9 bit. 3. If interrupts are desired, set the RCIE interrupt
5. Enable reception by setting the CREN bit. enable bit and set the GIE and PEIE bits of the
6. The RCIF interrupt flag bit will be set when a INTCON register.
character is transferred from the RSR to the 4. Enable 9-bit reception by setting the RX9 bit.
receive buffer. An interrupt will be generated if 5. Enable address detection by setting the ADDEN
the RCIE interrupt enable bit was also set. bit.
7. Read the RCSTA register to get the error flags 6. Enable reception by setting the CREN bit.
and, if 9-bit data reception is enabled, the ninth 7. The RCIF interrupt flag bit will be set when a
data bit. character with the ninth bit set is transferred
8. Get the received 8 Least Significant data bits from the RSR to the receive buffer. An interrupt
from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit
register. was also set.
9. If an overrun occurred, clear the OERR flag by 8. Read the RCSTA register to get the error flags.
clearing the CREN receiver enable bit. The ninth data bit will always be set.
9. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.

FIGURE 12-5: ASYNCHRONOUS RECEPTION

Start Start Start
RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop
bit bit bit
Rcv Shift
Reg
Rcv Buffer Reg
Word 1 Word 2
RCREG RCREG
RCIDL

Read Rcv
Buffer Reg
RCREG

RCIF
(Interrupt Flag)

OERR bit
CREN

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.

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TABLE 12-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception.

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12.2 Clock Accuracy with The first (preferred) method uses the OSCTUNE
Asynchronous Operation register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
The factory calibrates the internal oscillator block out- changes to the system clock source. See 4.5 “Internal
put (INTOSC). However, the INTOSC frequency may Clock Modes” for more information.
drift as VDD or temperature changes, and this directly
The other method adjusts the value in the Baud Rate
affects the asynchronous baud rate. Two methods may
Generator. This can be done automatically with the
be used to adjust the baud rate clock, but both require
Auto-Baud Detect feature (see Section 12.3.1 “Auto-
a reference clock source of some kind.
Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.

REGISTER 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

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REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.

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REGISTER 12-3: BAUDCTL: BAUD RATE CONTROL REGISTER

R-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 5 Unimplemented: Read as ‘0’
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Transmit inverted data to the RB7/TX/CK pin
0 = Transmit non-inverted data to the RB7/TX/CK pin
Synchronous mode:
1 = Data is clocked on rising edge of the clock
0 = Data is clocked on falling edge of the clock
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge. No character will be received byte RCIF will be set. WUE will
automatically clear after RCIF is set.
0 = Receiver is operating normally
Synchronous mode:
Don’t care
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care

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12.3 EUSART Baud Rate Generator If the system clock is changed during an active receive
(BRG) operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
The Baud Rate Generator (BRG) is an 8-bit or 16-bit make sure that the receive operation is Idle before
timer that is dedicated to the support of both the changing the system clock.
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the EXAMPLE 12-1: CALCULATING BAUD
BRG16 bit of the BAUDCTL register selects 16-bit RATE ERROR
mode.
For a device with FOSC of 16 MHz, desired baud rate
The SPBRGH, SPBRG register pair determines the of 9600, Asynchronous mode, 8-bit BRG:
period of the free running baud rate timer. In
F OS C
Asynchronous mode the multiplier of the baud rate Desired Baud Rate = ---------------------------------------------------------------------
64 ( [SPBRGH:SPBRG] + 1 )
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCTL register. In Solving for SPBRGH:SPBRG:
Synchronous mode, the BRGH bit is ignored.
FOSC
---------------------------------------------
Table 12-3 contains the formulas for determining the Desired Baud Rate
X = --------------------------------------------- – 1
baud rate. Example 12-1 provides a sample calculation 64
for determining the baud rate and baud rate error. 16000000
------------------------
Typical baud rates and error values for various 9600
= ------------------------–1
asynchronous modes have been computed for your 64
convenience and are shown in Table 12-3. It may be = [ 25.042 ] = 25
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate 16000000
Calculated Baud Rate = ---------------------------
64 ( 25 + 1 )
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies. = 9615
Writing a new value to the SPBRGH, SPBRG register
Calc. Baud Rate – Desired Baud Rate
pair causes the BRG timer to be reset (or cleared). This Error = --------------------------------------------------------------------------------------------
Desired Baud Rate
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate. ( 9615 – 9600 )
= ---------------------------------- = 0.16%
9600

TABLE 12-3: BAUD RATE FORMULAS

Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH

0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)]

0 0 1 8-bit/Asynchronous
FOSC/[16 (n+1)]
0 1 0 16-bit/Asynchronous
0 1 1 16-bit/Asynchronous
1 0 x 8-bit/Synchronous FOSC/[4 (n+1)]
1 1 x 16-bit/Synchronous
Legend: x = don’t care, n = value of SPBRGH, SPBRG register pair

TABLE 12-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.

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TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
BAUD
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 1221 1.73 255 1200 0.00 239 1200 0.00 143 1202 0.16 103
2400 2404 0.16 129 2400 0.00 119 2400 0.00 71 2404 0.16 51
9600 9470 -1.36 32 9600 0.00 29 9600 0.00 17 9615 0.16 12
10417 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 10417 0.00 11
19.2k 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 — — —
57.6k — — — 57.60k 0.00 7 57.60k 0.00 2 — — —
115.2k — — — — — — — — — — — —

SYNC = 0, BRGH = 0, BRG16 = 0

BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300 0.16 207 300 0.00 191 300 0.16 103 300 0.16 51
1200 1202 0.16 51 1200 0.00 47 1202 0.16 25 1202 0.16 12
2400 2404 0.16 25 2400 0.00 23 2404 0.16 12 — — —
9600 — — — 9600 0.00 5 — — — — — —
10417 10417 0.00 5 — — — 10417 0.00 2 — — —
19.2k — — — 19.20k 0.00 2 — — — — — —
57.6k — — — 57.60k 0.00 0 — — — — — —
115.2k — — — — — — — — — — — —

SYNC = 0, BRGH = 1, BRG16 = 0

BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — 2404 0.16 207
9600 9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51
10417 10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19231 0.16 25
57.6k 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8
115.2k 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 — — —

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TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0

BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — 300 0.16 207
1200 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51
2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25
9600 9615 0.16 25 9600 0.00 23 9615 0.16 12 — — —
10417 10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5
19.2k 19.23k 0.16 12 19.2k 0.00 11 — — — — — —
57.6k — — — 57.60k 0.00 3 — — — — — —
115.2k — — — 115.2k 0.00 1 — — — — — —

SYNC = 0, BRGH = 0, BRG16 = 1

BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 299.9 -0.02 1666
1200 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 1199 -0.08 416
2400 2399 -0.03 520 2400 0.00 479 2400 0.00 287 2404 0.16 207
9600 9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51
10417 10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19.23k 0.16 25
57.6k 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8
115.2k 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 — — —

SYNC = 0, BRGH = 0, BRG16 = 1

BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.1 0.04 832 300.0 0.00 767 299.8 -0.108 416 300.5 0.16 207
1200 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51
2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25
9600 9615 0.16 25 9600 0.00 23 9615 0.16 12 — — —
10417 10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5
19.2k 19.23k 0.16 12 19.20k 0.00 11 — — — — — —
57.6k — — — 57.60k 0.00 3 — — — — — —
115.2k — — — 115.2k 0.00 1 — — — — — —

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TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 300.0 0.00 6666
1200 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 1200 -0.02 1666
2400 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 2401 0.04 832
9600 9597 -0.03 520 9600 0.00 479 9600 0.00 287 9615 0.16 207
10417 10417 0.00 479 10425 0.08 441 10433 0.16 264 10417 0 191
19.2k 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 19.23k 0.16 103
57.6k 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 57.14k -0.79 34
115.2k 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 117.6k 2.12 16

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.01 3332 300.0 0.00 3071 299.9 -0.02 1666 300.1 0.04 832
1200 1200 0.04 832 1200 0.00 767 1199 -0.08 416 1202 0.16 207
2400 2398 0.08 416 2400 0.00 383 2404 0.16 207 2404 0.16 103
9600 9615 0.16 103 9600 0.00 95 9615 0.16 51 9615 0.16 25
10417 10417 0.00 95 10473 0.53 87 10417 0.00 47 10417 0.00 23
19.2k 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 25 19.23k 0.16 12
57.6k 58.82k 2.12 16 57.60k 0.00 15 55.56k -3.55 8 — — —
115.2k 111.1k -3.55 8 115.2k 0.00 7 — — — — — —

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12.3.1 AUTO-BAUD DETECT and SPBRG registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
The EUSART module supports automatic detection
average bit time when clocked at full speed.
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the Note 1: If the WUE bit is set with the ABDEN bit,
BRG is reversed. Rather than the BRG clocking the auto-baud detection will occur on the byte
incoming RX signal, the RX signal is timing the BRG. following the Break character (see
The Baud Rate Generator is used to time the period of Section 12.3.2 “Auto-Wake-up on
a received 55h (ASCII “U”) which is the Sync character Break”).
for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the
that it has five rising edges including the Stop bit edge. incoming character baud rate is within the
Setting the ABDEN bit of the BAUDCTL register starts range of the selected BRG clock source.
the auto-baud calibration sequence (Figure 12-6). Some combinations of oscillator frequency
While the ABD sequence takes place, the EUSART and EUSART baud rates are not possible
state machine is held in Idle. On the first rising edge of due to bit error rates. Overall system timing
the receive line, after the Start bit, the SPBRG begins and communication baud rates must be
counting up using the BRG counter clock as shown in taken into consideration when using the
Table 12-6. The fifth rising edge will occur on the RX Auto-Baud Detect feature.
pin at the end of the eighth bit period. At that time, an 3: After completion of the auto-baud
accumulated value totaling the proper BRG period is sequence, the calculated auto-baud
left in SPBRGH, SPBRG register pair, the ABDEN bit is value will be the baud-rate plus 1.
automatically cleared and the RCIF interrupt flag is set.
The value in the RCREG needs to be read to clear the TABLE 12-6: BRG COUNTER CLOCK RATES
RCIF interrupt. RCREG content should be discarded.
When calibrating for modes that do not use the BRG Base BRG ABD
BRG16 BRGH
SPBRGH register the user can verify that the SPBRG Clock Clock
register did not overflow by checking for 00h in the 0 0 FOSC/64 FOSC/512
SPBRGH register.
0 1 FOSC/16 FOSC/128
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 12-6. During ABD, 1 0 FOSC/16 FOSC/128
both the SPBRGH and SPBRG registers are used as a 1 1 FOSC/4 FOSC/32
16-bit counter, independent of the BRG16 bit setting.
Note: During the ABD sequence, SPBRG and
While calibrating the baud rate period, the SPBRGH
SPBRGH registers are both used as a 16-bit
counter, independent of BRG16 setting.

FIGURE 12-6: AUTOMATIC BAUD RATE CALIBRATION

BRG Value XXXXh 0000h 001Ch

Edge #1 Edge #2 Edge #3 Edge #4 Edge #5

RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit

BRG Clock

Set by User Auto Cleared

ABDEN bit

RCIDL

RCIF bit
(Interrupt)

Read
RCREG

SPBRG XXh 1Ch

SPBRGH XXh 00h

Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode

© 2007 Microchip Technology Inc. Preliminary DS41291D-page 165

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12.3.2 AUTO-WAKE-UP ON BREAK 12.3.2.1 Special Considerations
During Sleep mode, all clocks to the EUSART are Break Character
suspended. Because of this, the Baud Rate Generator To avoid character errors or character fragments during
is inactive and a proper character reception cannot be a wake-up event, the wake-up character must be all
performed. The Auto-Wake-up feature allows the zeros.
controller to wake-up due to activity on the RX/DT line.
This feature is available only in Asynchronous mode. When the wake-up is enabled the function works
independent of the low time on the data stream. If the
The Auto-Wake-up feature is enabled by setting the WUE bit is set and a valid non-zero character is
WUE bit of the BAUDCTL register. Once set, the normal received, the low time from the Start bit to the first rising
receive sequence on RX/DT is disabled and the edge will be interpreted as the wake-up event. The
EUSART remains in an Idle state, monitoring for a wake- remaining bits in the character will be received as a
up event independent of the CPU mode. A wake-up fragmented character and subsequent characters can
event consists of a high-to-low transition on the RX/DT result in framing or overrun errors.
line. (This coincides with the start of a Sync Break or a
wake-up signal character for the LIN protocol.) Therefore, the initial character in the transmission must
be all ‘0’s. This must be 10 or more bit times, 13-bit
The EUSART module generates an RCIF interrupt times recommended for LIN bus, or any number of bit
coincident with the wake-up event. The interrupt is times for standard RS-232 devices.
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 12-7), and asynchronously if Oscillator Startup Time
the device is in Sleep mode (Figure 12-8). The interrupt Oscillator start-up time must be considered, especially
condition is cleared by reading the RCREG register. in applications using oscillators with longer start-up
The WUE bit is automatically cleared by the low-to-high intervals (i.e., LP, XT or HS/PLL mode). The Sync
transition on the RX line at the end of the Break. This Break (or wake-up signal) character must be of
signals to the user that the Break event is over. At this sufficient length, and be followed by a sufficient
point, the EUSART module is in Idle mode waiting to interval, to allow enough time for the selected oscillator
receive the next character. to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.

FIGURE 12-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto Cleared
WUE bit
RX/DT Line

RCIF
Cleared due to User Read of RCREG

Note 1: The EUSART remains in Idle while the WUE bit is set.

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FIGURE 12-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4

OSC1
Bit Set by User Auto Cleared
WUE bit
RX/DT Line Note 1
RCIF
Cleared due to User Read of RCREG
Sleep Command Executed Sleep Ends

Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.

12.3.3 BREAK CHARACTER SEQUENCE 12.3.4 RECEIVING A BREAK CHARACTER

The EUSART module has the capability of sending the The Enhanced EUSART module can receive a Break
special Break character sequences that are required by character in two ways.
the LIN bus standard. A Break character consists of a The first method to detect a Break character uses the
Start bit, followed by 12 ‘0’ bits and a Stop bit. FERR bit of the RCSTA register and the Received data
To send a Break character, set the SENDB and TXEN as indicated by RCREG. The Baud Rate Generator is
bits of the TXSTA register. The Break character trans- assumed to have been initialized to the expected baud
mission is then initiated by a write to the TXREG. The rate.
value of data written to TXREG will be ignored and all A Break character has been received when:
‘0’s will be transmitted.
• RCIF bit is set
The SENDB bit is automatically reset by hardware after
• FERR bit is set
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte • RCREG = 00h
following the Break character (typically, the Sync The second method uses the Auto-Wake-up feature
character in the LIN specification). described in Section 12.3.2 “Auto-Wake-up on
The TRMT bit of the TXSTA register indicates when the Break”. By enabling this feature, the EUSART will
transmit operation is active or idle, just as it does during sample the next two transitions on RX/DT, cause an
normal transmission. See Figure 12-9 for the timing of RCIF interrupt, and receive the next data byte followed
the Break character sequence. by another interrupt.
Note that following a Break character, the user will
12.3.3.1 Break and Sync Transmit Sequence typically want to enable the Auto-Baud Detect feature.
The following sequence will start a message frame For both methods, the user can set the ABDEN bit of
header made up of a Break, followed by an auto-baud the BAUDCTL register before placing the EUSART in
Sync byte. This sequence is typical of a LIN bus Sleep mode.
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.

© 2007 Microchip Technology Inc. Preliminary DS41291D-page 167

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FIGURE 12-9: SEND BREAK CHARACTER SEQUENCE

Write to TXREG
Dummy Write

BRG Output
(Shift Clock)

TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit

Break
TXIF bit
(Transmit
interrupt Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB Sampled Here Auto Cleared
SENDB
(send Break
control bit)

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12.4 EUSART Synchronous Mode the clock Idle state as high. When the SCKP bit is set,
the data changes on the falling edge of each clock.
Synchronous serial communications are typically used Clearing the SCKP bit sets the Idle state as low. When
in systems with a single master and one or more the SCKP bit is cleared, the data changes on the rising
slaves. The master device contains the necessary cir- edge of each clock.
cuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take 12.4.1.3 Synchronous Master Transmission
advantage of the master clock by eliminating the
Data is transferred out of the device on the RX/DT pin.
internal clock generation circuitry.
The RX/DT and TX/CK pin output drivers are automat-
There are two signal lines in Synchronous mode: a bidi- ically enabled when the EUSART is configured for
rectional data line and a clock line. Slaves use the synchronous master transmit operation.
external clock supplied by the master to shift the serial
A transmission is initiated by writing a character to the
data into and out of their respective receive and trans-
TXREG register. If the TSR still contains all or part of a
mit shift registers. Since the data line is bidirectional,
previous character the new character data is held in the
synchronous operation is half-duplex only. Half-duplex
TXREG until the last bit of the previous character has
refers to the fact that master and slave devices can
been transmitted. If this is the first character, or the pre-
receive and transmit data, but not both simultaneously.
vious character has been completely flushed from the
The EUSART can operate as either a master or slave
TSR, the data in the TXREG is immediately transferred
device.
to the TSR. The transmission of the character
Start and Stop bits are not used in synchronous commences immediately following the transfer of the
transmissions. data to the TSR from the TXREG.
Each data bit changes on the leading edge of the
12.4.1 SYNCHRONOUS MASTER MODE
master clock and remains valid until the subsequent
The following bits are used to configure the EUSART leading clock edge.
for Synchronous Master operation:
Note: The TSR register is not mapped in data
• SYNC = 1 memory, so it is not available to the user.
• CSRC = 1
• SREN = 0 (for transmit); SREN = 1 (for receive) 12.4.1.4 Synchronous Master Transmission
• CREN = 0 (for transmit); CREN = 1 (for receive) Set-up:
• SPEN = 1 1. Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
Setting the SYNC bit of the TXSTA register configures
desired baud rate (see Section 12.3 “EUSART
the device for synchronous operation. Setting the CSRC
Baud Rate Generator (BRG)”).
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCSTA 2. Enable the synchronous master serial port by
register ensures that the device is in the Transmit mode, setting bits SYNC, SPEN and CSRC.
otherwise the device will be configured to receive. Setting 3. Disable Receive mode by clearing bits SREN
the SPEN bit of the RCSTA register enables the and CREN.
EUSART. If the RX/DT or TX/CK pins are shared with an 4. Enable Transmit mode by setting the TXEN bit.
analog peripheral the analog I/O functions must be 5. If 9-bit transmission is desired, set the TX9 bit.
disabled by clearing the corresponding ANSEL bits.
6. If interrupts are desired, set the TXIE, GIE and
12.4.1.1 Master Clock PEIE interrupt enable bits.
7. If 9-bit transmission is selected, the ninth bit
Synchronous data transfers use a separate clock line,
should be loaded in the TX9D bit.
which is synchronous with the data. A device config-
ured as a master transmits the clock on the TX/CK line. 8. Start transmission by loading data to the TXREG
The TX/CK pin is automatically configured as an output register.
when the EUSART is configured for synchronous
transmit operation. Serial data bits change on the lead-
ing edge to ensure they are valid at the trailing edge of
each clock. One clock cycle is generated for each data
bit. Only as many clock cycles are generated as there
are data bits.

12.4.1.2 Clock Polarity

A clock polarity option is provided for Microwire
compatability. Clock polarity is selected with the SCKP
bit of the BAUDCTL register. Setting the SCKP bit sets

© 2007 Microchip Technology Inc. Preliminary DS41291D-page 169

PIC16F822/883/884/886/887
FIGURE 12-10: SYNCHRONOUS TRANSMISSION

RX/DT
pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
TX/CK pin
(SCKP = 0)

TX/CK pin
(SCKP = 1)
Write to
TXREG Reg Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)

TRMT bit

‘1’ ‘1’
TXEN bit

Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.

FIGURE 12-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7

TX/CK pin

Write to
TXREG reg

TXIF bit

TRMT bit

TXEN bit

TABLE 12-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Transmission.

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 PIC16F822/883/884/886/887
12.4.1.5 Synchronous Master Reception 12.4.1.8 Synchronous Master Reception Set-
Data is received at the RX/DT pin. The RX/DT and TX/ up:
CK pin output drivers are automatically disabled when 1. Initialize the SPBRGH, SPBRG register pair for
the EUSART is configured for synchronous master the appropriate baud rate. Set or clear the
receive operation. BRGH and BRG16 bits, as required, to achieve
In Synchronous mode, reception is enabled by setting the desired baud rate.
either the Single Receive Enable bit (SREN of the 2. Enable the synchronous master serial port by
RCSTA register) or the Continuous Receive Enable bit setting bits SYNC, SPEN and CSRC.
(CREN of the RCSTA register). 3. Ensure bits CREN and SREN are clear.
When SREN is set and CREN is clear, only as many 4. If using interrupts, set the GIE and PEIE bits of
clock cycles are generated as there are data bits in a the INTCON register and set RCIE.
single character. The SREN bit is automatically cleared 5. If 9-bit reception is desired, set bit RX9.
at the completion of one character. When CREN is set, 6. Start reception by setting the SREN bit or for
clocks are continuously generated until CREN is continuous reception, set the CREN bit.
cleared. If CREN is cleared in the middle of a character
7. Interrupt flag bit RCIF will be set when reception
the CK clock stops immediately and the partial charac-
of a character is complete. An interrupt will be
ter is discarded. If SREN and CREN are both set, then
generated if the enable bit RCIE was set.
SREN is cleared at the completion of the first character
and CREN takes precedence. 8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
To initiate reception, set either SREN or CREN. Data is during reception.
sampled at the RX/DT pin on the trailing edge of the
9. Read the 8-bit received data by reading the
TX/CK clock pin and is shifted into the Receive Shift
RCREG register.
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the char- 10. If an overrun error occurs, clear the error by
acter is automatically transferred to the two character either clearing the CREN bit of the RCSTA
receive FIFO. The Least Significant eight bits of the top register or by clearing the SPEN bit which resets
character in the receive FIFO are available in RCREG. the EUSART.
The RCIF bit remains set as long as there are un-read
characters in the receive FIFO.

12.4.1.6 Receive Overrun Error

The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.

12.4.1.7 Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.

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FIGURE 12-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

TX/CK pin
(SCKP = 0)

TX/CK pin
(SCKP = 1)

Write to
bit SREN

SREN bit

CREN bit ‘0’ ‘0’

RCIF bit
(Interrupt)
Read
RXREG

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

TABLE 12-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.

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12.4.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
The following bits are used to configure the EUSART
for Synchronous slave operation: 1. The first character will immediately transfer to
the TSR register and transmit.
• SYNC = 1
2. The second word will remain in TXREG register.
• CSRC = 0
3. The TXIF bit will not be set.
• SREN = 0 (for transmit); SREN = 1 (for receive)
4. After the first character has been shifted out of
• CREN = 0 (for transmit); CREN = 1 (for receive)
TSR, the TXREG register will transfer the second
• SPEN = 1 character to the TSR and the TXIF bit will now be
Setting the SYNC bit of the TXSTA register configures the set.
device for synchronous operation. Clearing the CSRC bit 5. If the PEIE and TXIE bits are set, the interrupt
of the TXSTA register configures the device as a slave. will wake the device from Sleep and execute the
Clearing the SREN and CREN bits of the RCSTA register next instruction. If the GIE bit is also set, the
ensures that the device is in the Transmit mode, program will call the interrupt service routine.
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the 12.4.2.2 Synchronous Slave Transmission
EUSART. If the RX/DT or TX/CK pins are shared with an Set-up:
analog peripheral the analog I/O functions must be
1. Set the SYNC and SPEN bits and clear the
disabled by clearing the corresponding ANSEL bits.
CSRC bit.
12.4.2.1 EUSART Synchronous Slave 2. Clear the CREN and SREN bits.
Transmit 3. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
The operation of the Synchronous Master and Slave
TXIE bit.
modes are identical (see Section 12.4.1.3
“Synchronous Master Transmission”), except in the 4. If 9-bit transmission is desired, set the TX9 bit.
case of the Sleep mode. 5. Enable transmission by setting the TXEN bit.
6. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
7. Start transmission by writing the Least
Significant 8 bits to the TXREG register.

TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.

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12.4.2.3 EUSART Synchronous Slave 12.4.2.4 Synchronous Slave Reception Set-
Reception up:
The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the
modes is identical (Section 12.4.1.5 “Synchronous CSRC bit.
Master Reception”), with the following exceptions: 2. If using interrupts, ensure that the GIE and PEIE
• Sleep bits of the INTCON register are set and set the
• CREN bit is always set, therefore the receiver is RCIE bit.
never idle 3. If 9-bit reception is desired, set the RX9 bit.
• SREN bit, which is a “don’t care” in Slave mode 4. Set the CREN bit to enable reception.
A character may be received while in Sleep mode by 5. The RCIF bit will be set when reception is
setting the CREN bit prior to entering Sleep. Once the complete. An interrupt will be generated if the
word is received, the RSR register will transfer the data RCIE bit was set.
to the RCREG register. If the RCIE enable bit is set, the 6. If 9-bit mode is enabled, retrieve the Most
interrupt generated will wake the device from Sleep Significant bit from the RX9D bit of the RCSTA
and execute the next instruction. If the GIE bit is also register.
set, the program will branch to the interrupt vector. 7. Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
8. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.

TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.

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 PIC16F882/883/884/886/887
13.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
13.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated CircuitTM (I2CTM)
- Full Master mode
- Slave mode (with general address call).
The I2C interface supports the following modes in
hardware:
• Master mode
• Multi-Master mode
• Slave mode.

13.2 Control Registers

The MSSP module has three associated registers.
These include a STATUS register and two control
registers.
Register 13-1 shows the MSSP STATUS register
(SSPSTAT), Register 13-2 shows the MSSP Control
Register 1 (SSPCON), and Register 13-3 shows the
MSSP Control Register 2 (SSPCON2).

© 2007 Microchip Technology Inc. Preliminary DS41291D-page 175

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REGISTER 13-1: SSPSTAT: SSP STATUS REGISTER

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SMP: Sample bit

SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2 C Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
bit 6 CKE: SPI Clock Edge Select bit
CKP = 0:
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1:
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3 S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2 R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to
the next Start bit, Stop bit, or not ACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in Idle mode.
bit 1 UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode only):
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty

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REGISTER 13-2: SSPCON: SSP CONTROL REGISTER 1

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WCOL: Write Collision Detect bit

Master mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started
0 = No collision
Slave mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR
is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting
data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is
initiated by writing to the SSPBUF register (must be cleared in software).
0 = No overflow
In I2 C mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit
mode (must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2 C Slave mode:
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2 C Master mode:
Unused in this mode
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))
1001 = Load Mask function
1010 = Reserved
1011 = I2C firmware controlled Master mode (Slave idle)
1100 = Reserved
1101 = Reserved
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

© 2007 Microchip Technology Inc. Preliminary DS41291D-page 177

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REGISTER 13-3: SSPCON2: SSP CONTROL REGISTER 2

R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C Master mode only)
In Master Transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (in I2C Master mode only)
In Master Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)
SCK Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).

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 PIC16F882/883/884/886/887
13.3 SPI Mode FIGURE 13-1: MSSP BLOCK DIAGRAM
(SPI MODE)
The SPI mode allows 8 bits of data to be synchronously
transmitted and received, simultaneously. All four modes Internal
Data Bus
of SPI are supported. To accomplish communication,
typically three pins are used: Read Write

• Serial Data Out (SDO) – RC5/SDO

SSPBUF Reg
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in any
Slave mode of operation: SSPSR Reg
• Slave Select (SS) – RA5/SS/AN4 SDI bit 0 Shift
Clock

13.3.1 OPERATION SDO

When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits SSPCON<5:0> and SSPSTAT<7:6>. SS Control
Enable
These control bits allow the following to be specified:
SS Edge
• Master mode (SCK is the clock output)
Select
• Slave mode (SCK is the clock input)
• Clock polarity (Idle state of SCK) 2
• Data input sample phase (middle or end of data Clock Select
output time)
SSPM<3:0>
• Clock edge (output data on rising/falling edge of SMP:CKE 4
TMR2 Output
SCK) 2 ( 2 )
• Clock rate (Master mode only) Edge
Select Prescaler TOSC
• Slave Select mode (Slave mode only)
SCK 4, 16, 64
Figure 13-1 shows the block diagram of the MSSP
module, when in SPI mode. Data to TX/RX in SSPSR
TRIS bit

Note: I/O pins have diode protection to VDD and VSS.

The MSSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the buffer full-detect bit BF of the SSP-
STAT register and the interrupt flag bit SSPIF of the
PIR1 register are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit WCOL of the SSPCON register
will be set. User software must clear the WCOL bit so
that it can be determined if the following write(s) to the
SSPBUF register completed successfully.

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When the application software is expecting to receive 13.3.2 ENABLING SPI I/O
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The To enable the serial port, SSP Enable bit SSPEN of the
buffer full bit BF of the SSPSTAT register indicates SSPCON register must be set. To reset or reconfigure
when SSPBUF has been loaded with the received data SPI mode, clear the SSPEN bit, re-initialize the
(transmission is complete). When the SSPBUF is read, SSPCON registers, and then set the SSPEN bit. This
the BF bit is cleared. This data may be irrelevant if the configures the SDI, SDO, SCK and SS pins as serial
SPI is only a transmitter. Generally, the MSSP Interrupt port pins. For the pins to behave as the serial port
is used to determine when the transmission/reception function, some must have their data direction bits (in
has completed. The SSPBUF must be read and/or the TRIS register) appropriately programmed. That is:
written. If the interrupt method is not going to be used, • SDI is automatically controlled by the SPI module
then software polling can be done to ensure that a write • SDO must have TRISC<5> bit cleared
collision does not occur. Example 13-1 shows the • SCK (Master mode) must have TRISC<3> bit
loading of the SSPBUF (SSPSR) for data transmission. cleared
The SSPSR is not directly readable or writable, and • SCK (Slave mode) must have TRISC<3> bit set
can only be accessed by addressing the SSPBUF • SS must have TRISA<5> bit set
register. Additionally, the MSSP STATUS register
(SSPSTAT register) indicates the various status Any serial port function that is not desired may be
conditions. overridden by programming the corresponding data
direction (TRIS) register to the opposite value.

EXAMPLE 13-1: LOADING THE SSPBUF (SSPSR) REGISTER

LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?
GOTO LOOP ;No
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit

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13.3.3 MASTER MODE The clock polarity is selected by appropriately program-
ming the CKP bit of the SSPCON register. This, then,
The master can initiate the data transfer at any time would give waveforms for SPI communication as
because it controls the SCK. The master determines shown in Figure 13-2, Figure 13-4 and Figure 13-5,
when the slave is to broadcast data by the software where the MSb is transmitted first. In Master mode, the
protocol. SPI clock rate (bit rate) is user programmable to be one
In Master mode, the data is transmitted/received as of the following:
soon as the SSPBUF register is written to. If the SPI is • FOSC/4 (or TCY)
only going to receive, the SDO output could be dis-
• FOSC/16 (or 4 • TCY)
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin • FOSC/64 (or 16 • TCY)
at the programmed clock rate. As each byte is • Timer2 output/2
received, it will be loaded into the SSPBUF register as This allows a maximum data rate (at 40 MHz) of
a normal received byte (interrupts and Status bits 10.00 Mbps.
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode. Figure 13-2 shows the waveforms for Master mode.
When the CKE bit of the SSPSTAT register is set, the
SDO data is valid before there is a clock edge on SCK.
The change of the input sample is shown based on the
state of the SMP bit of the SSPSTAT register. The time
when the SSPBUF is loaded with the received data is
shown.

FIGURE 13-2: SPI MODE WAVEFORM (MASTER MODE)

Write to
SSPBUF

SCK
(CKP = 0
CKE = 0)

SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)

SCK
(CKP = 1
CKE = 1)

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 1)
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SDI
(SMP = 1) bit 0
bit7

Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
SSPSR to after Q2↓
SSPBUF

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13.3.4 SLAVE MODE the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte, and becomes a floating
In Slave mode, the data is transmitted and received as output. External pull-up/pull-down resistors may be
the external clock pulses appear on SCK. When the desirable, depending on the application.
last bit is latched, the SSPIF interrupt flag bit of the
PIR1 register is set. Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
While in Slave mode, the external clock is supplied by
0100), the SPI module will reset if the SS
the external clock source on the SCK pin. This external
pin is set to VDD.
clock must meet the minimum high and low times, as
specified in the electrical specifications. 2: If the SPI is used in Slave mode with CKE
set (SSPSTAT register), then the SS pin
While in Sleep mode, the slave can transmit/receive
control must be enabled.
data. When a byte is received, the device will wake-up
from Sleep. When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
13.3.5 SLAVE SELECT a high level, or clearing the SSPEN bit.
SYNCHRONIZATION To emulate two-wire communication, the SDO pin can
The SS pin allows a Synchronous Slave mode. The be connected to the SDI pin. When the SPI needs to
SPI must be in Slave mode with SS pin control operate as a receiver, the SDO pin can be configured
enabled (SSPCON<3:0> = 04h). The pin must not as an input. This disables transmissions from the SDO.
be driven low for the SS pin to function as an input. The SDI can always be left as an input (SDI function),
The Data Latch must be high. When the SS pin is since it cannot create a bus conflict.
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,

FIGURE 13-3: SLAVE SYNCHRONIZATION WAVEFORM

SS

SCK
(CKP = 0
CKE = 0)

SCK
(CKP = 1
CKE = 0)

Write to
SSPBUF

SDO bit 7 bit 6 bit 7 bit 0

SDI bit 0
(SMP = 0)
bit 7 bit 7
Input
Sample
(SMP = 0)

SSPIF
Next Q4 Cycle
SSPSR to after Q2↓
SSPBUF

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FIGURE 13-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS
Optional

SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)

Write to
SSPBUF

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)

SSPIF
Next Q4 Cycle
SSPSR to after Q2↓
SSPBUF

FIGURE 13-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS
Required

SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)

Write to
SSPBUF

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SDI
(SMP = 0)
bit 7 bit 0

Input
Sample
(SMP = 0)

SSPIF

Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF

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13.3.6 SLEEP OPERATION 13.3.8 BUS MODE COMPATIBILITY
In Master mode, all module clocks are halted, and the Table 13-1 shows the compatibility between the
transmission/reception will remain in that state until the standard SPI modes and the states of the CKP and
device wakes from Sleep. After the device returns to CKE control bits.
normal mode, the module will continue to
transmit/receive data. TABLE 13-1: SPI BUS MODES
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the Standard SPI Mode Control Bits State
device to be placed in Sleep mode and data to be Terminology CKP CKE
shifted into the SPI transmit/receive shift register.
0, 0 0 1
When all eight bits have been received, the MSSP
interrupt flag bit will be set and, if enabled, will wake the 0, 1 0 0
device from Sleep. 1, 0 1 1
1, 1 1 0
13.3.7 EFFECTS OF A RESET
There is also a SMP bit that controls when the data will
A Reset disables the MSSP module and terminates the be sampled.
current transfer.

TABLE 13-2: REGISTERS ASSOCIATED WITH SPI OPERATION

Value on Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS

INTCON GIE/GIEH PEIE/GIEL T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 0000 0000

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and
read ‘0’.

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13.4 MSSP I2C Operation The SSPCON register allows control of the I 2C
operation. The SSPM<3:0> mode selection bits
The MSSP module in I 2C mode, fully implements all (SSPCON register) allow one of the following I 2C modes
master and slave functions (including general call to be selected:
support) and provides interrupts on Start and Stop bits in
hardware, to determine a free bus (Multi-Master mode). • I2C Master mode, clock = OSC/4 (SSPADD +1)
The MSSP module implements the standard mode • I 2C Slave mode (7-bit address)
specifications, as well as 7-bit and 10-bit addressing. • I 2C Slave mode (10-bit address)
Two pins are used for data transfer. These are the • I 2C Slave mode (7-bit address), with Start and
RC3/SCK/SCL pin, which is the clock (SCL), and the Stop bit interrupts enabled
RC4/SDI/SDA pin, which is the data (SDA). The user • I 2C Slave mode (10-bit address), with Start and
must configure these pins as inputs or outputs through Stop bit interrupts enabled
the TRISC<4:3> bits. • I 2C firmware controlled master operation, slave is
The MSSP module functions are enabled by setting idle
MSSP Enable bit SSPEN of the SSPCON register. Selection of any I 2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain,
FIGURE 13-6: MSSP BLOCK DIAGRAM provided these pins are programmed to be inputs by
(I2C MODE) setting the appropriate TRISC bits.

Internal
13.4.1 SLAVE MODE
Data Bus
In Slave mode, the SCL and SDA pins must be
Read Write configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
RC3/SCK/SCL
SSPBUF Reg when required (slave-transmitter).
When an address is matched, or the data transfer after
Shift
Clock an address match is received, the hardware
automatically will generate the Acknowledge (ACK)
SSPSR Reg
pulse and load the SSPBUF register with the received
RC4/ MSb LSb value currently in the SSPSR register.
SDI/
SDA If either or both of the following conditions are true, the
Match Detect Addr Match MSSP module will not give this ACK pulse:
a) The buffer full bit BF (SSPCON register) was set
SSPMSK Reg
before the transfer was received.
b) The overflow bit SSPOV (SSPCON register)
was set before the transfer was received.
SSPADD Reg
In this event, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF of the PIR1 register is
Start and Set, Reset
S, P bits set. The BF bit is cleared by reading the SSPBUF
Stop bit Detect
(SSPSTAT Reg) register, while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
Note: I/O pins have diode protection to VDD and VSS.
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
The MSSP module has these six registers for I2C
and parameter #101.
operation:
• MSSP Control Register 1 (SSPCON)
• MSSP Control Register 2 (SSPCON2)
• MSSP STATUS register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address register (SSPADD)
• MSSP Mask register (SSPMSK)

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13.4.1.1 Addressing When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
Once the MSSP module has been enabled, it waits for
condition is defined as either bit BF (SSPSTAT register)
a Start condition to occur. Following the Start condition,
is set, or bit SSPOV (SSPCON register) is set.
the eight bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the An MSSP interrupt is generated for each data transfer
clock (SCL) line. The value of register SSPSR<7:1> is byte. Flag bit SSPIF of the PIR1 register must be
compared to the value of the SSPADD register. The cleared in software. The SSPSTAT register is used to
address is compared on the falling edge of the eighth determine the status of the byte.
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur: 13.4.1.3 Transmission
a) The SSPSR register value is loaded into the When the R/W bit of the incoming address byte is set
SSPBUF register. and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
b) The buffer full bit BF is set.
loaded into the SSPBUF register. The ACK pulse will
c) An ACK pulse is generated. be sent on the ninth bit and pin RC3/SCK/SCL is held
d) MSSP interrupt flag bit, SSPIF of the PIR1 low. The transmit data must be loaded into the
register, is set on the falling edge of the ninth SSPBUF register, which also loads the SSPSR regis-
SCL pulse (interrupt is generated, if enabled). ter. Then pin RC3/SCK/SCL should be enabled by set-
In 10-bit address mode, two address bytes need to be ting bit CKP (SSPCON register). The master must
received by the slave. The five Most Significant bits monitor the SCL pin prior to asserting another clock
(MSb) of the first address byte specify if this is a 10-bit pulse. The slave devices may be holding off the master
address. The R/W bit (SSPSTAT register) must specify by stretching the clock. The eight data bits are shifted
a write so the slave device will receive the second out on the falling edge of the SCL input. This ensures
address byte. For a 10-bit address, the first byte would that the SDA signal is valid during the SCL high time
equal ‘1111 0 A9 A8 0’, where A9 and A8 are the (Figure 13-8).
two MSb’s of the address. An MSSP interrupt is generated for each data transfer
The sequence of events for 10-bit addressing is as byte. The SSPIF bit must be cleared in software and
follows, with steps 7-9 for slave-transmitter: the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
1. Receive first (high) byte of address (bit SSPIF of
the ninth clock pulse.
the PIR1 register and bits BF and UA of the
SSPSTAT register are set). As a slave-transmitter, the ACK pulse from the
2. Update the SSPADD register with second (low) master-receiver is latched on the rising edge of the
byte of address (clears bit UA and releases the ninth SCL input pulse. If the SDA line is high (not ACK),
SCL line). then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset and the
3. Read the SSPBUF register (clears bit BF) and
slave monitors for another occurrence of the Start bit. If
clear flag bit SSPIF.
the SDA line was low (ACK), the transmit data must be
4. Receive second (low) byte of address (bits loaded into the SSPBUF register, which also loads the
SSPIF, BF, and UA are set). SSPSR register. Pin RC3/SCK/SCL should be enabled
5. Update the SSPADD register with the first (high) by setting bit CKP.
byte of address. If match releases SCL line, this
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.

13.4.1.2 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.

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FIGURE 13-7: I 2C™ SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

Receiving Address R/W = 0 Receiving Data ACK Receiving Data Not ACK
ACK
SDA A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P

SSPIF Bus Master

Terminates
Transfer
BF
Cleared in software
SSPBUF register is read
SSPOV
Bit SSPOV is set because the SSPBUF register is still full
ACK is not sent

FIGURE 13-8: I 2C™ SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
R/W = 0
Receiving Address R/W = 1 Transmitting Data Not ACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Data in SCL held low
Sampled while CPU
responds to SSPIF
SSPIF

BF
Cleared in software From SSP Interrupt
SSPBUF is written in software Service Routine

CKP

Set bit after writing to SSPBUF

(the SSPBUF must be written to
before the CKP bit can be set)

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13.4.2 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is
SUPPORT transferred to the SSPBUF, the BF bit is set (eighth bit),
and on the falling edge of the ninth bit (ACK bit), the
The addressing procedure for the I2C bus is such that, SSPIF interrupt flag bit is set.
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the When the interrupt is serviced, the source for the inter-
master. The exception is the general call address, rupt can be checked by reading the contents of the
which can address all devices. When this address is SSPBUF. The value can be used to determine if the
used, all devices should, in theory, respond with an address was device specific or a general call address.
Acknowledge. In 10-bit mode, the SSPADD is required to be updated
The general call address is one of eight addresses for the second half of the address to match, and the UA
reserved for specific purposes by the I2C protocol. It bit is set (SSPSTAT register). If the general call address
consists of all 0’s with R/W = 0. is sampled when the GCEN bit is set, and while the
slave is configured in 10-bit address mode, then the
The general call address is recognized (enabled) when second half of the address is not necessary. The UA bit
the General Call Enable (GCEN) bit is set (SSPCON2 will not be set, and the slave will begin receiving data
register). Following a Start bit detect, eight bits are after the Acknowledge (Figure 13-9).
shifted into the SSPSR and the address is compared
against the SSPADD. It is also compared to the general
call address and fixed in hardware.

FIGURE 13-9: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS)

Address is compared to General Call Address

after ACK, set interrupt

Receiving Data ACK

R/W = 0
General Call Address ACK D7
SDA D6 D5 D4 D3 D2 D1 D0

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S

SSPIF

BF

Cleared in software
SSPBUF is read
SSPOV ‘0’

GCEN ‘1’

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13.4.3 MASTER MODE 13.4.4 I2C™ MASTER MODE SUPPORT
Master mode of operation is supported by interrupt Master mode is enabled by setting and clearing the
generation on the detection of the Start and Stop appropriate SSPM bits in SSPCON and by setting the
conditions. The Stop (P) and Start (S) bits are cleared SSPEN bit. Once Master mode is enabled, the user
from a Reset, or when the MSSP module is disabled. has the following six options:
Control of the I 2C bus may be taken when the P bit is 1. Assert a Start condition on SDA and SCL.
set, or the bus is idle, with both the S and P bits clear.
2. Assert a Repeated Start condition on SDA and
In Master mode, the SCL and SDA lines are manipu- SCL.
lated by the MSSP hardware. 3. Write to the SSPBUF register initiating
The following events will cause SSP Interrupt Flag bit, transmission of data/address.
SSPIF, to be set (SSP Interrupt if enabled): 4. Generate a Stop condition on SDA and SCL.
• Start condition 5. Configure the I2C port to receive data.
• Stop condition 6. Generate an Acknowledge condition at the end
• Data transfer byte transmitted/received of a received byte of data.
• Acknowledge transmit
• Repeated Start condition Note: The MSSP module, when configured in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
imitate transmission, before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.

FIGURE 13-10: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)

Internal SSPM<3:0>
Data Bus SSPADD<6:0>
Read Write

SSPBUF Baud
Rate
Generator
SDA Shift
Clock Arbitrate/WCOL Detect

SDA In Clock
SSPSR
(hold off clock source)

MSb LSb
Receive Enable

Start bit, Stop bit,

Clock Cntl

Acknowledge
Generate
SCL

Start bit Detect

Stop bit Detect
SCL In Write Collision Detect Set/Reset, S, P, WCOL (SSPSTAT)
Clock Arbitration Set SSPIF, BCLIF
Bus Collision State Counter for Reset ACKSTAT, PEN (SSPCON2)
End of XMIT/RCV

Note: I/O pins have diode protection to VDD and VSS.

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13.4.4.1 I2C™ Master Mode Operation A typical transmit sequence would go as follows:
The master device generates all of the serial clock a) The user generates a Start condition by setting
pulses and the Start and Stop conditions. A transfer is the Start Enable (SEN) bit (SSPCON2 register).
ended with a Stop condition or with a Repeated Start b) SSPIF is set. The MSSP module will wait the
condition. Since the Repeated Start condition is also required start time before any other operation
the beginning of the next serial transfer, the I2C bus will takes place.
not be released. c) The user loads the SSPBUF with the address to
In Master Transmitter mode, serial data is output transmit.
through SDA, while SCL outputs the serial clock. The d) Address is shifted out the SDA pin until all eight
first byte transmitted contains the slave address of the bits are transmitted.
receiving device (7 bits) and the Read/Write (R/W) bit. e) The MSSP module shifts in the ACK bit from the
In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the
transmitted eight bits at a time. After each byte is trans- ACKSTAT bit (SSPCON2 register).
mitted, an Acknowledge bit is received. Start and Stop
f) The MSSP module generates an interrupt at the
conditions are output to indicate the beginning and the
end of the ninth clock cycle by setting the SSPIF
end of a serial transfer.
bit.
In Master Receive mode, the first byte transmitted con- g) The user loads the SSPBUF with eight bits of
tains the slave address of the transmitting device data.
(7 bits) and the R/W bit. In this case, the R/W bit will be
h) Data is shifted out the SDA pin until all eight bits
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
are transmitted.
address followed by a ‘1’ to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial i) The MSSP module shifts in the ACK bit from the
clock. Serial data is received eight bits at a time. After slave device and writes its value into the
each byte is received, an Acknowledge bit is transmit- ACKSTAT bit (SSPCON2 register).
ted. Start and Stop conditions indicate the beginning j) The MSSP module generates an interrupt at the
and end of transmission. end of the ninth clock cycle by setting the SSPIF
bit.
The Baud Rate Generator used for the SPI mode oper-
ation is now used to set the SCL clock frequency for k) The user generates a Stop condition by setting
either 100 kHz, 400 kHz, or 1 MHz I2C operation. The the Stop Enable bit PEN (SSPCON2 register).
Baud Rate Generator reload value is contained in the l) Interrupt is generated once the Stop condition is
lower 7 bits of the SSPADD register. The Baud Rate complete.
Generator will automatically begin counting on a write
to the SSPBUF. Once the given operation is complete
(i.e., transmission of the last data bit is followed by
ACK), the internal clock will automatically stop counting
and the SCL pin will remain in its last state.

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13.4.5 BAUD RATE GENERATOR
2
In I C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 13-11). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically. If clock arbitration is taking
place, for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 13-12).

FIGURE 13-11: BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM<3:0> SSPADD<6:0>

SSPM<3:0> Reload Reload

SCL Control

CLKOUT BRG Down Counter FOSC/4

FIGURE 13-12: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA DX DX-1

SCL de-asserted but slave holds SCL allowed to transition high

SCL low (clock arbitration)
SCL

BRG decrements on
Q2 and Q4 cycles

BRG
03h 02h 01h 00h (hold off) 03h 02h
Value

SCL is sampled high, reload takes

place and BRG starts its count
BRG
Reload

© 2007 Microchip Technology Inc. Preliminary DS41291D-page 191

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13.4.6 I2C™ MASTER MODE START 13.4.6.1 WCOL Status Flag
CONDITION TIMING If the user writes the SSPBUF when a Start sequence
To initiate a Start condition, the user sets the Start Con- is in progress, the WCOL is set and the contents of the
dition Enable bit SEN of the SSPCON2 register. If the buffer are unchanged (the write doesn’t occur).
SDA and SCL pins are sampled high, the Baud Rate Note: Because queueing of events is not
Generator is reloaded with the contents of allowed, writing to the lower 5 bits of
SSPADD<6:0> and starts its count. If SCL and SDA are SSPCON2 is disabled until the Start condi-
both sampled high when the Baud Rate Generator tion is complete.
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low, while SCL is high, is the
Start condition, and causes the S bit of the SSPSTAT
register to be set. Following this, the Baud Rate Gener-
ator is reloaded with the contents of SSPADD<6:0>
and resumes its count. When the Baud Rate Generator
times out (TBRG), the SEN bit of the SSPCON2 register
will be automatically cleared by hardware, the Baud
Rate Generator is suspended leaving the SDA line held
low and the Start condition is complete.
Note: If, at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs, the
Bus Collision Interrupt Flag, BCLIF, is set,
the Start condition is aborted, and the I2C
module is reset into its Idle state.

FIGURE 13-13: FIRST START BIT TIMING

Set S bit (SSPSTAT)

Write to SEN bit occurs here
SDA = 1,
At completion of Start bit,
SCL = 1
hardware clears SEN bit
and sets SSPIF bit
TBRG TBRG Write to SSPBUF occurs here

1st Bit 2nd Bit

SDA
TBRG

SCL
TBRG
S

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 PIC16F882/883/884/886/887
13.4.7 I2C™ MASTER MODE REPEATED
START CONDITION TIMING Note 1: If RSEN is programmed while any other
A Repeated Start condition occurs when the RSEN bit event is in progress, it will not take effect.
(SSPCON2 register) is programmed high and the I2C 2: A bus collision during the Repeated Start
Logic module is in the Idle state. When the RSEN bit is condition occurs if:
set, the SCL pin is asserted low. When the SCL pin is
• SDA is sampled low when SCL goes
sampled low, the Baud Rate Generator is loaded with
from low-to-high.
the contents of SSPADD<5:0> and begins counting.
The SDA pin is released (brought high) for one Baud • SCL goes low before SDA is
Rate Generator count (TBRG). When the Baud Rate asserted low. This may indicate that
Generator times out, if SDA is sampled high, the SCL another master is attempting to
pin will be de-asserted (brought high). When SCL is transmit a data “1”.
sampled high, the Baud Rate Generator is reloaded Immediately following the SSPIF bit getting set, the
with the contents of SSPADD<6:0> and begins count- user may write the SSPBUF with the 7-bit address in
ing. SDA and SCL must be sampled high for one TBRG. 7-bit mode, or the default first address in 10-bit mode.
This action is then followed by assertion of the SDA pin After the first eight bits are transmitted and an ACK is
(SDA = 0) for one TBRG, while SCL is high. Following received, the user may then transmit an additional eight
this, the RSEN bit (SSPCON2 register) will be automat- bits of address (10-bit mode), or eight bits of data (7-bit
ically cleared and the Baud Rate Generator will not be mode).
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins, 13.4.7.1 WCOL Status Flag
the S bit (SSPSTAT register) will be set. The SSPIF bit If the user writes the SSPBUF when a Repeated Start
will not be set until the Baud Rate Generator has timed sequence is in progress, the WCOL is set and the con-
out. tents of the buffer are unchanged (the write doesn’t
occur).
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.

FIGURE 13-14: REPEAT START CONDITION WAVEFORM

Set S (SSPSTAT<3>)
Write to SSPCON2
SDA = 1,
occurs here, At completion of Start bit,
SDA = 1, SCL = 1
hardware clear RSEN bit
SCL (no change) and set SSPIF

TBRG TBRG TBRG

1st bit
SDA
Falling edge of ninth clock Write to SSPBUF occurs here
End of Xmit
TBRG

SCL TBRG

Sr = Repeated Start

© 2007 Microchip Technology Inc. Preliminary DS41291D-page 193

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13.4.8 I2C™ MASTER MODE 13.4.8.3 ACKSTAT Status Flag
TRANSMISSION In Transmit mode, the ACKSTAT bit (SSPCON2
Transmission of a data byte, a 7-bit address, or the register) is cleared when the slave has sent an
other half of a 10-bit address, is accomplished by sim- Acknowledge (ACK = 0), and is set when the slave
ply writing a value to the SSPBUF register. This action does not Acknowledge (ACK = 1). A slave sends an
will set the Buffer Full bit, BF, and allow the Baud Rate Acknowledge when it has recognized its address
Generator to begin counting and start the next trans- (including a general call), or when the slave has
mission. Each bit of address/data will be shifted out properly received its data.
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification, parameter 13.4.9 I2C™ MASTER MODE RECEPTION
106). SCL is held low for one Baud Rate Generator roll- Master mode reception is enabled by programming the
over count (TBRG). Data should be valid before SCL is Receive Enable bit, RCEN (SSPCON2 register).
released high (see data setup time specification,
parameter 107). When the SCL pin is released high, it Note: The MSSP module must be in an Idle state
is held that way for TBRG. The data on the SDA pin before the RCEN bit is set, or the RCEN bit
must remain stable for that duration and some hold will be disregarded.
time after the next falling edge of SCL. After the eighth The Baud Rate Generator begins counting, and on
bit is shifted out (the falling edge of the eighth clock), each rollover, the state of the SCL pin changes
the BF bit is cleared and the master releases SDA, (high-to-low/low-to-high) and data is shifted into the
allowing the slave device being addressed to respond SSPSR. After the falling edge of the eighth clock, the
with an ACK bit during the ninth bit time, if an address RCEN bit is automatically cleared, the contents of the
match occurs, or if data was received properly. The SSPSR are loaded into the SSPBUF, the BF bit is set,
status of ACK is written into the ACKDT bit on the fall- the SSPIF flag bit is set and the Baud Rate Generator
ing edge of the ninth clock. If the master receives an is suspended from counting, holding SCL low. The
Acknowledge, the Acknowledge Status bit, ACKSTAT, MSSP is now in Idle state, awaiting the next command.
is cleared. If not, the bit is set. After the ninth clock, the When the buffer is read by the CPU, the BF bit is auto-
SSPIF bit is set and the master clock (Baud Rate Gen- matically cleared. The user can then send an Acknowl-
erator) is suspended until the next data byte is loaded edge bit at the end of reception, by setting the
into the SSPBUF, leaving SCL low and SDA Acknowledge Sequence Enable bit ACKEN
unchanged (Figure 13-15). (SSPCON2 register).
After the write to the SSPBUF, each bit of the address
13.4.9.1 BF Status Flag
will be shifted out on the falling edge of SCL, until all
seven address bits and the R/W bit, are completed. On In receive operation, the BF bit is set when an address
the falling edge of the eighth clock, the master will or data byte is loaded into SSPBUF from SSPSR. It is
de-assert the SDA pin, allowing the slave to respond cleared when the SSPBUF register is read.
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDA pin to see if the 13.4.9.2 SSPOV Status Flag
address was recognized by a slave. The status of the In receive operation, the SSPOV bit is set when eight
ACK bit is loaded into the ACKSTAT Status bit bits are received into the SSPSR and the BF bit is
(SSPCON2 register). Following the falling edge of the already set from a previous reception.
ninth clock transmission of the address, the SSPIF is
set, the BF bit is cleared and the Baud Rate Generator 13.4.9.3 WCOL Status Flag
is turned off, until another write to the SSPBUF takes If the user writes the SSPBUF when a receive is
place, holding SCL low and allowing SDA to float. already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
13.4.8.1 BF Status Flag
are unchanged (the write doesn’t occur).
In Transmit mode, the BF bit (SSPSTAT register) is set
when the CPU writes to SSPBUF, and is cleared when
all eight bits are shifted out.

13.4.8.2 WCOL Status Flag

If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur). WCOL
must be cleared in software.

DS41291D-page 194 Preliminary © 2007 Microchip Technology Inc.

 FIGURE 13-15:

Write SSPCON2<0> SEN = 1 ACKSTAT in

Start condition begins SSPCON2 = 1
From slave, clear ACKSTAT bit SSPCON2<6>
SEN = 0

© 2007 Microchip Technology Inc.

Transmitting Data or Second Half
Transmit Address to Slave R/W = 0 of 10-bit Address ACK

SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0

SSPBUF written with 7-bit address and R/W

start transmit
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SCL held low
while CPU
responds to SSPIF
SSPIF
Cleared in software service routine
Cleared in software From SSP interrupt
Cleared in software

Preliminary
BF

SSPBUF written SSPBUF is written in software

SEN

After Start condition, SEN cleared by hardware.

PEN

R/W
I 2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
PIC16F882/883/884/886/887

DS41291D-page 195
 FIGURE 13-16:

DS41291D-page 196
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
Write to SSPCON2<0> (SEN = 1)
Begin Start Condition ACK from Master Set ACKEN start Acknowledge sequence
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPCON2<3>, (RCEN = 1)
PEN bit = 1
Write to SSPBUF occurs here RCEN cleared RCEN = 1 start RCEN cleared
automatically next receive automatically written here
Start XMIT ACK from Slave
Transmit Address to Slave R/W = 1 Receiving Data from Slave Receiving Data from Slave
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

Bus Master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPIF at end
of receive Set SSPIF interrupt
Set SSPIF interrupt at end of Acknow-
at end of receive Set SSPIF interrupt ledge sequence
at end of Acknowledge
SSPIF sequence
Set P bit
SDA = 0, SCL = 1 Cleared in software Cleared in software Cleared in software Cleared in software Cleared in (SSPSTAT<4>)

Preliminary
while CPU software and SSPIF
responds to SSPIF
PIC16F882/883/884/886/887

BF
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF

SSPOV

SSPOV is set because

SSPBUF is still full

ACKEN
I 2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

© 2007 Microchip Technology Inc.

 PIC16F882/883/884/886/887
13.4.10 ACKNOWLEDGE SEQUENCE TIMING 13.4.11 STOP CONDITION TIMING
An Acknowledge sequence is enabled by setting the A Stop bit is asserted on the SDA pin at the end of a
Acknowledge Sequence Enable bit, ACKEN (SSPCON2 receive/transmit by setting the Stop Sequence Enable
register). When this bit is set, the SCL pin is pulled low bit, PEN (SSPCON2 register). At the end of a
and the contents of the Acknowledge Data bit (ACKDT) receive/transmit, the SCL line is held low after the fall-
is presented on the SDA pin. If the user wishes to gener- ing edge of the ninth clock. When the PEN bit is set, the
ate an Acknowledge, then the ACKDT bit should be master will assert the SDA line low. When the SDA line
cleared. If not, the user should set the ACKDT bit before is sampled low, the Baud Rate Generator is reloaded
starting an Acknowledge sequence. The Baud Rate and counts down to 0. When the Baud Rate Generator
Generator then counts for one rollover period (TBRG) and times out, the SCL pin will be brought high, and one
the SCL pin is de-asserted (pulled high). When the SCL TBRG (Baud Rate Generator rollover count) later, the
pin is sampled high (clock arbitration), the Baud Rate SDA pin will be de-asserted. When the SDA pin is sam-
Generator counts for TBRG. The SCL pin is then pulled pled high while SCL is high, the P bit (SSPSTAT regis-
low. Following this, the ACKEN bit is automatically ter) is set. A TBRG later, the PEN bit is cleared and the
cleared, the Baud Rate Generator is turned off and the SSPIF bit is set (Figure 13-18).
MSSP module then goes into Idle mode (Figure 13-17).
13.4.11.1 WCOL Status Flag
13.4.10.1 WCOL Status Flag If the user writes the SSPBUF when a Stop sequence
If the user writes the SSPBUF when an Acknowledge is in progress, then the WCOL bit is set and the
sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t
contents of the buffer are unchanged (the write doesn’t occur).
occur).

FIGURE 13-17: ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here, ACKEN automatically cleared
Write to SSPCON2
ACKEN = 1, ACKDT = 0

TBRG TBRG
SDA D0 ACK

SCL 8 9

SSPIF

Set SSPIF at the end Cleared in Cleared in

of receive software software
Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.

© 2007 Microchip Technology Inc. Preliminary DS41291D-page 197

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FIGURE 13-18: STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPCON2 SCL = 1 for TBRG, followed by SDA = 1 for TBRG
Set PEN after SDA sampled high, P bit (SSPSTAT) is set

Falling edge of PEN bit (SSPCON2) is cleared by

9th clock hardware and the SSPIF bit is set
TBRG
SCL

SDA ACK

P
TBRG TBRG TBRG

SCL brought high after TBRG

SDA asserted low before rising edge of clock
to set up Stop condition

Note: TBRG = one Baud Rate Generator period.

13.4.12 CLOCK ARBITRATION 13.4.13 SLEEP OPERATION

Clock arbitration occurs when the master, during any While in Sleep mode, the I2C module can receive
receive, transmit or Repeated Start/Stop condition, addresses or data, and when an address match or
de-asserts the SCL pin (SCL allowed to float high). complete byte transfer occurs, wake the processor
When the SCL pin is allowed to float high, the Baud from Sleep (if the MSSP interrupt is enabled).
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the 13.4.14 EFFECT OF A RESET
SCL pin is sampled high, the Baud Rate Generator is
A Reset disables the MSSP module and terminates the
reloaded with the contents of SSPADD<6:0> and
current transfer.
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count, in the
event that the clock is held low by an external device
(Figure 13-19).

FIGURE 13-19: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE

BRG overflow,
Release SCL,
If SCL = 1, load BRG with
SSPADD<6:0>, and start count BRG overflow occurs,
to measure high time interval Release SCL, Slave device holds SCL low
SCL = 1, BRG starts counting
clock high interval

SCL

SCL line sampled once every machine cycle (TOSC*4),

Hold off BRG until SCL is sampled high

SDA

TBRG TBRG TBRG

DS41291D-page 198 Preliminary © 2007 Microchip Technology Inc.