Serial Communication Modules in the

PIC16F877
Introduction
The PIC16F877 has two serial communication modules. These are the universal synchronous asynchronous
receiver transmitter (USART) and the master synchronous serial port (MSSP). The USART module is also
known as the Serial Communication Interface (SCI).

The USART Module

The USART module made up of two parts, a transmitter and a receiver. The heart of the transmitter and the
receiver are two shift registers respectively named TSR and RSR. Figure 9.1 shows the block diagram of the
USART.

Figure 9.1 (a) Block diagram for transmitter

Figure 9.1 (b) Block diagram for receiver

TSR and RSR are not accessible by the user. TSR is used to shift data bits out as data is being transmitted out.
RSR is used to shift in data bits as data is being received. Following completion of a reception session,
received data is stored in the receive buffer register RCREG. To initiate transmission of data, data is written
to the transmit data buffer, TXREG.

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Reception of data can raise an interrupt. Likewise, end of a transmission session can raise an interrupt.

Operation of the USART is controlled through control registers RCSTA (mainly for receiver part) and TXSTA
(mainly for the transmit part). Baud rate is generated from the value written in the register SPBRG.

The USART can be configured to make the PIC an asynchronous receiver transmitter, a synchronous master
receiver/transmitter or a synchronous slave receiver/transmitter.

Associated Registers
TXREG (address 19h)
It is the buffer register to which is written to initiate a transmission of data.

RXREG (address 1Ah)

It is the buffer register in which data is stored after being shifted in during a reception session.

RCSTA (address 18h)

SPEN: Serial Port Enable bit

 1 – Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
 0 – Serial port disabled
RX9: 9-bit Receive Enable bit
 1 – Selects 9-bit reception
 0 – Selects 8-bit reception
SREN: Single Receive Enable bit
 Asynchronous mode, don’t care.
 Synchronous mode – Master:
o 1 – Enables single receive
o 0 – Disables single receive
o This bit is cleared after reception is complete.
 Synchronous mode – Slave, don’t care.
CREN: Continuous Receive Enable bit
 Asynchronous mode:
o 1 – Enables continuous receive
o 0 – Disables continuous receive
 Synchronous mode:
o 1 – Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
o 0 – Disables continuous receive
ADDEN: Address Detect Enable bit
 Asynchronous mode 9-bit (RX9 = 1):
o 1 – Enables address detection, enables interrupt and load of the receive buffer when RSR<8>
is set
o 0 – Disables address detection, all bytes are received and ninth bit can be used as parity bit
FERR: Framing Error bit
 1 – Framing error (can be updated by reading RCREG register and receive next valid byte)
 0 – No framing error
OERR: Overrun Error bit

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  1 – Overrun error (can be cleared by clearing bit CREN)
 0 – No overrun error
RX9D: 9th bit of Received Data (can be parity bit but must be calculated by user firmware)

TXSTA (address 98h)

CSRC: Clock Source Select bit

 Asynchronous mode, don’t care.
 Synchronous mode:
o 1 – Master mode (clock generated internally from BRG).
o 0 – Slave mode (clock from external source).
TX9: 9-bit Transmit Enable bit
 1 – Selects 9-bit transmission.
 0 – Selects 8-bit transmission.
TXEN: Transmit Enable bit
 1 – Transmit enabled.
 0 – Transmit disabled.
 Note: SREN/CREN overrides TXEN in Sync mode.
SYNC: USART Mode Select bit
 1 – Synchronous mode.
 0 – Asynchronous mode.
bit 3 is unimplemented and read as ‘0’
BRGH: High Baud Rate Select bit
 Asynchronous mode:
o 1 – High speed.
o 0 – Low speed.
 Synchronous mode, bit is unused.
TRMT: Transmit Shift Register Status bit
 1 – TSR empty
 0 – TSR full
TX9D: 9th bit of Transmit Data, can be Parity bit

SPBRG (address 99h)

The SPBRG register is used to generate the baud rate for the USART in the synchronous master mode and
the asynchronous slave and master modes. The baud rate also depends on the BRGH and SYNC bits in TSXTA.
The formulae for the baud rate under various conditions are:
BRGH = 0 (low speed) BRGH = 1 (high speed)
Asynchronous mode 𝐹𝑂𝑆𝐶 𝐹𝑂𝑆𝐶
𝑏𝑎𝑢𝑑 𝑟𝑎𝑡𝑒 = 𝑏𝑎𝑢𝑑 𝑟𝑎𝑡𝑒 =
(SYNC = 0) 64(𝑆𝑃𝐵𝑅𝐺 + 1) 16(𝑆𝑃𝐵𝑅𝐺 + 1)
Synchronous mode 𝐹𝑂𝑆𝐶
𝑏𝑎𝑢𝑑 𝑟𝑎𝑡𝑒 = N/A
(SYNC = 1) 4(𝑆𝑃𝐵𝑅𝐺 + 1)

Interrupt Control Registers

 PIE1 (address 8Ch) contains the interrupt enable bits, RCIE and TXIE for the USART module.
 PIR1 (address 0Ch) contains the interrupt flag, RCIF and TXIF for the USART module.

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  INTCON (addresses 0Bh, 8Bh, 108Bh and 18Bh) contains the global interrupt enable bits GIE and
PEIE, that also affect the operation of the USART interrupts.

Running the USART Module

1. In TXSTA and RXSTA, set the bits to values required to set up the required mode of operation.
2. If required, select the baud rate by writing an appropriate value to SPBRG.
3. Enable interrupts if required.
4. For transmission of data:
 If 9-bit communication required, write 9th bit to TX9 bit in TXSTA.
 Write the transmit data to TXREG.
 Transmission will follow after writing to TXREG. Check transmission is complete by polling
TXIF. Alternatively, wait for the USART transmit interrupt.
5. For reception of data:
 Poll the buffer RCIF flag and when set, read the value in RCREG.
 If 9th bit is required, read RX9 in RCSTA.
 Alternatively wait for the USART receive interrupt.

The MSSP module

The MSSP module can operate in serial peripheral (SPI) mode (slave or master) or inter-integrated circuit
(I2C) mode (slave or master). In either mode, the PIC can be configured to be the master or the slave.

The MSSP essentially consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF).
Figure 9.2 shows the basic structure of the MSSP.

Figure 9.2

The SSPSR is not accessible by the user and is used to shift data in or out one bit at a time during a serial
transmission session.

For reception, when the SSPSR has received a complete byte, the byte is transferred to the SSPBUF where it
can be accessed by the user. SSPSR and SSPBUF, thus, together create a double-buffered receiver that allows
another byte to be received while the previous one is held in the SSPBUF.

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For transmission, the byte to be transmitted is written to the SSPBUF. Writing to the SSPBUF automatically
writes the same byte to the SSPSR so that transmission may begin if all necessary conditions are satisfied.
Transmission is not double-buffered.

Completion of reception or transmission of byte can raise an interrupt called the SSP interrupt.

Operation of the MSSP is controlled by three control registers namely SSPSTAT, SSPCON1 and SSPCON2. The
lowest 4 bits in SSPCON1 are used to select the mode (SPI or I2C) and the baud rate (when operating as the
master). The roles of the other bits in SSPCON and the bits in SSPSTAT depend on whether SPI or I2C mode is
selected. SSPCON2 is used only in the I2C mode. An address register, SSPADD is available for use in the I2C
mode. SSPADD is used to hold the slave address when the PIC is in slave mode. In the master mode, SSPADD
is used generate the baud rate.

The SPI Mode

The PIC can be configured as a SPI master or SPI slave. The pins used for the data transfer are:
 RC5/SDO – Serial Data Out
 RC4/SDI/SDA – Serial Data In (SDI)
 RC3/SCK/SCL – Serial Clock (SCK). In master mode, the PIC generates a clock on the SCK pin. In slave
mode it receives a clock on the SCK pin.
 RA5/AN4/SS/C2OUT – Slave Select (SS). Used in the slave mode to select the PIC as a slave to
communicate with a master.

Use of Associated Registers – SPI mode

SSPBUF Register (address 94h)
It is the buffer register for received data or data to be transmitted.

The SSPCON1 register (address 14h)

It is used to select the mode and control the operation of the MSSP.

 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

o 0101 – SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
o 0100 – SPI Slave mode, clock = SCK pin. SS pin control enabled.
o 0011 – SPI Master mode, clock = TMR2 output/2
o 0010 – SPI Master mode, clock = FOSC/64
o 0001 – SPI Master mode, clock = FOSC/16
o 0000 – SPI Master mode, clock = FOSC/4
o Note: Bit combinations not specifically listed here are either reserved or implemented in I2C
mode only.
 CKP: Clock Polarity Select bit
o 1 – Idle state for clock is a high level
o 0 – Idle state for clock is a low level
 SSPEN: Synchronous serial port enable bit
o 1 – Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins
o 0 – Disables serial port and configures these pins as I/O port pins
o Note: When enabled, these pins must be properly configured as input or output.

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  SSPOV: Receive overflow indicator bit
o SPI Slave mode:
 1 – A new byte is received while the SSPBUF register is still holding the previous
data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave
mode. The user must read the SSPBUF, even if only transmitting data, to avoid
setting overflow. (Must be cleared in software.)
 0 – No overflow
o Note: In Master mode, the overflow bit is not set, since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
 WCOL: Write collision detect bit (transmit mode only)
o 1 – The SSPBUF register is written while it is still transmitting the previous word. (Must be
cleared in software.)
o 0 – No collision

The SSPSTAT register (address 94h)

The register contains bits that tell the status of the SPI module.

 SMP: Sample bit

o SPI Master mode:
 1 – Input data sampled at end of data output time
 0 – Input data sampled at middle of data output time
o SPI Slave mode: SMP must be cleared when SPI is used in Slave mode.
 CKE: SPI Clock Select bit
o 1 – Transmit occurs on transition from active to Idle clock state
o 0 – Transmit occurs on transition from Idle to active clock state
o Note: Polarity of clock state is set by the CKP bit (SSPCON1<4>).
 D/A, P, S, R/W and UA – used in I2C mode only.
 BF: Buffer Full Status bit (Receive mode only):
o 1 – Receive complete, SSPBUF is full
o 0 – Receive not complete, SSPBUF is empty

TRISA and TRISC

Some of the pins used for SPI communication need their directions to be set as follows:
 SDI is automatically controlled by the SPI module.
 SDO must have TRISC<5> bit cleared.
 SCK (master mode) must have TRISC<3> bit cleared.
 SCK (slave mode) must have TRISC<3> bit set.
 SS must have TRISA<4> bit set.

Any serial port function that is not desired may be overridden by programming the corresponding data
direction (TRIS) register to the opposite value.

Interrupt Control Registers

 PIE1 (address 8Ch) contains the interrupt enable bit, SSPIE for the MSSP module.
 PIR1 (address 0Ch) contains the interrupt flag, SSPIF for the MSSP module.

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  INTCON (addresses 0Bh, 8Bh, 108Bh and 18Bh) contains the global interrupt enable bits GIE and
PEIE, that also affect the operation of the SSP interrupt.

Steps for running SPI communication

1. Configure the MSSP module:
 Select the SPI mode using bits SSPM3:SSPM0 in SSPCON1.
 Select the clock polarity and enable the SSP module respectively using CKP and SSPEN in
SSPCON1.
 Select the sample point and clock transition on which transmission occurs respectively using
SMP and CKE in SSPSTAT.
 Configure port pin directions for SSP pins as required for operation in SPI mode.
2. Writing to slave (master side):
 Select the slave to communicate with using the slave select line.
 Write the transmit data to SSPBUF (master side).
 Check WCOL and if set, clear it and rewrite the transmit data to SSPBUF. Repeat until WCOL
is read as cleared.
3. Reading from slave (master side):
 Select the slave to communicate with using the slave select line.
 Write the transmit data to SSPBUF (master side).
 Read SSPBUF.
4. Receiving data from master (slave side)
 Poll the buffer full bit (BF) and read SSPBUF when BF is read as set. Alternatively wait for an
MSSP receive interrupt.
 Overflows may be checked by checking state of SSPOV.

A typical connection may have the following scenarios of communication:

 Master sends data, slave sends dummy data. Effectively master is sending data to the slave.
 Master sends data, slave sends data. Effectively master and slave are exchanging data.
 Master sends dummy data, slave sends data. Effectively slave is sending data to the master.

When the slave mode is receiving only, the SDO can be disabled by setting it as an input.
Notes
1. A write to SSPBF during transmission of a byte is ignored. The SSPBF is not changed and WCOL is set.
2. Data reception before last received value in SSPBF is read is ignored. The received data is lost and
the SSPOV is set.
3. SPI in mast mode is halted when sleep mode is entered. SPI in slave mode continues to operate and
causes a wakeup whenever data is received.

The I2C mode

The PIC can be configured as an I2C master or I2C slave. The MSSP module implements the standard mode
specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer:
 RC3/SCK/SCL – Serial clock (SCL)
 RC4/SDI/SDA – Serial data (SDA)

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 Figure 9.3

The MSSP module in I2C mode provides interrupts on start and stop bits in hardware to determine a free bus
(multi-master function).

Use of Associated Registers – I2C mode

SSPADD Register (address 93h)
It is used to hold the address of the slave by the slave. In master mode it is used to generate the baud rate.

SSPBUF Register (address 94h)

It is the buffer register for received data or data to be transmitted.

The SSPCON1 register (address 14h)

It is used to select the mode and control operation of the MSSP.

SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

 1111 – I2C Slave mode, 10-bit address with start and stop bit interrupts enabled.
 1110 – I2C Slave mode, 7-bit address with start and stop bit interrupts enabled.
 1011 – I2C Firmware Controlled Master mode (Slave Idle)
𝐹𝑂𝑆𝐶
 1000 – I2C Master mode, 𝑐𝑙𝑜𝑐𝑘 = 4(𝑆𝑃𝐴𝐷𝐷 + 1)
 0111 – I2C Slave mode, 10-bit address

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  0110 – I2C Slave mode, 7-bit address
 Note: Bit combinations not specifically listed here are either reserved or implemented in SPI mode
only.
CKP: SCK Release Control bit
 In Slave mode:
o 1 – Release clock
o 0 – Holds clock low (clock stretch). Used to ensure data setup time is met.
 In Master mode, it not used.
SSPEN: Synchronous serial port enable bit
 1 – Enables serial port and configures SDA and SCL as serial port pins
 0 – Disables serial port and configures these pins as I/O port pins
 Note: When enabled, SDA and SCL pins must be properly configured as input or output.
SSPOV: Receive overflow indicator bit
 In Receive mode:
o 1 – A new byte is received while the SSPBUF register is still holding the previous data. (Must
be cleared in software.)
o 0 – No overflow
 In Transmit mode, this is a “don’t care” bit in Transmit mode.
WCOL: Write collision detect bit
 In master transmit mode:
o 1 – The SSPBUF register is attempted while conditions were not valid for a transmission to
be started. (Must be cleared in software.)
o 0 – No collision
 In slave mode:
o 1 – The SSPBUF register is written while it is still transmitting the previous word. (Must be
cleared in software.)
o 0 – No collision
 In master receive mode, the bit is a “don’t care”.

The SSPCON2 register (address 91h)

It is used to control the operation of the MSSP in the I2C mode.

GCEN: General Call Enable bit (Slave mode only)

 1 – Enable interrupt when a general call address (0000h) is received in the SSPSR.
 0 – General call address disabled.
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
 1 – Acknowledge was not received from slave.
 0 – Acknowledge was received from slave.
ACKDT: Acknowledge Data bit (Master Receive mode only)
 1 – Not Acknowledge
 0 – Acknowledge
 Note: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
a receive.
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)

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  1 – Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically
cleared by hardware.
 0 – Acknowledge sequence Idle
RCEN: Receive Enable bit (Master mode only)
 1 – Enables Receive mode for I2C
 0 – Receive Idle
PEN: Stop Condition Enable bit (Master mode only)
 1 – Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
 0 – Stop condition Idle
RSEN: Repeated Start Condition Enabled bit (Master mode only)
 1 – Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
 0 – Repeated Start condition Idle
SEN: Start Condition Enabled/Stretch Enabled bit
 In Master mode:
o 1 – Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
o 0 – Start condition Idle
 In Slave mode:
o 1 – Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
o 0 – Clock stretching is enabled for slave transmit only (PIC16F87X compatibility)

The SSPSTAT register (address 94h)

The register contains bits that tell the status of the I2C module.

SMP: Slew Rate Control bit

 In Master or Slave mode:
o 1 – Slew rate control disabled for standard speed mode (100 kHz and 1 MHz).
o 0 – Slew rate control enabled for high-speed mode (400 kHz).
CKE: SMBus Select bit
 In Master or Slave mode:
o 1 – Enable SMBus specific inputs.
o 0 – Disable SMBus specific inputs.
D/A: Data/Address bit
 In Master mode, it is reserved.
 In Slave mode:
o 1 – Indicates that the last byte received or transmitted was data.
o 0 – Indicates that the last byte received or transmitted was address.
P: Stop bit
 1 – Indicates that a Stop bit has been detected last
 0 – Stop bit was not detected last
 Note: This bit is cleared on reset and when SSPEN is cleared.
S: Start bit
 1 – Indicates that a Start bit has been detected last
 0 – Start bit was not detected last

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  Note: This bit is cleared on Reset and when SSPEN is cleared.
R/W: Read/Write bit information (I2C mode only)
 In Slave mode:
o 1 – Read
o 0 – Write
o Note: This bit holds the R/W bit information following the last address match. This bit is only
valid from the address match to the next Start bit, Stop bit or not ACK bit.
 In Master mode:
o 1 – Transmit is in progress.
o 0 – Transmit is not in progress.
o Note: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle
mode.
UA: Update Address (10-bit Slave mode only)
 1 – Indicates that the user needs to update the address in the SSPADD register.
 0 – Address does not need to be updated.
BF: Buffer Full Status bit
 In Transmit mode:
o 1 – Receive complete, SSPBUF is full.
o 0 – Receive not complete, SSPBUF is empty.
 In Receive mode:
o 1 – Data Transmit in progress (does not include the ACK and Stop bits), SSPBUF is full.
o 0 – Data Transmit complete (does not include the ACK and Stop bits), SSPBUF is empty.

TRISC
Some of the pins used for SPI communication need their directions to be set as follows:
 SCL must have TRISC<3> bit set.
 SDA must have TRISC<4> bit set.

The MSSP module will override the input state with the output data when required (for slave-transmitter).

To ensure proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA
pins.

Interrupt Control Registers

 PIE1 (address 8Ch) contains the interrupt enable bit, SSPIE for MSSP module.
 PIR1 (address 0Ch) contains the interrupt flag, SSPIF for the MSSP module.
 INTCON (addresses 0Bh, 8Bh, 108Bh and 18Bh) contains the global interrupt enable bits GIE and
PEIE, that also affect the operation of the SSP interrupt.

Steps for running I2C communication

Setting up (both master and slave sides)
1. In the SSPCON1 register:
 Select the I2C mode using the bits SSPM3:SSPM0.
 Select clock release or clock stretch (for slave mode) using CKP.
 Enable the SSP using the SSPEN bit.
 Clear the WCOL bit.
2. In the SSPCON2, set the bits to suit the required options of operation of the I2C module.
3. In the SSPSTAT register:
 Select the slew rate using the SMP bit.
 Enable or disable SMBus using the CKE bit.

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 4. To the SSPADD
 Write the slave address when device is to be in slave mode.
 Write a value to generate the required baud rate. The baud rate is given by the formulae
𝐹𝑂𝑆𝐶
𝑏𝑎𝑢𝑑 𝑟𝑎𝑡𝑒 = 4(𝑆𝑃𝐴𝐷𝐷 + 1)
5. Using TRISC, configure port pin directions of SCL and SDA as required for I2C operation.

Operation of slave side

Once the MSSP module has been set up enabled, it waits for a start condition to occur. Following the start
condition, 8 bits are shifted into the SSPSR register each with each clock cycle. These bits represent the
address (7 upper bits) of the slave to be accessed and the nature of the intended access (LSB) as a read (bit
set) or a write (bit cleared). If the address received matches the address in the SSPADD, the BF bit is clear
and SSPOV bit is clear, the received address written to SSPBUF and the BF and SSPIF are set. An interrupt can
be raised. The SSPBF can then be read to clear the BF and SSPOV flags so as to make the slave ready to
receive the data bytes. Bytes are received one at a time. If there is no match of address, the device waits for
another start condition. If the BF flag is set, the reception is ignored and SSPOV is set.

If 10-bit address mode is used, the address is received in two bytes. The first byte carries the information
indicating that 10-bit address is used and the two MSBs of the address. The high byte is if the format
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSBs of the address and the upper 5-bit pattern
indicates use of a 10-bit address. The SSPADD of the intended slave initially contains the high byte of a 10-bit
address. When a match of the high byte occurs, the received address is stored in SSPBUF. The slave SSPBUF
can then be read and the SSPADD is updated with the low byte. If the low byte matches in the next
reception, the received low address is stored in SSPBUF. The SSPBUF can then be read so that data reception
can begin.

Running the slave side

The steps for running the slave side are:
1. Poll the buffer full bit (BF) and read SSPBUF when BF is read as set. The read value will be an address
value that matches the slave address. Alternatively wait for the SSP interrupt.
2. If bit UA in SSPSTAT is set, update SSPBUF with the low address value, wait for a byte to be received,
read SSPBUF when byte received (match occurred for the low byte of address) and update SSPADD
with high byte of the address.
3. If R/W bit in SSPSTAT is cleared, the slave is being accessed for a write (slave being written to):
 Poll the buffer full bit (BF) and read SSPBUF when BF is read as set. The read value will be a
data byte. Alternatively wait for the SSP interrupt. An interrupt can be raised with each
received byte.
4. If R/W bit in SSPSTAT is set, the slave is being accessed for a read (slave being read):
 Write the transmit data to SSPBUF. Check WCOL and if set, clear and write again to SSPBUF.
Repeat until WCOL is read as cleared.
 Set CKP to release the clock. If an acknowledge is not received, the slave automatically resets
and waits for another start condition. If an acknowledge is received, the master expects
another byte.
 Note: After transmission of each byte, the clock is automatically stretched to allow
transmitting end to respond.
 Poll the SSPIF and when set, check the status of the byte in the SSPSTAT to respond
accordingly (set slave in correct state). Alternatively wait for the SSP interrupt.

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Operation of the master side
The master device generates all of the serial clock pulses and the start and stop conditions. A transfer is
started using a start condition and is ended using a stop or a repeated start condition. Serial data is
transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.

The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write
(R/W) bit.

The baud rate generator used for the SPI mode operation is used to set the SCL clock frequency for either
100 kHz, 400 kHz or 1 MHz I2C operation.

Running the I2C Master side

1. Generate the start condition by setting the SEN bit in SSPCON2. SSPIF is set. The MSSP module will
wait the required Start time before any other operation takes place.
2. Load the slave address into SSPBUF. The address is transmitted out. At the end of the transmission,
the MSSP module shifts in the ACK bit from the slave device and writes it into SSPCON2<6>. The SSP
interrupt is generated.
3. When transmitting:
 Load SSPBUF with eight bits of data. The data is transmitted out. After the transmission, the
MSSP module shifts in the ACK bit from the slave device and writes it into SSPCON2<6>. The
SSP interrupt is generated.
 Repeat until all bytes have been transmitted out, each time generating the repeated start
condition using RSEN before writing to SSPBUF.
 Generate the stop condition by setting the PEN bit in SSPCON2. The SSP interrupt is
generated when the start condition is complete.
4. When receiving:
 Poll the buffer full bit (BF) and read SSPBUF when BF is read as set. The read value will be a
data byte. Alternatively wait for the SSP interrupt. An interrupt can be raised with each
received byte.
 Repeat until all bytes have been received, each time generating the repeated start condition
using RSEN before after reading the SSPBUF.

Tutorial Questions
1. Develop C programs to perform the following:
a) Set a PIC as a synchronous USART master and send or receive data.
b) Set a PIC as a synchronous USART slave and receive or transmit data.
c) Set a PIC as an asynchronous USART and receive or transmit data.

2. Develop C programs to perform the following:

a) Set a PIC as a SPI master and send or receive data.
b) Set a PIC as a SPI slave and receive or transmit data.

3. Develop C programs to perform the following:

a) Set a PIC as a I2C master and send or receive data.
b) Set a PIC as a I2C slave and receive or transmit data.

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