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BCS402-Notes

Module-2: ARM INSTRUCTION SET

Contents

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 Lecture Notes | BCS402 – MC Module 2

MODULE-2
INTRODUCTION TO THE ARM INSTUCTION SET

Fundamentals of ARM instructions:

• ARM Processor contains Set of instruction sets which used to develop an ARM based
applications.
• ARM has three instruction set states
1. 32 bit ARM instruction set
2. 16 bit Thumb instruction set
3. 8 bit Jazelle instruction set
1. ARM instruction set: 32 bit Load-Store architecture with every instruction conditionally
execute.
2. Thumb instruction set: 16 bit with only branch instruction conditional executes and only halfof
the registers being used. It is improves high code density.
3. Jazelle instruction set: Allows Java byte code to be directly executed in ARM architecture,
improves performance by 5 to 10 times.

Instruction Format:

Label Mnemonics{<condition>}{S} Rd , Rn, {#_immediate | Rm | N } ;comments

Label - Labels are symbols representing the addresses in memory of instructions or data.
MNEMONIC - Short name (mnemonic) of the instruction.
{S} - An optional suffix, If S is specified; the condition flags are updated on the result of the
operation.
{condition} - Condition that is needed to be met in order for the instruction to be executed.
{Rd} - Register (destination) for storing the result of the instruction
Operand1 - First operand, either a register or an immediate value
Operand2 - Second (flexible) operand, Can be an immediate value (number) or a register with an
optional shift.

Features of the ARM Instruction Set:

* All instructions are 32 bits long.
* Most instructions execute in a single cycle.
* Every instruction can be conditionally executed.
* Data processing instructions act only on registers.
* Combined ALU and shifter design for a high speed bit manipulation.
* Memory access instructions with powerful auto-indexing addressing modes.
* Flexible multiple register load and store instructions
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 Lecture Notes | BCS402 – MC Module 2

MAC Unit:
• Multiply Accumulate operation is that computes the product of two numbers and adds
that product to an accumulator.
• The hardware unit that performs the operation is known as a multiplier–
accumulator (MAC, or MAC unit)
• The MAC operation modifies an accumulator, Rd Rn + (Rm x Rs)
• MAC operation is widely used in convolution.

Example:
Pre R4=0x0000 0001
R3=0x0000 0002
R2=0x0000 0002
R1=0x0000 0002
MLA R4, R3, R2, R1
Post R4=0x0000 0006
R3=0x0000 0002
R2=0x0000 0002
R1=0x0000 0002
R4 R1 + (R3 x R2)

Barrel Shifter:
• A unique and powerful feature of ARM Processor is that, it has in built barrel shifter used
to shifts or rotates (preprocessing) the 32 bit binary pattern in one of the source operand
register Rm left or right by a specific number of positions before it enters the ALU.
• Shifts increases the power and flexibility of data processing operations.
• The preprocessing or shift occurs in one cycle time of execution.
• It is useful to achieve fast multiplication or division by a power of 2.

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 Lecture Notes | BCS402 – MC Module 2

Shifted register operand:

• Barrel Shifter provides five types of Shift and Rotate operations and they are :
1. Logical Shift Left (LSL)
2. Logical Shift Right (LSR)
3. Arithmetic Shift Right (ASR)
4. Rotate Right (ROR)
5. Rotate Right Extended (RRX)
Note:

(1) Logical shift left:

▪ The value of a register bits shift towards the most significant bit position, by n bits.
Ex. MOV R0, R1, LSL # 2
▪ After the execution of this instruction R0 will become the value of R1 shifted 2 bits.
(2) Logical shift right:
▪ The value of a register shift towards right by n bits.
Ex. MOV R0, R1, LSR R2
▪ After the execution of this instruction R0 will have the value of R1 shifted right by
R2 times. R1 and R2 are not altered.
(3) Arithmetic shift right:
▪ This is similar to logical shift right, except that the MSB is retained as well as shifted
for arithmetic shift operation.
Ex. MOV R0, R1, ASR #2
▪ After the execution of this instruction R0 will have the value of R1 Arithmetic;
shifted right by 2 bits.
(4) Rotate right:
▪ The value of a register rotate right by n bits

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 Lecture Notes | BCS402 – MC Module 2

Ex. MOV R0, R1, ROR R2

▪ After the execution of this instruction R0 will have the value of R1 rotated right for
R2 times.
(5) Rotate right extended:
▪ This is similar to Rotate right by one bit, with the carry flag moved into the MSB, i.e.
it is similar to rotate right through carry.
Ex. MOV R0, R1 RRX
▪ After the execution of this instruction R0 will have the value of register R1 rotated
right through carry by 1 bit.

ARM instruction set Classification:

ARM instruction set classified into 5 types. They are
1. Data Processing instructions
2. Branch Instructions
3. Load- Store Instructions
4. Software Interrupt instructions
5. Program Status Register Instructions

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 Lecture Notes | BCS402 – MC Module 2

1. Data Processing instructions:

• Data Processing instructions are used to manipulate data within the registers.
• Most of the instruction preprocesses one of source operand using barrel shifter.
• Some instructions uses suffix ‘S’ to updates the cpsr flag bits after results.
Syntax:
< instruction>{<cond>}{s} Rd, Rn, N
Data Processing Instructions are classified into 5 types.
They are,
1. Move Instructions
2. Arithmetic instructions
3. Logical Instructions
4. Compare Instructions
5. Multiple Instructions

1. Move Instructions:
• It is used to copies data from source operand registers or a immediate constant 32 bit
value to destination operand register.

Syntax:<Instruction>{<cond>}{S} Rd, N

1. MOV
• MOV (Move), copies a value into the destination register.
• The value can be either an immediate value or a value from a register, and can be shifted
before the write.
• MOV can optionally update the condition code flags, based on the result.
Syntax:
MOV{<cond>}{S} <Rd>, N
Rd N
Where, N can be an immediate value (number) or a register with an optional shift.
Ex_1:
PRE r5 = 5
r7 = 8
MOV r7, r5 ; r7 = r5
POST r5 = 5
r7 = 5
Ex_2:
PRE cpsr = nzcvqiFt_USER
r0 = 0x00000000
r1 = 0x80000004

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 Lecture Notes | BCS402 – MC Module 2

MOVS r0, r1, LSL #1

POST cpsr = nzCvqiFt_USER
r0 = 0x00000008
r1 = 0x80000004 ■
Ex_3:
PRE r5 = 5
r7 = 8
MOV r7, r5, LSL #2 ; let r7 = r5*4 = (r5 << 2)
POST r5 = 5
r7 = 20

2. MVN
• MVN (Move Not) generates the logical one’s complement of a value and places result in
Rd.
• The value can be either an immediate value or a value from a register, and can be shifted
before the MVN operation.
• MVN can optionally update the condition code flags, based on the result.
Syntax:
MVN{<cond>}{S} <Rd>, N
Rd Not ( N )
Ex_1: PRE r5 = 5
r7 = 8
MVN r7, r5 ; r5= 0000 0000 0000 0000 0000 0000 0000 0101
POST r5 = 5 ; ~r5= 1111 1111 1111 1111 1111 1111 1111 1010
r7 = 0xFFFFFFFA ; (0xFFFFFFFA)

2. Arithmetic Instructions:
• The arithmetic instructions implement addition and subtraction of 32-bit signed and
unsigned values.
Syntax:
<instruction>{<cond>}{S} Rd, Rn, N

ADC:
• ADC (Add with Carry), adds two values and the Carry flag.
• The first value comes from a register.

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 Lecture Notes | BCS402 – MC Module 2

• The second value can be either an immediate value or a value from a register, and can be
shifted before the addition.
• ADC can optionally update the condition code flags, based on the result.

Syntax:-
ADC{<cond>}{S} Rd, Rn , N
Rd →Rn + N
Example_1: PRE R0 = 0x0000 0005
R2 = 0x0000 0008
R4 = 0x0000 0000
ADD R4,R0,R2
POST R0 = 0x0000 0005
R2 = 0x0000 0008
R4 = 0x0000 000D

ADD
• ADD, adds two 32 bit values.
• The first value comes from a register.
• The second value can be either an immediate value or a value from a register, and can be
shifted before the addition.
• ADD can optionally update the condition code flags, based on the result.
Syntax:
ADD{<cond>}{S} Rd, Rn, N

SUB
• SUB (Subtract) subtracts one value from a first value.
• The first value comes from a register.
• The second value can be either an immediate value or a value from a register, and can be
shifted before the subtraction.
• SUB can optionally update the condition code flags, based on the result.
Syntax:
SUB{<cond>}{S} <Rd>, <Rn>, N

SBC
• SBC (Subtract with Carry), subtracts the value of its second operand and the value of
NOT(Carry flag) from the value of its first operand.
• The first operand comes from a register.
• The second operand can be either an immediate value or a value from a register, and can
be shifted before the subtraction.
• Use SBC to synthesize multi-word subtraction.
• SBC can optionally update the condition code flags, based on the result.
Syntax:
SBC{<cond>}{S} <Rd>, <Rn>, N

RSB

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 Lecture Notes | BCS402 – MC Module 2

• RSB (Reverse Subtract) subtracts a value from a second value.

• The first value comes from a register.
• The second value can be either an immediate value or a value from a register, and can be
shifted before the subtraction.
• This is the reverse of the normal order of operands in ARM assembler language.
• RSB can optionally update the condition code flags, based on the result.
Syntax:
RSB{<cond>}{S} <Rd>, <Rn>, N

RSC
• RSC (Reverse Subtract with Carry) subtracts a value from a second value, and the value
of NOT(Carry flag) from the value of its second operand.
• The normal order of the operands is reversed, to allow subtraction from a shifted register
value, or from an immediate value.
• RSC can optionally update the condition code flags, based on the result.
Syntax:
RSC{<cond>}{S} <Rd>, <Rn>, N

Logical Instructions:
• Logical instructions perform bitwise logical operations on the two source registers.
Syntax: <instruction>{<cond>}{S} Rd, Rn, N

1. AND
• AND performs a bitwise AND of two values.
• The first value comes from a register.
• The second value can be either an immediate value or a value from a register, and can be
shifted before the AND operation.
• AND can optionally update the condition code flags, based on the result.
Syntax:
AND{<cond>}{S} <Rd>, <Rn>, N

2. ORR
• ORR (Logical OR) performs a bitwise (inclusive) OR of two values.
• The first value comes from a register.
• The second value can be either an immediate value or a value from a register, and can be
shifted before the OR operation.
• ORR can optionally update the condition code flags, based on the result.

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 Lecture Notes | BCS402 – MC Module 2

Syntax:
ORR{<cond>}{S} <Rd>, <Rn>, N

3. EOR
• EOR (Exclusive OR) performs a bitwise Exclusive-OR of two values.
• The first value comes from a register.
• The second value can be either an immediate value or a value from a register, and can be
shifted before the exclusive OR operation.
• EOR can optionally update the condition code flags, based on the result.
Syntax:
EOR{<cond>}{S} <Rd>, <Rn>, N

4. BIC
• BIC (Bit Clear) performs a bitwise AND of one value with the complement of a second
value.
• The first value comes from a register.
• The second value can be either an immediate value or a value from a register, and can be
shifted before the BIC operation.
• BIC can optionally update the condition code flags, based on the result.
Syntax:
BIC{<cond>}{S} <Rd>, <Rn>, N

Compare Instructions:
• The comparison instructions are used to compare or test a register with a 32-bit value.
• They update the cpsr flag bits according to the result, but do not affect other registers.

1. CMP
• CMP (Compare) compares two values.
• The first value comes from a register.
• The second value can be either an immediate value or a value from a register, and can be
shifted before the comparison.
• CMP updates the condition flags, based on the result of subtracting the second value from
the first.
Syntax:
CMP{<cond>} <Rn>, N

2. CMN
• CMN (Compare Negative) compares one value with the twos complement of a second
value.
• The first value comes from a register.
• The second value can be either an immediate value or a value from a register, and can be
shifted before the comparison.
• CMN updates the condition flags, based on the result of adding the two values.
Syntax:
CMN{<cond>} Rn, N

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 Lecture Notes | BCS402 – MC Module 2

3. TEQ
• TEQ (Test Equivalence) compares a register value with another arithmetic value.
• The condition flags are updated, based on the result of logically exclusive-ORing the two
values, so that subsequent instructions can be conditionally executed.
Syntax:
TEQ{<cond>} <Rn>, N

4. TST
• TST (Test) compares a register value with another arithmetic value.
• The condition flags are updated, based on the result of logically ANDing the two values,
so that subsequent instructions can be conditionally executed.
Syntax:
TST{<cond>} <Rn>, N

Multiple Instructions:
• The multiply instructions multiply the contents of a pair of registers and, depending upon
the instruction, accumulate the results in with another register.
• The long multiplies accumulate onto a pair of registers representing a 64-bit value. The
final result is placed in a destination register or a pair of registers.
Syntax:
MLA{<cond>}{S} Rd, Rm, Rs, Rn
MUL{<cond>}{S} Rd, Rm, Rs
<Long_instruction>{<cond>}{S} RdLo, RdHi, Rm, Rs
Types:

1. MLA (multiply and accumulate ) Rd = (Rm*Rs) + Rn

2. MUL (multiply) Rd = Rm*Rs
3. SMLAL (signed multiply accumulate long) [RdHi, RdLo] = [RdHi, RdLo] + (Rm *Rs)
4. SMULL (signed multiply long) [RdHi, RdLo] = Rm *Rs
5. UMLAL (unsigned multiply accumulate long) [RdHi, RdLo] = [RdHi, RdLo] + (Rm *Rs)
5. UMULL (unsigned multiply long) [RdHi, RdLo] = Rm ∗ Rs

1. MUL
• MUL (Multiply) multiplies two signed or unsigned 32-bit values.
• The least significant 32 bits of the result are written to the destination register.
• MUL can optionally update the condition code flags, based on the result.
Syntax:
MUL{<cond>}{S} <Rd>, <Rm>, <Rs>
where
<Rd> - Specifies the destination register for the instruction.
<Rm> - Specifies the register that contains the first value to be multiplied.
<Rs> - Holds the value to be multiplied with the value of <Rm>.

2. MLA
• MLA (Multiply Accumulate) multiplies two signed or unsigned 32-bit values, and adds a
third 32-bit value.

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 Lecture Notes | BCS402 – MC Module 2

• The least significant 32 bits of the result are written to the destination register.
• MLA can optionally update the condition code flags, based on the result.
Syntax:
MLA{<cond>}{S} <Rd>, <Rm>, <Rs>, <Rn>
Where,
<Rd> - Specifies the destination register.
<Rm> - Holds the value to be multiplied with the value of <Rs>.
<Rs> - Holds the value to be multiplied with the value of <Rm>.
<Rn> - Contains the value that is added to the product of <Rs> and <Rm>.

SMULL
• SMULL (Signed Multiply Long) multiplies two 32-bit signed values to produce a 64-bit
result.
• SMULL can optionally update the condition code flags, based on the 64-bit result.
Syntax:
SMULL{<cond>}{S} <RdLo>, <RdHi>, <Rm>, <Rs>
Where,
<RdLo> - Stores the lower 32 bits of the result.
<RdHi> - Stores the upper 32 bits of the result.
<Rm> - Holds the signed value to be multiplied with the value of <Rs>.
<Rs> - Holds the signed value to be multiplied with the value of <Rm>.

SMLAL
• SMLAL (Signed Multiply Accumulate Long) multiplies two signed 32-bit values to
produce a 64-bit value, and accumulates this with a 64-bit value.
• SMLAL can optionally update the condition code flags, based on the result.
Syntax:
SMLAL{<cond>}{S} <RdLo>, <RdHi>, <Rm>, <Rs>
Where,
<RdLo> - Stores the lower 32 bits of the result.
<RdHi> - Stores the upper 32 bits of the result.
<Rm> - Holds the signed value to be multiplied with the value of <Rs>.
<Rs> - Holds the signed value to be multiplied with the value of <Rm>.

UMLAL
• UMLAL (Unsigned Multiply Accumulate Long) multiplies the unsigned value of register
<Rm> with the unsigned value of register <Rs> to produce a 64-bit product.
• This product is added to the 64-bit value held in <RdHi> and <RdLo>, and the sum is
written back to <RdHi> and <RdLo>.
• The condition code flags are optionally updated, based on the result.
Syntax:
UMLAL{<cond>}{S} <RdLo>, <RdHi>, <Rm>, <Rs>
Where,
<RdLo> - Stores the lower 32 bits of the result.
<RdHi> - Stores the upper 32 bits of the result.
<Rm> - Holds the signed value to be multiplied with the value of <Rs>.

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 Lecture Notes | BCS402 – MC Module 2

<Rs> - Holds the signed value to be multiplied with the value of <Rm>.

UMULL
• UMULL (Unsigned Multiply Long) multiplies the unsigned value of register <Rm> with
the unsigned value of register <Rs> to produce a 64-bit result.
• The upper 32 bits of the result are stored in <RdHi>.
• The lower 32 bits are stored in <RdLo>.
• The condition code flags are optionally updated, based on the 64-bit result.
Syntax
UMULL{<cond>}{S} <RdLo>, <RdHi>, <Rm>, <Rs>
Where,
<RdLo> - Stores the lower 32 bits of the result.
<RdHi> - Stores the upper 32 bits of the result.
<Rm> - Holds the signed value to be multiplied with the value of <Rs>.
<Rs> - Holds the signed value to be multiplied with the value of <Rm>.
Example 1:
PRE r0 = 0x00000000
r1 = 0x00000002
r2 = 0x00000002
MUL r0, r1, r2 ; r0 = r1*r2
POST r0 = 0x00000004
r1 = 0x00000002
r2 = 0x00000002
Example 2:
PRE r0 = 0x00000000
r1 = 0x00000000
r2 = 0xf0000002
r3 = 0x00000002
UMULL r0, r1, r2, r3 ; [r1,r0] = r2*r3
POST r0 = 0xe0000004 ; = RdLo
r1 = 0x00000001 ; = RdHi

Branch Instructions:
• These control flow of execution include the various forms of PC-
relative branch and branch-and-link instruction seen in the ARM
instruction set, and
• Branch-and-exchange instruction for switching between the ARM and
Thumb instruction sets.
Syntax: B{<cond>} label
BL{<cond>} label
BX{<cond>} Rm
BLX{<cond>} label | Rm
Types
1. B branch pc = label

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 Lecture Notes | BCS402 – MC Module 2

2. BL branch with link pc = label

lr = address of the next instruction after the BL
3. BX branch exchange pc = Rm & 0xfffffffe, T = Rm & 1
4. BLX branch exchange with link pc = label, T = 1,
pc = Rm & 0xfffffffe, T = Rm & 1
lr = address of the next instruction after the BLX

1. B
• B (Branch), causes a branch to a target address, and provide both conditional and
unconditional changes to program flow.
Syntax:
B{<cond>} <target_address>

<target_addr> - Specifies the address of the Thumb instruction (approximately ±32MB).

2. BL
• BL (Branch and Link) cause a branch to a target address, and provide both conditional
and unconditional changes to program flow.
• BL also stores a return address in the link register, R14 (also known as LR).
Syntax:
BL{<cond>} <target_address>

<target_addr> - Specifies the address of the Thumb instruction (approximately ±32MB).

3. BX:
• BX (Branch and Exchange) branches to an address, with an optional switch to Thumb
state.
Syntax:
BX{<cond>} <Rm>

<Rm> - Holds the value of the branch target address. Bit[0] of Rm is 0 to select a target ARM
instruction, or 1 to select a target Thumb instruction

4. BLX
• BLX, (Branch with Link and Exchange) calls a Thumb subroutine from the ARM
instruction set at an address specified in the instruction.
• Execution of Thumb instructions begins at the target address.
• After completion of execution it return from the subroutine, use a BX R14 instruction, or
store R14 on the stack and reload the stored value into the PC.
Syntax
BLX{<cond>} <target_addr> | Rm

<target_addr> - Specifies the address of the Thumb instruction (approximately ±32MB).

Rm - the register containing the address of the target instruction.

Example 1:

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 Lecture Notes | BCS402 – MC Module 2

B forward
ADD r1, r2, #4
ADD r0, r6, #2
ADD r3, r7, #4
forward
SUB r1, r2, #4
Backward
ADD r1, r2, #4
SUB r1, r2, #4
ADD r4, r6, r7
B backward

Example 2:
BL subroutine ; branch to subroutine
CMP r1, #5 ; compare r1 with 5
MOVEQ r1, #0 ; if (r1==5) then r1 = 0
:
subroutine
<subroutine code>
MOV pc, lr ; return by moving pc = lr

Load – Store Instructions:

• Load-store instructions transfer data between memory and processor registers.
• There are three types of load-store instructions:
1. single-register transfer,
2. multiple-register transfer,
3. swap.
Single-register transfer:
• These instructions are used for moving a single data item in and out of a register.
• The data types supported are signed and unsigned words (32-bit), halfwords (16-bit), and
bytes.
Syntax: <LDR|STR>{<cond>}{B} Rd,addressing
LDR{<cond>}SB|H|SH Rd, addressing
STR{<cond>}H Rd, addressing

• Various load-store single-register transfer instructions

LDR load word into a register Rd <- mem32[address]

STR save byte or word from a register Rd -> mem32[address]
LDRB load byte into a register Rd <- mem8[address]
STRB save byte from a register Rd -> mem8[address]
LDRH load halfword into a register Rd <- mem16[address]
STRH save halfword into a register Rd -> mem16[address]
LDRSB load signed byte into a register Rd <- SignExtend (mem8[address])
LDRSH load signed halfword into a register Rd <- SignExtend (mem16[address])

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 Lecture Notes | BCS402 – MC Module 2

1. LDR
• LDR (Load Register) loads a word from a memory address.
• If the PC is specified as register <Rd>, the instruction loads a data word which it treats as
an address, then branches to that address.
Syntax:
LDR{<cond>} <Rd> , <addressing_mode>
where:
<Rd> Specifies the destination register for the loaded value.

2. LDRB
• LDRB (Load Register Byte) loads a byte from memory and zero-extends the byte to a 32-
bit word.
Syntax:
LDR{<cond>}B <Rd>, <addressing_mode>

3. LDRH
• LDRH (Load Register Halfword) loads a halfword from memory and zero-extends it to a
32-bit word.
Syntax:
LDR{<cond>}H <Rd>, <addressing_mode>

4. LDRSB
• LDRSB (Load Register Signed Byte) loads a byte from memory and sign-extends the
byte to a 32-bit word.
Syntax:
LDR{<cond>}SB <Rd>, <addressing_mode>

5. LDRSH
• LDRSH (Load Register Signed Halfword) loads a halfword from memory and sign-
extends the halfword to a 32-bit word.
• If the address is not halfword-aligned, the result is UNPREDICTABLE.
Syntax:
LDR{<cond>}SH <Rd>, <addressing_mode>

6. STR
• STR (Store Register) stores a word from a register to memory.
Syntax:
STR{<cond>} <Rd>, <addressing_mode>

7. STRB
• STRB (Store Register Byte) stores a byte from the least significant byte of a register to
memory.
Syntax:
STR{<cond>}B <Rd>, <addressing_mode>

8. STRH

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 Lecture Notes | BCS402 – MC Module 2

• STRH (Store Register Halfword) stores a halfword from the least significant halfword of
a register to memory.
• If the address is not halfword-aligned, the result is UNPREDICTABLE.
Syntax:
STR{<cond>}H <Rd>, <addressing_mode>

Example:
;load register r0 with the contents of the memory address pointed to by register r1.

LDR r0, [r1] ; = LDR r0, [r1, #0]

; store the contents of register r0 to ; the memory address pointed to by register r1.

STR r0, [r1] ; = STR r0, [r1, #0]

Multiple register transfer instructions:

• Load-store multiple instructions can transfer multiple registers between memory and the
processor in a single instruction.
• The transfer occurs from a base address register Rn pointing into memory.
• Multiple-register transfer instructions are more efficient from single-register transfers for
moving blocks of data around memory and saving and restoring context and stacks.

Syntax: <LDM|STM>{<cond>}<addressing mode> Rn{!},<registers>{ˆ}

▪ The ! suffix is used, the address is written back into Rn.
▪ ^ - For an STM instruction, indicates that User mode registers are to be stored.

Addressing_mode Description Start address End address Rn!

IA increment after Rn Rn + 4∗N − 4 Rn + 4∗N
IB increment before Rn + 4 Rn + 4∗N Rn + 4∗N
DA decrement after Rn − 4∗N + 4 Rn Rn − 4∗N
DB decrement before Rn − 4∗N Rn − 4 Rn − 4∗N

Types:

1. LDM load multiple registers {Rd}*N  mem32[start address + 4*N] optional Rn updated
2. STM save multiple registers {Rd}*N → mem32[start address + 4*N] optional Rn updated

LDM
• LDM (Load Multiple), loads a non-empty subset, or possibly all, of the general-purpose
registers from sequential memory locations.
• It is useful for block loads, stack operations and procedure exit sequences.
• The general-purpose registers loaded can include the PC.

Syntax:
LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>

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 Lecture Notes | BCS402 – MC Module 2

STM
• STM (Store Multiple), stores a non-empty subset (or possibly all) of the general-purpose
registers to sequential memory locations.
Syntax:
STM{<cond>}<addressing_mode> <Rn>{!}, <registers>

STM
• STM stores a subset (or possibly all) of the User mode general-purpose registers to
sequential memory locations.
Syntax:
STM{<cond>}<addressing_mode> <Rn>, <registers>^
Where,
^ - For an STM instruction, indicates that User mode registers are to be stored.
Example 1:
PRE mem32[0x80010] = 0x01r0
= 0x00080010
r1 = 0x00000000
r2 = 0x00000000
r3 = 0x00000000
LDMIA r0!, {r1-r3}
POST r0 = 0x0008001c
r1 = 0x00000001
r2 = 0x00000002
r3 = 0x00000003

Example 2:
PRE r0 = 0x0000900c
r1 = 0x00000001
r2 = 0x00000002
r3 = 0x00000003
STMIB r0!, {r1-r3}
POST

Example 3:
PRE r0 = 0x0000900c

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 Lecture Notes | BCS402 – MC Module 2

r1 = 0x00000001
r2 = 0x00000002
r3 = 0x00000003
0x00009000 0x00000007
0x00009004 0x00000009
0x00009008 0x00000008
0x0000900c 0x00000007

LDMDA r0!, {r1-r3}

POST r0 = 0x00009000
r1 = 0x00000009
r2 = 0x00000008
r3 = 0x00000007
Stack Operation:
• The ARM architecture uses the load-store multiple instructions to carry out stack
operations.
• The pop operation (removing data from a stack) uses a load multiple instruction.
• The push operation (placing data onto the stack) uses a store multiple instruction.
• The stack memory use to store in either Ascending (A) or Descending (D).
• Ascending stacks grow towards higher memory addresses.
• Descending stacks grow towards lower memory addresses.
• Points the stack address,
1. Full stack (F), the stack pointer (sp) points to the last item on the stack.
2. Empty stack(E), the sp points to first unused or empty location (i.e., after the last item
on the stack).
• There are a number of load-store multiple addressing mode aliases available to support
stack operations.They are,
Addressing Mode PUSH POP
Full Descending (FD) STMFA (STMIB) LDMFA (LDMDA)
Full Ascending (FA) STMFD (STMDB) LDMFD (LDMIA)
Empty Descending(ED) STMEA (STMIA) LDMEA (LDMDB)
Empty Ascending(EA) STMED (STMDA) LDMED (LDMIB)

Example:
PRE r1 = 0x00000002
r4 = 0x00000003
sp = 0x00080014
STMFD sp!, {r1,r4}
POST r1 = 0x00000002
r4 = 0x00000003
sp = 0x0008000c

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 Lecture Notes | BCS402 – MC Module 2

Swap Instructions:
• Swap instructions combine a load and a store of a word or an
unsigned byte in a single instruction.
• These instructions allow a value in a register to be exchanged with a
value in memory.
• Their principal use is to implement semaphores to ensure mutual
exclusion.

SWP
• SWP (Swap) swaps a word between registers and memory.
• SWP loads a word from the memory address given by the value of register <Rn>. The
value of register <Rm> is then stored to the memory address given by the value of <Rn>,
and the original loaded value is written to register <Rd>.
• If the same register is specified for <Rd> and <Rm>, this instruction swaps the value of
the register and the value at the memory address.
Syntax:
SWP{<cond>} <Rd>, <Rm>, [<Rn>]
Where,
<Rd> - Specifies the destination register for the instruction.
<Rm> - Contains the value that is stored to memory.
<Rn> - Contains the memory address to load from.
Example:
SWP r1, r1, [r0] ; exchange 32 bit value

SWPB
• SWPB (Swap Byte), swaps a byte between registers and memory.
• SWPB loads a byte from the memory address given by the value of register <Rn>.
• The value of the least significant byte of register <Rm> is stored to the memory address
given by <Rn>, the original loaded value is zero-extended to a 32-bit word, and the word
is written to register <Rd>.
• If the same register is specified for <Rd> and <Rm>, this instruction swaps the value of
the least significant byte of the register and the byte value at the memory address.
Syntax:
SWP{<cond>}B <Rd>, <Rm>, [<Rn>]

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 Lecture Notes | BCS402 – MC Module 2

Where,
<Rd> - Specifies the destination register for the instruction.
<Rm> - Contains the value that is stored to memory.
<Rn> - Contains the memory address to load from.

Example:
SWPB r1, r1, [r0] ; exchange byte

Software Instructions:
• A software interrupt instruction (SWI) causes a software interrupt exception, which force
the processor into supervisor mode.(privileged mode).
• Each SWI has an associated SWI Number which is used to represent a particular function
call.
• ARM exception entry sequence. In detail, the processor actions are:
1. Save the address of the instruction after the SWI in r14_svc.
2. Save the CPSR in SPSR_svc.
3. Enter supervisor mode and disable IRQs (but not FIQs) by setting
CPSR[4:0] to
100112andCPSR[7]tol.
4. Set the PC to 08 and begin executing the instructions there.
5. A special form of data processing instruction used to return to the

instruction after the SWI the system routine must not only copy
r14_svc back into the PC, but it must also restore the CPSR from
SPSR_svc.

Syntax:
SWI{<cond>} SWI_number
Where,
SWI_number - Is a 24-bit immediate value that is put into bits[23:0] of the instruction.
Example:
PRE
cpsr = nzcVqift_USER
pc = 0x00008000
lr = 0x003fffff; lr = r14
r0 = 0x12
0x00008000 SWI 0x123456 ; used by ARM toolkits as a debugging SWI
POST
cpsr = nzcVqIft_SVC
spsr = nzcVqift_USER
pc = 0x00000008

Dept of CSE and Comp.Eng,CBIT,Kolar

 Lecture Notes | BCS402 – MC Module 2

lr = 0x00008004
r0 = 0x12
Note: SWI number using the address of the executed instruction, which is calculated from
the link register lr. The SWI number is determined by,
SWI_Number = <SWI instruction> AND NOT(0xff000000).

Example:

Status register access instructions:

• ARM has two instructions for moving the contents of a program status register to or from
a general-purpose register.
• Both the CPSR and SPSR can be accessed.

1. MRS

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 Lecture Notes | BCS402 – MC Module 2

• MRS (Move PSR to general-purpose register) moves the value of the CPSR or the SPSR
of the current mode into a general-purpose register.
• In the general-purpose register, the value can be examined or manipulated with normal
data-processing instructions.
Syntax:
MRS{<cond>} <Rd>, CPSR
MRS{<cond>} <Rd>, SPSR
Where
<Rd> specifies the destination register.
Note:If R15 is specified for <Rd>, the result is UNPREDICTABLE.

2. MSR
• MSR (Move to Status Register from ARM Register) transfers the value of a general-
purpose register or an immediate constant to the CPSR or the SPSR of the current mode.
Syntax:
MSR{<cond>} CPSR_<fields>, #<immediate>
MSR{<cond>} CPSR_<fields>, <Rm>
MSR{<cond>} SPSR_<fields>, #<immediate>
MSR{<cond>} SPSR_<fields>, <Rm>
Where,
<fields> - These fields relate to particular byte regions in a psr register,
c sets the control field mask bit (bit 16)
x sets the extension field mask bit (bit 17)
s sets the status field mask bit (bit 18)
f sets the flags field mask bit (bit 19).
<immediate> -Is the immediate value to be transferred to the CPSR or SPSR.
<Rm> Is the general-purpose register to be transferred to the CPSR or SPSR.

Example 1:
MRS R0, CPSR ; Read the CPSR
BIC R0, R0, #0xF0000000 ; Clear the N, Z, C and V bits
MSR CPSR_f, R0 ; Update the flag bits in the CPSR
; N, Z, C and V flags now all clear
Example 2:
PRE

cpsr = nzcvqIFt_SVC
MRS r1, cpsr ; The MSR first copies the cpsr into register r1
BIC r1, r1, #0x80 ; 0b01000000 (The BIC instruction clears bit 7 of r1)
MSR cpsr_c, r1 ; Register r1 is then copied back into the cpsr
; enables IRQ interrupts
POST

i
cpsr = nzcvq Ft_SVC

Indexed Addressing:

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 Lecture Notes | BCS402 – MC Module 2

▪ The offset address is added to the value in Rn before the transfers take place.
▪ The result is used as the memory address for the transfers.
▪ The base address Rn is not updated with new value.
Example:
PRE r0 = 0x00000000
r1 = 0x00090000
mem32[0x00009000] = 0x01010101
mem32[0x00009004] = 0x02020202
LDR r0, [r1, #4]
POST r0 = 0x02020202
r1 = 0x00009000
Exmple_2:
LDR R0, [R1],#4 ; R0  value at [R1], R1  R1+4
LDR R0, [R1],R2 ; R0 value at [R1], R1 R1+R2

2. Preindexing with writeback:

▪ The offset address is added to the value in Rn before the transfers take place.
▪ The result is used as the memory address for the transfers.
▪ The ! suffix is used, the address is written back into Rn.
Example:
PRE r0 = 0x00000000
r1 = 0x00090000
mem32[0x00009000] = 0x01010101
mem32[0x00009004] = 0x02020202

LDR r0, [r1, #4]!

POST r0 = 0x02020202
r1 = 0x00009004
Exmple_2:
LDR R0, [R1,#4]! ; R0  value at [R1+4], R1  R1+4
LDR R0, [R1,R2]! ; R0  value at [R1+R2], R1  R1+R2

3. Post-indexed offset
▪ The value in Rn is used as the memory address for the transfer.
▪ The offset is applied to the value in Rn after the transfer takes place.
▪ The result is written back into Rn.
Example:

Postindexing:
PRE r0 = 0x00000000
r1 = 0x00090000
mem32[0x00009000] = 0x01010101
mem32[0x00009004] = 0x02020202

LDR r0, [r1], #4

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 Lecture Notes | BCS402 – MC Module 2

POST r0 = 0x01010101
r1 =0x00009004
Example_2:
LDR R0, [R1],#4 ; R0 value at [R1], R1  R1+4
LDR R0, [R1],R2 ; R0 value at [R1], R1  R1+R2

Distinguish between post & pre indexed addressing mode with an example

Pre-indexing Post-indexing
Pre-indexing involves direct addressing and Post-indexing also uses direct addressing and
indexing indexing
Indexing is performed before indirection Indexing is performed after indirection
Base register contains memory address Memory address is base register value.
Base register value can be updated by
Offset can be added or subtracted using base
incrementing or decrementing the offset value (i.e.
updated base register). register value (i.e. updated base register).
Sum of base address plus offset yields effective Base address stored in base register is used
address. directly as effective address
Result is stored in updated base register Result is stored in original base register

Describe the difference between ADR & ADRL.

1. ADR:(Address Relataive)
Syntax: ADR <register> <label>
• This instruction will load the address of label into the indicated register.
• The instruction will evaluate to a PC relative ADD or SUB instruction depending upon
where the label is located.
• This is a small range of address read pseudo instructions
• If the label is out of range, or if it is not defined in the same file (and section) as the ADR
instruction, then an error will be generated.
• This instruction will not make use of the literal pool.
1. ADRL: (Address Relative Long)
Syntax: ADRL <register> <label>
• This instruction will load the address of label into the indicated register.
• The instruction will evaluate to one or two PC relative ADD or SUB instructions
depending upon where the label is located.
• If a second instruction is not needed a NOP instruction will be generated in its place, so
that this instruction is always 8 bytes long.
• This is a medium range address read pseudo instruction.
• If the label is out of range, or if it is not defined in the same file (and section) as the ADRL
instruction, then an error will be generated. This instruction will not make use of the literal
pool.

Example:

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 Lecture Notes | BCS402 – MC Module 2

ADR lr, return_address ; set return address

MOV r0, #0 ; set a function
argument
BX r9 ; call the function

return_address ; resume
• Call the function pointed to by r9. We use ADR to
• Set lr to the return address;
• In this case, it will assemble to ADD lr, pc, #4.
• Recall that pc reads as the address of the current instruction plus eight in this case.
Endianness:
• A memory system uses one of the two following mapping schemes.
1. Little-endian memory system:
• A byte or halfword at a word-aligned address is the least significant byte or
halfwordwithin the word at that address.
• A byte at a halfword-aligned address is the least significant byte within the
halfword atthat address.
Example:
0x12345678
0x0000 78(LSB)
0x0004 56
0x0008 34
0x000C 12(MSB)

2. Big-endian memory system:

• A byte or halfword at a word-aligned address is the most significant byte or
halfwordwithin the word at that address.
• A byte at a halfword-aligned address is the most significant byte within the halfword at
that address.
Example: 0x12345678
0x0000 12(MSB)
0x0004 34
0x0008 56
0x000C 78(MSB)

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 Lecture Notes | BCS402 – MC Module 2

Dept of CSE and Comp.Eng,CBIT,Kolar

 Lecture Notes | BCS402 – MC Module 2

register r0

Dept of CSE and Comp.Eng,CBIT,Kolar