ARM instruction set

Instruction : An instruction is a command given to the processor to perform a specific operation

on specified data. Each instruction has 2- parts:
Instruction
OPCODE OPERAND

Opcode  the operation to be performed

Operand  the data to be operated

 Instruction set of a processor gives information about the instructions, addressing modes and
the timing requirement for the execution of each instruction.

ARM architecture has two instruction sets - The ARM instruction set and Thumb instruction set.
 In ARM instruction set, all instructions are 32 bits wide and are aligned at 4-bytes
boundaries in memory.
 On the other hand, in thumb instruction set, all instructions are of 16 bits wide and are
aligned at even or two bytes boundaries in memory.

Early ARM instruction set

 32-bit instruction set, called the ARM instructions
 Powerful and High performance
 Larger program memory
 Larger power consumption

ARM Instructions can be categorized into following classes :

1. Data Movement instructions.

2. Data Processing Instructions
(a) Arithmetic Instructions
(b) Logic Instructions
(c) Comparison Instructions
(d) Shift instructions
3. Branch Instructions
4. Load and store Instructions
(a) Load and Store register instruction
(b) Load and Store multiple register instructions
(c) Stack instructions
(d) Swap register and memory content
1. Data Movement instructions:

Instruction Operation Example

MOV R0, R1
MOV Move a 32-bit value into a register
R0  R1
MVN R0, R1
MVN Move the NOT of the 32-bit value into a register
R0  NOT R1
Move top MOVT R0, #0x1234
MOVT Writes 16-bit immediate value to Top-half word of a
R0(31:16)  1234
register, without affecting the bottom half-word.

2. Data Processing instructions:

(a) Arithmetic Instructions:

Instruction Operation Example

ADD R0, R1,R2
ADD Add two 32-bit values
R0  R1+R2
ADC R0, R1,R2
ADC Add two 32-bit values with carry
R0  R1+R2+C
SUB R0, R1,R2
SUB Subtract two 32-bit values
R0  R1-R2
MUL R0, R1,R2
MUL Multiply
R0  R1*R2
MLA R0, R1,R2
MLA Multiply and Accumulate R0  R0 +
R1*R2

(b) Logical Instructions :

Instruction Operation Example

Performs bitwise Logic AND operation of AND R0, R1,R2

AND
two 32-bit values R0  R1 AND R2

Performs bitwise Logic OR operation of ORR R0, R1,R2

ORR
two 32-bit values R0  R1 OR R2

Performs bitwise Logic Ex-OR operation of EOR R0, R1,R2

EOR
two 32-bit values R0  R1 XOR R2
Logical Bit Clear BIC R0, R1,R2
It is used to clear the selected bits in a Register
BIC R0  R1 AND (NOT
It Performs bitwise Logic AND operation of Register
R2)
with Complement of Operand2
(c) Comparison Instructions :

Instruction Operation Example

Compare Register with Operand2 CMP R1, R2

Performs R1-R2
CMP Only flags are affected
It performs Subtraction operation, but the result is not
stored anywhere. If R1>R2 : C=0, Z=0
If R1<R2 : C=1, Z=0
Only flags are affected.
If R1=R2 : C=0, Z=1

Compare Negative CMN R1, R2

CMN Compare Register with Negative of Operand2 Performs R1 - (NEG

R2)
Only flags are affected.
Only flags are affected
Test for EQUALITY of bits
TEQ R1, R2
It performs bitwise Logic Ex-OR operation of Register
and Operand2, but the result is not stored anywhere.
TEQ
Only flags are affected. Performs R1 XOR R2
It is used to Test, if two values are equal or not, without Only flags are affected
affecting V and C flags
(d) Shift Instructions:

Instruction Operation Example

Logical Shift Left LSL R0, R1, #1

LSL R0, R1, R2
LSL
R0  destination
R1  source
R2  No. of bits
to be shifted

Logical Shift Right

LSR R0, R1, #1
LSR
LSR R0, R1, R2

Rotate Right

ROR R0, R1, #1

ROR
ROR R0, R1, R2
3. Branch instructions:

Instruction Operation Example

Branch B Label
B
(Unconditional jump to specified location) Branch to ‘Label’

Branch and exchange BX Label

BX (Branch to specified location and change the Branch to ‘Label’ and
processor state from ARM to Thumb) change processor state

4. Load and Store instructions :

(a) Load and Store register instructions :

Instruction Operation Example

LDR R1, [R2]

LDR Load Register from memory
R1  [R2]

STR R1, [R2]

STR Store Register to memory
R1  [R2]

LDRH R1, [R2]

LDRH Load 16-bit half-word from memory
R1(15:0)  [R2]

LDRSH R1, [R2]

LDRSH Load signed 16-bit half-word from memory
R1(15:0)  [R2]

LDRH R1, [R2]

LDRB Load 8-bit byte from memory
R1(7:0)  [R2]

LDRSB R1, [R2]

LDRSB Load signed 8-bit byte from memory
R1(7:0)  [R2]

(b) Load and Store multiple register instructions :

Instruction Operation Example

LDM R0 !, {R4-R11}
LDM Load multiple Registers from memory Load 8-registers R4 to R11
from memory pointed by R0

STM R0 !, {R4-R11}
STM Store multiple Registers to memory Store 8-registers R4 to R11
to memory pointed by R0
 (c) Stack instructions:

Instruction Operation Example

PUSH R4
Push R4 onto stack
PUSH Push registers onto stack PUSH {R4-R11}
Push registers R4 to R11
onto stack

POP R4
Pop R4 from stack
POP Pop registers from stack POP {R4-R11}
Pop registers R4 to R11
from stack

(d) Swap instructions :

Instruction Operation Example

Swap a 32-bit word between Registers and SWP R0, R1, [R2]
SWP
Memory [R2]  R1
R0  [R2]

SWPB Swap a byte between Registers and Memory SWPB R0, R1, [R2]