Mosfet Theory

February 28, 2025

 Outline
 Semiconductor structure
▪ Physical structure
▪ Channel formation
 Mosfet characteristics
▪ I-V relation
▪ Mos resistance
▪ Mos capacitance
▪ Leakage current
▪ Saturation current
▪ Threshold voltage
 Short-channel devices
▪ Velocity saturation effect
▪ Threshold voltage variation
▪ Hot carrier effect
 Deal with cmos inverter
▪ Define the trippoint
▪ Switching interval
▪ Low to high time
▪ High to low time
▪ Power dissipation

2
Semiconductor structure

3
 Physical structure

vS vG vD polysilicon
vS vG < 0
iG iD v <0
iS i D
Gate (G) iS G Gate iD
Source (S) Drain (D) Drain
Source

n+ Channel Region n+ p+ Channel Region p+

Isulating layer
L SiO2
L

P-Type Substrate n-type substrate

Body (B) Body

i vB > 0
iB B
vB

MOSFET - Current through the channel region is controlled with voltage Vg

4
 Channel formation

Depletion region

Vds=Vgs-Vtn
V(x) = Vgs-Vtn
Id
Vtn Vgs-Vtn = 0

Vd Vs,0

Vg

5
 Mosfet Region
Example of water analogy

6
 I-V relation

❖ Cut_off region

❖ Triode region

❖ Saturation region

Cut_off
Channel modulation factor
7
 v DS
i DS   n (vGS  VTN  )v DS
2

Summary of MOS equations

8
 Mosfet resistance

9
 Mosfet capacitance

Nmos device in cut off Gate

Source Drain
CGS  COL
'
W
CGD  COL
'
W
C' C'OL
OL

Overlaping capacitance
n+ n+
C
GB
CSB C DB

p-type substrate Depletion region

NMOS device in cutoff

Bulk

10
 Mosfet capacitance

Nmos device in the linear region

Source Gate Drain

CGC  C WL
''
ox

CGS  CGD  C WL / 2  C W
''
Ox
'
OL C' C" C" C'
OL OX OX OL

n+ n+

C n-type channel C
SB DB

p-type
substrate
NMOS device in
the linear region Bulk

11
 Mosfet capacitance

Gate
Nmos device in saturation Source Drain

2 ''
CGS  COL
'
W Cox ( WL )
3
C' C" C" C'
CGD  C W
'
OL
OL OX OX OL

n+ n+
C n-type channel C
SB DB

p-type substrate

NMOS device in saturation

Bulk

12
 Leakage current

❖ Three main sources for leakage current

❖ Source/Drain junction leakage. This
dues to inversed bias p-n junction.
❖ Gate direct tunneling leakage
❖ Sub-threshold leakage through the
channel of OFF transistor. This origins
from minority carriers

Largest leakage

13
 Leakage current

VD = 0 ÷ vsup

Vb= 0
VG = 0

VS = 0

NMOS

.measure dc ileak_nmos find i(mn)

when v(D) = vsup

Leakage current increases when Vds goes up

as a result of gaining subthreshold leakage

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 Saturation current

v(xpo) = vgs - Vtn

0 xpo L

VD = 0 ÷ vsup

VG = 1;1.2; 1.4; VS = 0
1.6;1.8;2.0
NMOS

.measure dc idsat_nmos find i(mn)

when v(D) = vsup
Idsat increases when Vgs goes up
15
 Threshold voltage

.measure dc vth_nmos find lv9(mn)

when v(B) = 0

With available technology, threshold voltage will

increases when Vsb goes up

16
 Short-channel devices

❖ As the technology scaling reaches channel

lengths less than a micron (L<1µ), second Gate Oxyde
order effects, that were ignored in devices Gate
with long channel length (L>1µ), become Polysilicon Field-Oxyde
Source Drain
very important. (SiO2)
n+ n+
❖ MOSFET‘s owning those dimensions are
called „short channel devices“.
p+ stopper
p-substrate
❖ The main second order effects are: Velocity
Saturation, Threshold Voltage Variations
and Hot Carrier Effects.
Bulk Contact

CROSS-SECTION of NMOS Transistor

17
 Velocity saturation effect

ID
W  V 
2
I D   VDS  nCOX VGS  VT VDS 
DS

L  2 
VGS=VDD Long-channel
1 device
 VDS  
1  VDS  C L 

Short-channel
For large values of L or small values of device
VDS,  approaches 1.
For short channel devices <1 and the
current is smaller than what would
be expected.
VDS
VDSAT VGS-VT
Short channel devices display an extended
saturation region due to velocity-saturation

18
 Velocity saturation effect

❖ I-V characteristics of long- and short-channel MOS transistors both with W/L=1.5

19
 Velocity saturation effect

❖ ID-VGS characteristic for long- and short channel devices both with W/L=1.5

20
 Threshold voltage variations

For a long channel N-MOS transistor the threshold Voltage is given for:

VT  VT 0     2 F  VSB   2 F 
The threshold Voltage is only a function of the technology and applied body bias Vsb
For short channel devices this model becomes inaccurate and threshold voltage
becomes function of L, W and VDS.
VT
VT
Long-channel threshold
Low V DS threshold

L Vds
Threshold as a function of the length Drain-induced barrier lowering
(for low Vds) (for low L)

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 Hot carrier effects

❖ During the last decades transistors dimensions were scaled

down, but not the power supply.
❖ The resulting increase in the electric field strength causes an
increasing energy of the electrons.
❖ Some electrons are able to leave the silicon and tunnel into the
gate oxide.
❖ Such electrons are called „Hot carriers“.
❖ Electrons trapped in the oxide change the VT of the transistors.
❖ This leads to a long term reliabilty problem.
❖ For an electron to become hot an electric field of 104 V/cm is
necessary.
❖ This condition is easily met with channel lengths below 1µm.

22
 Deal with cmos inverter

❖ Define the trippoint

❖ Trippoint is the point that the
input voltage reachs the output
one.
❖ Why should the trippoint be
defined
❖ The trippoint will make the
operation wrong.
❖ How to control the trippoint
❖ To increase the trippoint, the
pmos is set to conduct stronger
than nmos.
❖ To decrease the trippoint, the
pmos is set to conduct weaker
then nmos

23
 Deal with cmos inverter

❖ Switching intervals

24
 Deal with cmos inverter

❖ High to low transition

MN goes from Cutoff over Saturation into Nonsaturation region
for the given input.
The border between Saturation and Nonsaturation is reached at
the time tx and the output voltage Vout = VOH - VTn v
I

+ 5V
V DD= 5 V

MP 0V t
v
v I = 5V v O(0+) = 5V 0 O

MN saturated
MN C VOH = 5V

MN nonsaturated
(Vin - VTn)

VOL = 0 V t

t1 tX t2

25
 Deal with cmos inverter

❖ High to low transition

In order to simplify the final

expressions, the
integrations on the right for
computing tHL are done
with the borders from V1 to
V0
(V1 = 0,9 VDD
V0 = 0,1 VDD)

dQ dVOUT
i  COUT
dt dt
dVOUT
 dt  COUT  i
26
 Deal with cmos inverter

❖ Low to high time

From symmetry (VTn VTp; Kn Kp) follows for the high to low transition time:

v
I
V =5V
DD
+ 5V

MP
0V t

V =0V
I O
v O (0+) = 0V
+ 5V
M C
N

0V t
0

27
 Deal with cmos inverter

❖ Maximum switching frequency

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 Power dissipation

❖ Two kinds of power dissipation in digital electronics:

❖ static power dissipation (logic gate output is stable)

❖ dynamic power dissipation (during switching of logic gate)

❖ With CMOS nearly no static power dissipation!

29
 Dynamic Power Dissipation

❖ Power dissipation due to charge and discharge of capacitance.

❖ The total energy ETD dissipated in the process of first charging and then
discharging the capacitor is equal to

 CV DD
2
  CV DD
2

ETD      
 2  Charge  2  Discharge
 CV DD
2

❖ Every time a logic gate goes through a complete switching cycle, the transistors
within the gate dissipate an energy equal to ETD. Logic gates normally switch
states at some relatively high frequency (switching events/second), and the
dynamic power PD dissipated by the logic gate is then

PD  CV DD
2
f

30
 Dynamic Power Dissipation

❖ Power dissipation due to the “short circuit current” (when both

transistors are on during transition)
❖ The short circuit current reaches a peak for Vin = Vout = VDD/2

5.0 V VDD = 5 V
vO
Voltag

R onp
Vin = Vout = VDD/2
vI
e

0.0 V
vout
30uA
i DD
Current

R onn
0 uA
0s 4ns 8ns 12ns 16ns
Time

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