Fundamentals of MOS Devices

Yu-Te Liao
Department of Electrical and Computer
Engineering
National Chiao Tung University

1
 Outline
 Present intuitive understanding of device operation
 Introduction of models for manual analysis
 Analysis of secondary and deep-sub-micron effects
 Future trends of transistors

(Chapter 3)

2
 Diode

B Al A
SiO 2

Cross-section of pn-junction in an IC process

A Al

p A

B B
One-dimensional
representation diode symbol

3
 P-N junction Diode
 Equilibrium: ID=IS  Conductance current:
- E+  drift current
 diffusion current

Holes Electrons  Depletion Region: No

Bound charges free charge, only
ID
IS immobile charges
(Diffusion) (drift)
2𝜀𝜀𝑠𝑠 1 1
𝑊𝑊𝑑𝑑𝑑𝑑𝑑𝑑 = 𝑋𝑋𝑋𝑋 + 𝑋𝑋𝑋𝑋 = + 𝑉𝑉
𝑞𝑞 𝑁𝑁𝐴𝐴 𝑁𝑁𝐷𝐷 𝑜𝑜
xn NA
Potential ≅ 𝑁𝑁𝐴𝐴𝑁𝑁𝐷𝐷
xp ND 𝑉𝑉𝑜𝑜 = 𝑉𝑉𝑇𝑇𝑙𝑙𝑙𝑙( 2 )
𝑛𝑛𝑖𝑖
VO Barrier voltage VT =
KT
q
Link to the page
Distance 4
Fundamentals of Diode

5
 PN Junction Under Bias
 Forward bias: applied positive potentials to P and
negative potentials to N, which increases electrical
field and diffusion current as well as lower barrier
voltage
 Reverse bias:

6
 I-V Curve of a Diode
 𝐼𝐼𝐷𝐷 = 𝐼𝐼𝑆𝑆 𝑒𝑒 𝑉𝑉𝐷𝐷 /𝑉𝑉𝑇𝑇 − 1 ID
𝑘𝑘𝑘𝑘
 𝑉𝑉𝑇𝑇 = = 26𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚
𝑞𝑞
Reverse current

VD0~0.7V VD
Forward current
Breakdown
current

 Reverse leakage current (three orders higher than

saturation current (Is) of 10-17A /µm2) can dominate
the low power digital circuit design in the submicron
process .
7
 Depletion-region Capacitance

 The forward bias voltage reduces the potential barrier  less space
charge and less depletion width
 The reverse bias voltage increases the potential barrier  more space
charge and larger depletion width
𝑁𝑁𝐴𝐴 𝑁𝑁𝐷𝐷
 Qj= 𝐴𝐴𝐷𝐷 2𝜀𝜀𝑠𝑠𝑠𝑠 𝑞𝑞 𝜑𝜑0 − 𝑉𝑉𝐷𝐷
𝑁𝑁𝐴𝐴 +𝑁𝑁𝐷𝐷

𝑑𝑑𝑄𝑄𝑗𝑗 𝜀𝜀𝑠𝑠𝑠𝑠 𝑞𝑞 𝑁𝑁𝐴𝐴 𝑁𝑁𝐷𝐷 −1 𝐶𝐶𝑗𝑗𝑗

 𝐶𝐶𝑗𝑗 = = 𝐴𝐴𝐷𝐷 𝜑𝜑0 − 𝑉𝑉𝐷𝐷 =
𝑑𝑑𝑉𝑉𝐷𝐷 2 𝑁𝑁𝐴𝐴 +𝑁𝑁𝐷𝐷 𝑉𝑉
1− 𝐷𝐷
𝜑𝜑0
𝑁𝑁𝐴𝐴 𝑁𝑁𝐷𝐷
 𝜑𝜑0 = 𝑉𝑉𝑇𝑇 ln( ) ni = 1.5 x1010 cm-3 for silicon
𝑛𝑛𝑖𝑖 2
𝐶𝐶𝑗𝑗𝑗
 𝐶𝐶𝑗𝑗 = 𝑉𝑉 𝑚𝑚
(m =1/2 for abrupt junction (forward bias), m =1/3 linear
1− 𝜑𝜑𝐷𝐷
0
junction(reverse bias)
8
 Circuit Model
 Rs is about 1-100 Ω ( model the voltage drops in
the neutral zone)

9
 Diode Temperature Effects
 𝐼𝐼𝐷𝐷 = 𝐼𝐼𝑆𝑆 𝑒𝑒 𝑉𝑉𝐷𝐷 /𝑉𝑉𝑇𝑇 − 1
𝑘𝑘𝑘𝑘
 The thermal voltage (𝑉𝑉𝑇𝑇 = ), which is linearly
𝑞𝑞
dependent on the temperature.
 The saturation current Is is also temperature
dependent because the thermal equilibrium carrier
concentrations increase with increasing
temperature. Saturation current doubles every 5oC.
The reversed current doubles every 8oC.

10
 MOSFET
 Metal-Oxide Semiconductor Field Effect Transistor
(MOSFET)
 Voltage-Control current source

11
 MOSFET Technology
 MOSFET transistor - Lilienfeld (Canada) in 1925
 CMOS – 1960’s, but plagued with manufacturing problems
 PMOS in 1960’s (calculators)
 NMOS in 1970’s (4004, 8080) – for speed
 CMOS in 1980’s – preferred MOSFET technology because
of power benefits
 BiCMOS, Gallium-Arsenide, Silicon-Germanium
 Silicon on insulator (SOI), Copper-Low K, …

12
 MOSFET Physical Structure
 Key elements:
 inversion under gate (depend on gate voltage)
 heavily doped regions reach underneath gate
electrically connect source and drain
 4 terminal device: body voltage is important

13
 CMOS
 Complementary metal–oxide–semiconductor
(CMOS): NMOS+PMOS

NMOS PMOS
14
 Concept of Threshold Voltage (Vth)
 A positive gate voltage causes negative charges to
accumulate on the gate. Thus, a depletion layer is
formed. (NMOS)
 After certain voltage (Vth), the depletion layer
inverts to n-type. (Connect source and drain)

15
 Body Effect
 The threshold voltage changes with the substrate
potential (Think about the diode characteristics)
 𝑉𝑉𝑇𝑇 = 𝑉𝑉𝑇𝑇𝑇 + 𝛾𝛾( −2𝜑𝜑𝐹𝐹 ± 𝑉𝑉𝑆𝑆𝑆𝑆 − 2𝜑𝜑𝐹𝐹 ) (+:PMOS -
:NMOS)
− Large reverse voltage high barrier potential hard to
inverse the channel
− Why connect the body (NMOS) to gnd and (PMOS) to
vdd?

16
 MOS Operation Regions
 VGS < Vth OFF
 VGS > Vth VGD < Vth Saturation region
1 𝑊𝑊
− 𝐼𝐼𝐷𝐷 = 𝜇𝜇 𝐶𝐶 (𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 )2
2 0 𝑂𝑂𝑂𝑂 𝐿𝐿
 VGS > Vth VGD > Vth Triode region
𝑊𝑊 1 2
− 𝐼𝐼𝐷𝐷 = 𝜇𝜇0 𝐶𝐶𝑂𝑂𝑂𝑂 ( 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝐷𝐷𝐷𝐷 )
𝐿𝐿 2

OFF Triode Saturation

17
 I-V Curve
 Plot the current equations

18
 Design Parameters
𝑊𝑊 1 2
 𝐼𝐼𝐷𝐷 = 𝜇𝜇0 𝐶𝐶𝑂𝑂𝑂𝑂 ( 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝐷𝐷𝐷𝐷 )
𝐿𝐿 2

 Weff and Leff : geometric parameters

 VGS, VDS, VBS and Vth : voltage parameters

µ 、Ԑox、tox : process parameters

19
Concept of Channel Length Modulation
 The effective length of a transistor is modulated by
VDS : increase VDS, depletion region at the drain
junction increases, means the length of effective
channel reduces.

20
 Channel Length Modulation
 𝐼𝐼𝐷𝐷 = 𝐼𝐼𝐷𝐷′ 1 + 𝜆𝜆𝑉𝑉𝐷𝐷𝐷𝐷 =
1 𝑊𝑊
𝜇𝜇0 𝐶𝐶𝑂𝑂𝑂𝑂 (𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 )2 1 + 𝜆𝜆𝑉𝑉𝐷𝐷𝐷𝐷
2 𝐿𝐿
 λ is proportional to the inverse of the channel length
 Lower Vgs bias, smaller λ, higher Ro

21
 Summary of MOS Operation
 Strong Inversion VGS > VTH
− Linear (Resistive) VDS < VDSAT
− Saturated (Constant Current) VDS ≥ VDSAT
 Weak Inversion VGS <VTH
− Like a BJT (will talk about it later)
 Off state VGS = 0
− Only leakage current
 Body effect and channel length modulation
 𝑉𝑉𝑇𝑇 = 𝑉𝑉𝑇𝑇𝑇 + 𝛾𝛾( −2𝜑𝜑𝐹𝐹 ± 𝑉𝑉𝑆𝑆𝑆𝑆 − 2𝜑𝜑𝐹𝐹 )
 𝐼𝐼𝐷𝐷 = 𝐼𝐼𝐷𝐷 ′(1 + 𝜆𝜆𝑉𝑉𝐷𝐷𝐷𝐷 )

22
 Subthreshold Region
 Week inversion region (VGS ≤ VTH) : current does not
drop to zero.
 ID decays exponentially as VGS decreases. (BJT)
𝑉𝑉𝐺𝐺𝐺𝐺 𝑉𝑉
𝐷𝐷𝐷𝐷
𝑛𝑛𝑛𝑛𝑛𝑛 − 𝐾𝐾𝐾𝐾
 𝐼𝐼𝐷𝐷 = 𝐼𝐼𝑆𝑆 𝑒𝑒 𝑞𝑞 (1 − 𝑒𝑒 𝑞𝑞 )(1 + 𝜆𝜆𝑉𝑉𝐷𝐷𝐷𝐷 )

23
 Summary of MOS Operation
 Strong Inversion VGS > VT
− Linear (Resistive) VDS < VDSAT
− Saturated (Constant Current) VDS ≥ VDSAT
 Weak Inversion (Sub-Threshold) VGS ≤ VT
− Exponential in VGS with linear VDS dependence
 Off state

 Body effect and channel length modulation

24
 Intrinsic Gain
 Intrinsic gain: gm x ro (maximum AC gain of a transistor)
 What is gm ?
∂I D
gm = = µ n Cox
W
(VGS − VTH ) = 2I D
= 2 KI D
∂VGS L Vov

 What is ro ?

1 ∂I D ID
= =
ro ∂VDS V A
 Why transistors need to be in Saturation region for
“linear amplification” ?
25
 Small Signal Model
 Π model: used when source terminal is grounded
 T model: used when source terminal is loaded

With Body effect

26
 Advanced MOSFET Modeling
 MOS transistor model: parasitics
− Capacitance
− Resistance
− BJT
 Secondary effects in submicron devices
− Velocity saturation
− Vth variation
 Beyond transistor scaling

27
CMOS Cross Section

28
 High Frequency Model
Polysilicon

Gate Gate
Aluminum Source/Drain Source/Drain Source/Drain Source/Drain
Body Body

P+ N+ N+ N+ P+ P+

Nwell
P- Substrate

Rg
Cgs Cgd

Rs Rd
S D
Cgb
Csb Cdb
Rb Rb

B
29
 Gate Capacitance
 Cgate = Cgs + Cgd + Cgb
Polysilicon gate

Source Drain
W
n+ xd xd n+

Gate-bulk
Ld overlap
Top view
Gate oxide
tox
n+ L n+

Cross section
30
 Gate Capacitance in Different Region

Operation region CGB CGD CGS CG,tot

Cut-off CoxWL CovWxd Cov Wxd 2CovWxd + CoxWL

Triode 0 ½ CoxWL + ½ CoxWL + 2 CovWxd + CoxWL

CovWxd CovWxd
Saturation 0 Cov Wxd 2/3 CoxWL + 2 CovW xd+ 2/3
CovWxd CoxWL
31
 Summary of Gate Capacitance
 When a transistor turns on, the capacitance
depends on the VDS/(VGS-VTH) ratio
 Total gate capacitance decreases as the saturation
level increases.
 A large fluctuation of channel capacitance when a
transistor is biased at VGS=VTH
CG C
WLC ox WLC ox
CG C
2WLC ox
CG CS 3
WLC ox C G CS = CG CD
WLC ox CGC B
2 CGCD 2

0 VDS /(VG S-VT) 1 VG S

with VDS=0 32
 Junction Capacitance
 Contributed by the reverse-biased source-body and
drain-body PN-junction

𝐶𝐶𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 = 𝐶𝐶𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏 + 𝐶𝐶𝑆𝑆𝑆𝑆

= 𝐶𝐶𝑗𝑗 × 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐶𝐶𝑗𝑗𝑗𝑗𝑗𝑗 × 𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃
= 𝐶𝐶𝑗𝑗 × 𝐿𝐿𝑆𝑆 × 𝑊𝑊 + 𝐶𝐶𝑗𝑗𝑗𝑗𝑗𝑗 × (2𝐿𝐿𝑆𝑆 + 𝑊𝑊)

Side wall
W
Source
Bottom

xj Side wall
Channel
LS Substrate 33
 Source/Drain Resistance
 Reduce drain current for a given gate voltage
𝐿𝐿𝑆𝑆,𝐷𝐷
 𝑅𝑅𝑆𝑆,𝐷𝐷 = 𝑅𝑅⊡ + 𝑅𝑅𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐
𝑊𝑊
 𝑅𝑅⊡ ~20 − 100Ω/⊡
 Silicidation process and large width transistor

34
 Short Channel Effect: Velocity Saturation
 The mobility/velocity of carriers does not depend on the
electrical field (saturated) due to the frequent collisions of
carriers (too crowded). (Strong lateral electrical field) (short
channel)

1
I DSAT = CoxW (VGS − VT ) Esat
2

∂I DSAT µCoxW
gm = |VGS =vgs = Esat
∂VGS 2
35
 Velocity Saturation
 IDS becomes linearly proportional to VGS
 Short channel devices experience an extended
saturation region (Reduce linear/triode region)
 The drain current eventually ceases to depend on
the channel length
 gm reduction
 The velocity saturation effects in PMOS is less
pronounced since holes (major carriers in the
channel) needs high electrical field to drive.

36
 Reduced Output Impedance
 Drain-induced Barrier lowering (DIBL):
Lower VTH as VDS is increased  reduce ro
(VTH not only depends on the size but also the VDS)
 Hot Carriers Effect
High-velocity carrier causes currents to flow from the
drain to the substrate ( a finite drain to ground
resistance)

37
I-V Curve of Short Channel MOSFET

38
ID vs. VGS

39
 CMOS Latchup
 Short Vdd and ground through parasitic BJTs in the
CMOS process  burn the IC
 To avoid latchup, Rnwell and Rpsub should be
minimized.
 Place substrate and well contacts as many as you
can. V DD

VDD GND Rnwell

Gate Gate Source/Drain
Source/Drain Source/Drain Source/Drain M1
Body Body

P+ P+ P+
N+ Rpsub N+ N+ M2
Rnwell Nwell
M1 Rpsub
M2
P- Substrate

40
 Secondary Effects: Vth Variations
 VTH is a function of length, width, and VDS
 Scaling effect: Vth decreases with length decrease
 Drain-induced barrier lowering (DIBL): high VDS may
short the drain and source or punch through VTH
decreases with VDS increase (Leff reduces)
 Narrow channel effects: the channel depletion region
can extend to the source/drain  VTH increase
(pronounced in transistors with small width)
 Hot carrier effects: short channel length causes high
electrical field  electrons leave the silicon and tunnel
into the gate oxide  increase VTH in NMOS but
decrease VTH in PMOS
41
 Threshold Variations

VT VT

Long-channel
threshold

L VDS
Threshold as a function of Drain-induced barrier lowering
the length (for low VDS) (for low VDS)

42
 Process Variations
 Impurity densities, oxide thickness, diffusion depth,
etc.
 Vth variations ~ tens mV
 width and length variation depends on the
minimum resolution of the photolithographic
process
 Process parameters in simulation
− TT: typical NMOS -typical PMOS condition
− FF: fast-fast
− SS: slow-slow
− SF: slow-fast ……

43
Technology Scaling

44
 Transistor Perspectives
 Transistors go 3D

Extending channel vertically may save surface area

45
 Fin FET
 Invented by Chenming Hu, UC-berkeley
 The thickness of the fin (measured in the direction
from source to drain) determines the effective
channel length of the device.
 Gate delay of just 0.39 ps for the N-type transistor
and 0.88 ps for the P-type

46
3D IC

Source : Infineon 47
 Conclusion
 MOS transistor operation regions
− Saturation, triode ,off, subthreshold
 Two effects: body effect and channel length
modulation
 MOS capacitance and parasitics
 Secondary effects due to transistor scaling
− Vt variation
− Velocity saturation
 Next lecture: CMOS fabrication process
(Chapter 2)

48
 Questions
 Any other circuits can be build by diodes?
 How to build ESD circuit using diodes?
 What parameters may affect VTH in short-channel
transistors? (Size, VDS,…..)
 How to use transistors as variable resistor and
capacitor?
 Explain leakage current in CMOS circuits

49