Optimization of Patch Antennas

Authored by:
Tony Donisi
Ansoft Corporation

Ansoft 2003 / Global Seminars: Delivering Performance

Presentation #10
Slide 1
 Introduction
Goal: To introduce a more effective and streamlined design flow for
systems with patch antennas that leverage Parameterization, Solver-On-
Demand and Co-Simulation

Overview
Single Patch Element Design
Linear Patch Array
Corporate Fed Patch Array
System and Circuit Integration
Conclusion

Slide 2
 Designer Capability Overview
Designer can accurately simulate very large structures, quickly!
SVD fastsolve
Low memory requirements
Geometries can be drawn or imported
User friendly GUI
Dxf, iges, and popular geometry imports
Ansoft Links for Allegro and other CAD tools
Full Parameterization
Solver on Demand
The ability of designer that lets the user decide which solver to use on an element by
element basis
Co-Simulation
The capability of designer to seamlessly integrate circuit, system and EM simulations

Slide 3
 Single Patch Design
Designer allows easy design of single patches
Patch estimator tool gives a good first approximation
Fully parameterized single patch will be created
Solution for a range of geometries
Patch characteristics will be plotted
Functions of geometry, Frequency
Current and field distributions
Plots can be animated
Real time tuning
Both 2D and 3D plotting available

Slide 4
 Patch Estimator Tool
Integral patch estimator tool

Slide 5
 Single Patch: Recessed feed
1 π
Rin = Cos2 ( L slot )
2(G1 ± G12 ) LPatch

π 2
 Sin(k 0 WpatchCosθ ) 
∫0  Cosθ 

Sin3θdθ
WPatch G1 =
120π 2

2
1
π
 Sin(k 0 Wpatch Cosθ ) 
2 ∫
G12 =  J0 (k 0Lpatch Sinθ )Sin θdθ
3

120π 0  Cosθ 
LPatch Wf1

WSlot

LSlot

Lfeed
Wfeed

ThisPatch
This Patchcan
canbe
beused
usedas
aseither
eitheraafull
full
Zin planarEM
planar EMmodel
modelor
oraa“Solver
“Solveronon
Demand”component
Demand” component

Slide 6
 Single Patch Design Procedure
Use Patch Estimator to get starting point
10mil Duroid 5880
Frequency 10GHz
Resulting Width and length 393 mil
Also gives a starting point for Lslot
Nominal patch frequency response
Lslot and Wslot will have minimal effect on
center frequency
Adjust Wpatch if necessary
Vary Lslot and Wslot to get Best VSWR
Assume 100Ω
Lslot from 10mil to 100 mil
Wslot from 30mil to 150mil
Edge meshed to concentrate at Edges

Slide 7
 Single Patch Frequency Sweep

SweepofofFrequency
Frequency
Sweep
and LSlot. Note
and LSlot. Note
Frequencyresponse
responseisis
Frequency
not centered atat10GHz
not centered 10GHz

SweepofofFrequency
Frequencyandand
Sweep
Wpatch. As the
Wpatch. As the
frequencyincreases,
increases,itit
frequency
is obvious thatLSlot
LSlotwill
will
is obvious that
needfurther
furtheradjustment
adjustment
need

Slide 8
 Single Patch Optimization

Designer allows the user

to optimize with respect to
any variable, Including
field quantities.

Slide 9
 Single Patch Parameter Results
Smithplot
Smith plotofofinput
inputMatch
MatchVersus
VersusSlot
Slot
widthand
width andlength.
length.

OptimalMatch
Match
Optimal
(100Ω)atat
(100Ω)
Wslot==50mil
50mil
Wslot
Lslot=127mil
Lslot=127mil

Slide 10
 Single Patch Scalar Return Loss

Parametricsweep
Parametric sweepof
ofreturn
returnloss
loss
withrespect
with respectto
toWslot
Wslotand
andLslot
Lslot

Slide 11
 Single Patch Real Time Tuning

Slide 12
 Single Patch Far Field & Near Field

Slide 13
 Patch Arrays
Patches can be arranged various Arrays
Two examples will be shown
“Linear” array
Both x- and y- patches variable
Corporate Array
Arrays will be built with previous patches
100Ω impedance
Feed networks will be considered
Feeds have impact on antenna performance
Many, many feed designs

Slide 14
 Patch Array Feed Networks
Co-linear feed network
Straightforward Extension to other feed
styles Patch
Patch Patch
Patch
Vias
Designer has no restrictions on vias
This presentation will not take into effect
vias
Vias and feeds on other layers are Matching Matching
Matching
simple to add Matching

Input

Patch
Patch Patch
Patch Patch
Patch
(100Ω)
(100Ω) (100Ω)
(100Ω) (100Ω)
(100Ω)

λ/4
λ/4 λ/4
λ/4
100Ω Line
100Ω Line Transformer 100Ω Line
100Ω Line Transformer
Transformer
Transformer

Input

Slide 15
 Linear Array
“Patch” antenna with feed
Patch dimensions as previously outlined
Quarter wave transformers
The number of patches can be large
nx Set as “number of x-dimension” Patches
ny Set as “number of x-dimension” Patches

Quarter Wave
transformer sections.
Width and length
parameterized for user
optimization
dx
Lf1
dy

W01

Lf1

Lambda4

Slide 16
 Analysis Overview
One structure can represent
Circuit
Planar EM
Circuit provides quick analysis
Match and VSWR information
Planar EM provides
Fields
Full match and VSWR information
Near field and far field information
Current Distributions
A sample patch array is built to utilize:
Solver on demand
Equivalent Circuit modeling
Full parameterization
Parameter passing

Slide 17
 Component Description
The Patch Array will consist
of:
Component
Represents the overall patch
Contains parameters, circuit
equivalent
Footprint
Contains geometry information
Can be scripted in VB or Java
Full script of patch can be found in
appendix
Symbol
Schematic representation of patch
Circuit equivalent

Slide 18
 Design Procedure
1. Determine Geometry and parameters
2. Create parameterized footprint
Standard drawing of polygons or shapes
VBscript or JavaScript
3. Create circuit equivalent
4. Create symbol
5. Generate component
6. Optional: Create circuit equivalent

Once this
Once this isis done
done the
the user
user has
has aa flexible
flexible “Solver
“Solver on
on
Demand” component
Demand” component that
that can
can be
be used
used asas aa versatile
versatile
“stand alone”
“stand alone” design
design or
or as
as part
part of
of aa larger
larger scale
scale circuit
circuit
orsystem
or systemdesign.
design.

Slide 19
 Patch Array Design
One row, nx = 4 (4 elements) nominal
Same “patch” as previously designed
10mil, ε2.2 RT Duroid
50Ω, 8 mil, 70.7Ω, 17mil, 50Ω, 30mil
Contains parameters, circuit equivalent
λ/4 = 218 mil
The spacing between elements is important
“Orthogonal” pattern
Normal to x-y plane Feeding the patches
Patch elements must be fed in phase in phase will make the
pattern orthogonal to
the x-y plane. This
will occur when the
separation is an
integral multiple of a
wavelength

Slide 20
 Performance Plots

ReturnLoss
Return Loss

N=4,dx=
N=4, dx=600mil
600mil
GainVs
Gain Vsdx
dx Nominal
Nominal
Slide 21
 Swept Plots
Effect ofof varying
varying “dx”
“dx” on
on the
the 3D
3D gain
gain pattern,
pattern,
Effect
from 500mil to 1200mil. The optimal
from 500mil to 1200mil. The optimal
gain/directionoccurs
occursbetween
between800mil
800miland
and100mil
100mil
gain/direction

Effectofofvarying
varying“dx”
“dx”versus
versusfrequency
frequency
Effect

Slide 22
 4-Element Phased Array
Previously designed recessed patch
Array of 4 elements
Fully parameterized
Input Phase and amplitude can be set to
variables
These can be modified to observe field patterns

Designerallows
Designer allowsthe
theuser
user
tofeed
to feedthe
theports
portswith
with
differentphases
different phasesandand
amplitudes. These
amplitudes. Thesecan
can
beset
be setto
tovariables
variablestoto
allowfor
allow forany
anydesired
desiredfeed
feed
pattern
pattern

Slide 23
 Small Phased Array Animation

Variables are set up for the four ports.

In this simple example, the ports toggle
between 0 and 135° in a set pattern,
based on the variable FeedControl.

Slide 24
 Corporate Fed Array
A “corporate” array is a popular configuration
Feed structure can affect performance
Methods of analysis
Infinite array
Finite array without feed
Finite array with feed

Slide 25
 Corporate Feed Patch Geometry
Assume 4-Unit Cell Wpatch
Recessed Slot Patch
Patch dimensions
Calculated previously dx

Variable number of patches

Lf1

dy

WSlot

LSlot

(0,0)
W100

Slide 26
 Corporate Array Dimensions
Fully Parameterized
n
2 Unit Cells
Square Array
Single Feed Point
Patch may be any
dimension
VBScript Generation

Slide 27
 Patch Geometry
This patch was created
with a VB script, located
in appendix

Quarter Wave transformer

sections. Width and length
parameterized for user
optimization

Slide 28
 Corporate Fed 8X8 Array
Solution Details
21,267 Unknowns
343M Ram

13 Minutes

Slide 29
 Corporate Fed 8X8 Array Details
Solution Plots

Slide 30
 Corporate Fed 16X16 Array
Solution Details
86,428 Unknowns
121M Ram
2 Hours, 54 Minutes

Slide 31
 Corporate Fed 16X16 Solutions

Slide 32
 Patch as an Infinite array

Slide 33
 System Co-simulation

Slide 34
 Circuit, System and EM Cosimulation

Slide 35
 Conclusion
An improved design flow for systems with
patch antennas has been presented
Advanced features
Parameterization
Solver On Demand
Co-Simulation
Optimization
Graphics and plotting
Field and geometry plots and animations
Integration with system and circuit tool

Slide 36
 Appendix: Patch Arrays

Patches can be arranged various Arrays

Two examples will be shown
“Linear” array
Both x- and y- patches variable
Corporate Array
Arrays will be built with previous patches
100Ω impedance

Slide 37
 Appendix: Linear Array
“Patch” antenna with feed
The “wide” sections are “patches”, narrow sections are the feeds
The lengths of the patches are equal
The lengths of the feeds are equal
The widths of the patches can vary to form a “beam”
The number of patches can be large
Up to 16 patches

Patch “n”
dx

W03

W02 Wn
W01

Wfeed
Lpatch

Slide 38
 Appendix: Design Procedure
1. Determine Geometry and parameters
2. Create parameterized footprint
3. Create circuit equivalent
4. Create symbol
5. Generate component

Once this
Once this isis done
done the
the user
user has
has aa
flexible “Solver
flexible “Solver on on Demand”
Demand”
component that
component that can
can bebe used
used asas aa
versatile “stand
versatile “stand alone”
alone” design
design oror as
as
part of
part of aa larger
larger scale
scale circuit
circuit or
or system
system
design.
design.

Slide 39
 Appendix: Important Linear Patch Parameters
A component can be set up with
the following parameters:

Lpatch
W1 to W16
WFeed
dx
n

These parameters fully define the

patch element

Slide 40
 Appendix: Component Description
The Linear Patch will consist of:
Component
Represents the overall patch
Contains parameters, circuit equivalent
Footprint
Contains geometry information
Can be scripted in VB or Java
Symbol
Schematic representation of patch

Slide 41
 Appendix: Determine Footprint Geometry
Variables
Since “rectangle” objects are determined by Center “x” Point Chart
their center, width and height, the centers of A Reference, (0,0)
each of the patches/feeds will be determined. B Lfeed/2+Lpatch/2
C Lfeed+Lpatch
D (3/2)*Lfeed+(3/2)*Lpatch
E 2*Lfeed+2*Lpatch
F (5/2)*Lfeed+(5/2)*Lpatch
Lpatch
Y (n-.5)*(Lfeed+Lpatch)
Z n*(Lfeed+Lpatch)
dx

B C D E F Y Z

A
Lfeed = dx-Lpatch

Slide 42
 Appendix: Creating a Footprint

dx

Slide 43
 Appendix: Create Footprint Script Part 1
The script is broken into two parts for clarity
The first part sets up variables
The second part is the actual code
Note that the code section is only a few lines
One loop

‘Script Part 1 Defining all Variables Width(6) = LayoutHost.Pars.Item("W06")

Dim W1, W2, W3, W4, W5, W6, W7, W8 Width(7) = LayoutHost.Pars.Item("W07")
Dim W9, W10, W11, W12, W13, W14, W15, W16 Width(8) = LayoutHost.Pars.Item("W08")
Dim Lpatch, Lfeed, idnum, x, n, pi, pointsvar, width(20) Width(9) = LayoutHost.Pars.Item("W09")
set Pointsvar = LayoutHost.CreatePointsObject() Width(10) = LayoutHost.Pars.Item("W10")
pi = 3.1415926535 Width(11) = LayoutHost.Pars.Item("W11")
n = LayoutHost.Pars.Item("n") Width(12) = LayoutHost.Pars.Item("W12")
Lpatch = LayoutHost.Pars.Item("Lpatch") Width(13) = LayoutHost.Pars.Item("W13")
Wfeed = LayoutHost.Pars.Item("Wfeed") Width(14) = LayoutHost.Pars.Item("W14")
dx= LayoutHost.Pars.Item("dx") Width(15) = LayoutHost.Pars.Item("W15")
Width(16) = LayoutHost.Pars.Item("W16")
Width(1) = LayoutHost.Pars.Item("W01") Lfeed = LayoutHost.LayoutPars.Item("Lfeed")
Width(2) = LayoutHost.Pars.Item("W02") idnum = LayoutHost.GetLayerID("anywhere")
Width(3) = LayoutHost.Pars.Item("W03")
Width(4) = LayoutHost.Pars.Item("W04")
Width(5) = LayoutHost.Pars.Item("W05")

Slide 44
 Appendix: Create Footprint Script part 2
‘MainVB
‘Main VBScript
ScriptJust
Justaafor/
for/Next
NextLoop
Loopwith
withincremental
incrementalParameters!
Parameters!

‘Createaa“Points”
‘Create “Points”object
objecttotoDraw
DrawFirst
Firstline
line
pointsvar.Add (-1*lfeed/2),(width(1))
pointsvar.Add (-1*lfeed/2),(width(1))
pointsvar.Add (n*(Lpatch+Lfeed)+lfeed/2),(Width(1))
pointsvar.Add (n*(Lpatch+Lfeed)+lfeed/2),(Width(1))
‘DrawFirst
‘Draw Firstline
line
layouthost.NewRectidnum,
layouthost.NewRect idnum,0,0,0,0,Lfeed,Wfeed,
Lfeed,Wfeed,00

‘MainLoop
‘Main Loop
forxx==11totonn
for

‘DrawPatches
‘Draw Patches
layouthost.NewRectidnum,
layouthost.NewRect idnum,(x-.5)*(Lpatch+Lfeed),0,
(x-.5)*(Lpatch+Lfeed),0,Lpatch,width(x),0
Lpatch,width(x),0

‘DrawFeeds
‘Draw Feeds
layouthost.NewRectidnum,
layouthost.NewRect idnum,(x)*(Lpatch+Lfeed),0,
(x)*(Lpatch+Lfeed),0,Lfeed,Wfeed,0
Lfeed,Wfeed,0

next
next

‘ManipulatPorts
‘Manipulat Ports
LayoutHost.MovePort"n1",
LayoutHost.MovePort "n1",-1*lfeed/2,0,
-1*lfeed/2,0,pipi
LayoutHost.MovePort"n2",
LayoutHost.MovePort "n2",n*(Lpatch+Lfeed)+lfeed/2,0,
n*(Lpatch+Lfeed)+lfeed/2,0,00

Slide 45
 Appendix: Create Circuit Equivalent
A simple circuit equivalent could be made
Electromagnetic simulation is very fast
Largest problems
SVD Fast Solve
Low memory requirements
Geometries may get very large
Circuit equivalent is a good method to speed solution
Gives S-parameter equivalents
Demonstrates Designer’s flexibility

Slide 46
 Appendix: Equivalent Circuit
Purely optional
Some designers prefer electromagnetic analysis only
May consist of any circuit element
Can be as simple as a single resistor
Can be as complex as user can describe
Is formed as a “Netist” line

Slide 47
 Appendix: Netlist Basics
To complete the component, a Netlist line will be added
Circuit simulations run much faster than Planar EM simulations
It is desirable to have a circuit equivalent even if its just an approximation
Designer is a “Netlist” based program
All simulations run the engine through a netlist
This netlist is Spice compatible where applicable
The circuit geometry is similar to 3 to 33 “microstrip”
transmission lines
Transmission lines are well characterized within the circuit solver
Between each transmission line, there may be a “step
discontinuity”
The “circuit equivalent would look like:

Slide 48
 Appendix: Geometric Variable Setup
The “largest” structure (n=16) contains
16 patches and 17 Feeds : Total 33 Transmission lines
One “step discontinuity between each line
Total 32 Steps
The smallest Structure (n=1) contains:
1 patch, 2 feed lines, and 3 steps
Provisions must be made in the netlist to
“remove” components that are not used
Accomplished by setting “lengths” of the unused lines to
Lpatch/1000
“Widths” of the Unused transmission lines set to Wfeed
“Unused” transitions take care of themselves
“Worst case” (n=1)
Total of 30 lines “hanging” off end of the model
Total length of Lpatch *30/1000
This is an insignificant amount

Slide 49
 Appendix: Geometric Variable Setup
Variables We1 through we33 represent widths of each line
The “odd” numbers represent feeds
They will all have the width “wfeed”
The “even” numbers of Wexx represent patch widths
Dependent on the number of sections
16 sections, possibly 16 different width values
Case 1: n = 1
Second line (first patch) set to width We1
Remaining sections set to a width of Wfeed
Lengths are set to Lpatch/1000
Case 2: 1 < n <16
sections after the nth section are set to width Wfeed
Therefore Transmission line 2 (first patch) will always be set to We1
Lengths of the lines will be defined as L1 through L33
Depending on the value of n, these transmission lines will be set to a length
corresponding to the length of the patches & feeds, or set to a small value,
Lpatch/1000 as discussed
“If” statements will be used to define the lengths and widths

Slide 50
 Appendix: Typical Variable Property
The if statement in the netlist line will have the syntax
If (expression, true, false) or We32= if(n<16, wfeed, w16)

The @ character preceding a

variable name means that the
The variable We32 variable is a “passed
parameter” directly from the
component

We32@id= \{ if \( @n < 16 , @wfeed , @w16 \) \}

The variable We32@id (no Open and closed brackets surround an expression in the
space) is the syntax that tells netlist. Designer uses brackets for special functions, so In
designer to assign a unique order to netlist correctly, the backslash character must be put
identifier to the variable in front of the bracket or any other special character, such as
We32 parenthesis. This tells designer to netlist this character
directly.

Slide 51
 Appendix: Component Setup
Shown are the lines in the component and the netlist line
In the component, carriage returns are for visuals in this presentation, they will not
be in the component. The \n tells Designer to put carriage returns in the netlist
Designer puts the carriage returns in the netlist

Since it is a “multiple line” component, each component must have a unique ID. The
underscore following the @ID tells designer to assign it a unique ID, and each element
must have unique characters following the underscore. These can be alpha-numeric

MSTRL:@ID %0 %_101 w= @Wfeed p= \{ @dx - @Lpatch \} Sub=@sub \n

MSSTEP:@ID_ca %_101 %_1 W1= @Wfeed W2= @W01 sub=@sub \n Componenttext.
Component text. Note
Note
61 more “lines” thatthere
that therewill
willbe
beno
no
MSSTEP:@ID_bf %_132 %_32 W1= \{ We32@id \} W2= @wfeed sub=@sub \n carriagereturns.
returns.
MSTRL:@ID_af %_32 %1 w=@Wfeed p= \{ @dx - @Lpatch \} Sub=@sub carriage

The syntax for “defined” variables is different that that of the

passed parameters. We32 was defined previously, and as
explained, Designer assigned a unique ID to it. To reference
that variable in the netlist line, @id must follow the variable
name

MSTRL:1 Port1 inet_101 w= 10mil p= { 150mil - 50mil } Sub=Alumina

MSSTEP: inet_101 inet_1 W1= 10mil W2= 50mil sub=Alumina NetlistLine.
Netlist Line. Note
Notethat
that
62 more “lines” Designerputs
Designer putsinin
carriagereturns.
carriage returns.
MSSTEP: inet_132 inet_32 W1= { We321 } W2= 10mil sub=Alumina
MSTRL: inet_32 Port2 w=10mil p= { 150mil - 50mil } Sub=Alumina

Slide 52
 Appendix Linear Patch Script
Dim Lpatch, Lfeed, idnum, x, n, pi, if x=nx-2 then
pointsvar,feedline1,feedline2,feedline3 Feedline2.Add (cx+dx-w100/2-lambda4),(cy-lf1)
Dim width(20) Feedline2.Add (cx+dx+w100/2),(cy-lf1)
Sub ClearLines LayoutHost.NewLine FeedL, feedline2,W100, "corner", "flat"
Set Pointsvar = LayoutHost.CreatePointsObject() callisclearlines
'This routine will clear all feedlines and to be used after each
Set Feedline1= LayoutHost.CreatePointsObject()
line build end if
Set Feedline2= LayoutHost.CreatePointsObject() end Sub 'Draw patch
…..
Set Feedline3= LayoutHost.CreatePointsObject()
End Sub ' Clearlines
Set PatchOutline=LayoutHost.CreatePointsObject() for y = 0 to ny-1
'*****Draw Vertical Feeds
Sub DrawPatch(CenterZX,CenterZY)
pi = 3.1415926535 Feedline2.Add (-1*lambda4-w100),(y*dy-lf1+(w70-w100)/2)
Cx =CenterZX
nx = LayoutHost.Pars.Item("nx") Feedline2.Add (w100/2),(y*dy-lf1+(w70-w100)/2)
Cy =CenterZy
ny = LayoutHost.Pars.Item("ny") LayoutHost.NewLine Qwave, feedline2,W70, "corner", "flat"
n = LayoutHost.Pars.Item("n") Feedline2.Add (-1*lambda4-w100),(y*dy-lf1)
'Patch Drawing Subroutine, Cx and Cy are the coords
Lpatch = LayoutHost.Pars.Item("Lpatch") Feedline2.Add (-1*lambda4-w100-lf2),(y*dy-lf1)
PatchOutline.Add (cx-Wpatch/2),(cy)
Wfeed = LayoutHost.Pars.Item("Wfeed") LayoutHost.NewLine FeedL, feedline2,W100, "corner", "flat"
PatchOutline.Add (cx-Wpatch/2),(cy+Lpatch)
dx= LayoutHost.Pars.Item("dx")
PatchOutline.Add (cx+Wpatch/2),(cy+Lpatch)
dy= LayoutHost.Pars.Item("dy") if y<>0 then
PatchOutline.Add (cx+Wpatch/2),(cy)
lf1= LayoutHost.Pars.Item("lf1") Feedline2.Add (-1*lambda4-w100-lf2+w70/2),(y*dy-lambda4-lf1-w100/2)
PatchOutline.Add (cx+WCutout/2),(cy)
lf2= LayoutHost.Pars.Item("lf2") Feedline2.Add (-1*lambda4-w100-lf2+w70/2),(y*dy-lf1-w100/2)
PatchOutline.Add (cx+WCutout/2),(cy+Lcutout)
wf1= LayoutHost.Pars.Item("wf1") LayoutHost.NewLine Qwave, feedline2,W70, "corner", "flat"
PatchOutline.Add (cx+W100/2),(cy+Lcutout)
wf2= LayoutHost.Pars.Item("wf2") call clearlines
PatchOutline.Add (cx+W100/2),(cy)
W100= LayoutHost.Pars.Item("W100")
PatchOutline.Add (cx-W100/2),(cy)
W50= LayoutHost.Pars.Item("W50") Feedline2.Add (-1*lambda4-w100-lf2+w100/2),(y*dy-lambda4-lf1-w100/2)
PatchOutline.Add (cx-W100/2),(cy+Lcutout)
W70= LayoutHost.Pars.Item("W70") Feedline2.Add (-1*lambda4-w100-lf2+w100/2),((y-1)*dy-lf1+w100/2)
PatchOutline.Add (cx-Wcutout/2),(cy+Lcutout)
Lambda4= LayoutHost.Pars.Item("Lambda4") LayoutHost.NewLine FeedL, feedline2,W100, "corner", "flat"
PatchOutline.Add (cx-Wcutout/2),(cy)
Wcutout= LayoutHost.Pars.Item("WSlot") end if
LayoutHost.Newpoly idnum, Patchoutline
Lcutout= LayoutHost.Pars.Item("LSlot")
WPatch= LayoutHost.Pars.Item("WPatch") for x = 0 to nx-1
'*** Draw Horiz Feeds
Linput= LayoutHost.Pars.Item("Linput") Call drawpatch(dx*x,dy*y)
'LayoutHost.NewCircle idnum,cx,cy,(Wpatch/4)
Feedline2.Add (cx),(cy)
Lfeed = LayoutHost.LayoutPars.Item("Lfeed") next ‘nx
Feedline2.Add (cx),(cy-lf1)
idnum = LayoutHost.GetLayerID("anywhere") Next 'ny
, W50 '***Draw input Feed
if x<>nx-1 then
Feedline2.Add (-1*lambda4-w100-lf2+w100/2)-w100/2,(-lf1-w100/2+w50/2)
Feedline2.Add (cx+dx-w100/2-lambda4),(cy-lf1)
Feedline2.Add (-1*lambda4-w100-lf2+w100/2)-linput-w100/2,(-lf1-w100/2+w50/2)
end if
LayoutHost.NewLine idnum, feedline2,W50, "corner", "flat"
LayoutHost.NewLine FeedL, feedline2,W100, "corner", "flat"
call clearlines
' Manipulate Port
LayoutHost.MovePort "n1", (-1*lambda4-w100-lf2+w100/2)-linput-w100/2,(-lf1-
w100/2+w50/2), pi
LayoutHost.SetPortWidth idnum, "n1", W50
Slide 53